Wafer test equipment

Abstract

The present application provides a wafer testing device for testing a wafer to be tested, wherein the wafer to be tested has a plurality of light-emitting units. The wafer testing device comprises a wafer testing carrier and a soft conductive layer. The wafer testing carrier has a first surface, and a plurality of detection units are arranged on the first surface. The soft conductive layer is detachably arranged on the first surface, and the soft conductive layer is conductive in the vertical direction and non-conductive in the horizontal direction. When testing the wafer to be tested, the wafer to be tested is placed on the soft conductive layer, and each light-emitting unit in the vertical direction is electrically connected to one of the plurality of detection units via the soft conductive layer.

Description

Technical Field

[0001] The present application relates to a testing device for a light emitting unit, and more particularly to a testing device for testing a light emitting unit in a wafer. Background Art

[0002] With the development of laser technology, laser diodes can be used in reading and writing data, communication, emitting light, measuring distance or sensing various objects, etc., and their uses are very wide. In order to ensure the quality of laser diodes when they are shipped, it is necessary to light up the laser diodes during testing and detect whether the various photoelectric parameters of the laser diodes are normal. Generally speaking, laser diodes are manufactured using semiconductor processes. Basically, laser diodes can be divided into two types: edge emitting and surface emitting. Recently, surface emitting laser diodes have become the type with the largest production volume because their structure and characteristics meet market demand. Flip chip is a structure of semiconductor wafers, in which the external electrodes are made on the reverse side of the epitaxial layer. During packaging, the die bonding and packaging electrode connections can be completed at the same time, saving the cost and time of traditional wire bonding.

[0003] In the future, flip chip surface emitting laser diodes will become cheap and widely used optoelectronic components, and the market is promising. However, the production of any semiconductor component must be inspected and screened. The characteristics of laser diodes are greatly related to temperature. Different from traditional non-flip chip laser diodes, there is no reliable and effective mass production architecture for flip chip surface emitting laser diode testing. The goal of this application is to propose a fast, effective, low-cost, high-reliability test architecture with temperature control function to solve the wafer testing problem. Summary of the invention

[0004] In view of this, the present application proposes a wafer testing device, in which a plurality of detection parts are arranged on a wafer testing carrier, and a plurality of light-emitting units on the wafer to be tested can be directly electrically connected to the plurality of detection parts, so that there is no need to contact the light-emitting surface of the wafer to be tested. In addition, a soft conductive layer is further arranged on the wafer testing carrier, and the soft conductive layer can be in close contact with the surfaces of various light-emitting units, so as to avoid problems in electrical connection caused by uneven surfaces of the light-emitting units. Therefore, the wafer testing device of the present application can more efficiently detect the light-emitting units on the wafer to be tested.

[0005] The present application provides a wafer testing device for testing a wafer to be tested, wherein the wafer to be tested has a plurality of light-emitting units. The wafer testing device comprises a wafer testing carrier and a soft conductive layer. The wafer testing carrier has a first surface, and a plurality of detection units are arranged on the first surface. The soft conductive layer is detachably arranged on the first surface, and the soft conductive layer is conductive in the vertical direction and non-conductive in the horizontal direction. When testing the wafer to be tested, the wafer to be tested is placed on the soft conductive layer, and each light-emitting unit in the vertical direction is electrically connected to one of the plurality of detection units via the soft conductive layer.

[0006] In some embodiments, each detection part may have a first conductive member and a second conductive member, and the plurality of detection parts may be arranged into a first array, wherein in the detection parts in the same row of the first array, the first conductive members of adjacent detection parts are electrically connected to each other, and in the detection parts in the same column of the first array, the second conductive members of adjacent detection parts are electrically connected to each other. In addition, each detection part may correspond to one of the plurality of light-emitting units, and the first conductive member of each detection part is electrically connected to the first contact pad of the corresponding light-emitting unit via the soft conductive layer, and the second conductive member of each detection part is electrically connected to the second contact pad of the corresponding light-emitting unit via the soft conductive layer. In addition, the wafer testing device may further include a temperature control component, the temperature control component is adjacent to the second surface of the wafer testing carrier, the second surface is relative to the first surface, and the temperature control component is used to increase or decrease the temperature of the wafer testing carrier. Moreover, the soft conductive layer has a good thermal conductivity.

[0007] In some embodiments, the wafer test carrier may further have a plurality of exhaust holes, the plurality of exhaust holes are arranged in a second array, and one end of the plurality of exhaust holes is exposed to the first surface. In addition, the soft conductive layer may have a plurality of through holes, the plurality of through holes are arranged in a second array, and each through hole corresponds to one of the plurality of exhaust holes. In addition, the wafer testing device may further include an exhaust module, the exhaust module is connected to the plurality of exhaust holes, and gas is extracted from the plurality of exhaust holes according to an exhaust instruction. And, the wafer testing device may further include an airtight box and a pressurizing module, at least the wafer test carrier and the soft conductive layer are arranged in the accommodation space of the airtight box, and the pressurizing module is used to pressurize the accommodation space so that the air pressure value of the accommodation space is greater than 1atm.

[0008] In some embodiments, the wafer testing device may further include an optical detection module, a horizontal movement module and a processing module. The optical detection module may have a light receiving portion for receiving light to generate a detection result. The horizontal movement module may be controlled by a movement instruction to move the wafer test carrier so that one of the multiple detection portions is aligned with the light receiving portion of the optical detection module. The processing module may electrically connect the wafer test carrier, the optical detection module and the horizontal movement module to execute a detection program to generate a movement instruction and receive the detection result. In addition, when testing the wafer to be tested, the non-light-emitting surface of the wafer to be tested may contact the soft conductive layer.

[0009] The present application also provides another wafer testing device for testing a wafer to be tested, wherein the wafer to be tested has a plurality of light-emitting units. The wafer testing device comprises a wafer testing carrier and a soft conductive layer. The wafer testing carrier has a first surface and a plurality of exhaust holes, wherein a plurality of detection parts are arranged on the first surface, wherein each detection part has a first conductive part and a second conductive part, wherein one end of each exhaust hole is exposed to the first surface, wherein the plurality of detection parts are arranged in a first pattern, and wherein the plurality of exhaust holes are arranged in a second pattern. The soft conductive layer is detachably arranged on the first surface, wherein the soft conductive layer is conductive in a vertical direction and non-conductive in a horizontal direction. The soft conductive layer has a plurality of through holes, wherein the plurality of through holes are arranged in a second pattern, and wherein each through hole corresponds to one of the plurality of exhaust holes. Each exhaust hole has at least a first distance from an adjacent first conductive part or a second conductive part, and each exhaust hole has at least a second distance from another adjacent exhaust hole, wherein the first distance is less than or equal to the second distance.

[0010] In summary, the wafer testing device provided by the present application can directly detect a large number of light-emitting unit dies on the wafer to be tested without contacting the light-emitting surface of the wafer to be tested. In addition, the wafer testing device provided by the present application has a soft conductive layer, and the light-emitting unit can be electrically connected to the detection unit via the soft conductive layer, which can overcome the problem of poor contact. In addition, the temperature control component provided by the present application can make the wafer to be tested on the wafer test carrier operate at a standardized temperature.

[0011] The details of other effects and embodiments of the present application are described as follows with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1Ais a functional block diagram of a wafer testing device according to an embodiment of the present application;

[0014] Figure 1B is a structural schematic diagram of a portion of a wafer testing device according to an embodiment of the present application;

[0015] Figure 2 is a top view schematic diagram of a wafer test carrier according to an embodiment of the present application;

[0016] Figure 3A is a top view schematic diagram of a portion of a detection unit according to an embodiment of the present application;

[0017] Figure 3B is a functional block diagram of a part of a detection unit according to an embodiment of the present application;

[0018] Figure 4 is a top view schematic diagram of a wafer test carrier according to another embodiment of the present application;

[0019] Figure 5A is a top view schematic diagram of a wafer test carrier according to yet another embodiment of the present application;

[0020] Figure 5B is based on Figure 5A The embodiment of the present invention is a schematic top view of a part of the detection unit;

[0021] Figure 6 is a structural schematic diagram of a portion of a wafer testing device according to yet another embodiment of the present application;

[0022] Figure 7 is a top view schematic diagram of a wafer test carrier according to another embodiment of the present application;

[0023] Figure 8 FIG. 4 is a top view of a wafer testing carrier according to another embodiment of the present application.

[0024] Explanation of symbols

[0025] 1 Wafer test device 10 Wafer test carrier

[0026] 11 soft conductive layer 12 optical detection module

[0027] 13 Temperature control component 14 Horizontal movement module

[0028] 15 airtight box 16 processing module

[0029] 17 Pressurization module 18 Vacuum module

[0030] 19-carrier DUT wafer to be tested

[0031] 2 Wafer test carrier 20 first surface

[0032] 200, 200a, 200b, 200c, 200d detection unit

[0033] 202a, 202b, 202c, 202d first conductive element

[0034] 204a, 204b, 204c, 204d second conductive element

[0035] 206 first driving circuit 208 second driving circuit

[0036] 4 Wafer test carrier 40 first surface

[0037] 400 detection unit 40a positioning unit

[0038] 5 Wafer test carrier 50 first surface

[0039] 500, 500a detection part 502a first conductive member

[0040] 504a second conductive member 506, 506a air extraction hole

[0041] 60 wafer test tray 600 exhaust holes

[0042] 61 soft conductive layer 610 through hole

[0043] 63 temperature control assembly 65 airtight box

[0044] 69 stage 690 exhaust pipe

[0045] 692 pipeline 7, 8 wafer test carrier

[0046] 70, 80 first surface 700, 800 detection unit

[0047] 706, 806 exhaust hole DETAILED DESCRIPTION

[0048] The aforementioned and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only the directions with reference to the accompanying drawings. Therefore, the directional terms used are used to illustrate and not to limit the present application.

[0049] See also Figure 1A , Figure 1A FIG. 2 is a functional block diagram of a wafer testing device according to an embodiment of the present application. Figure 1AAs shown, the wafer testing device 1 is used to test the wafer DUT to be tested, and the wafer DUT to be tested has a plurality of light-emitting units (not shown). Here, the wafer DUT to be tested may have a plurality of dies that have not been wafer diced, and each die may be one or more light-emitting units. The light-emitting unit may be, for example, a laser diode (LD) with a flip chip structure, such as a vertical cavity surface emitting laser (VCSEL). In other words, the light-emitting unit of this embodiment may emit light toward a light-emitting surface, and the side of the light-emitting unit opposite to the light-emitting surface may have a contact pad to receive a driving signal.

[0050] In practice, the light-emitting unit has at least two contact pads. Taking a laser diode as an example, the two contact pads may be the anode and cathode of the laser diode, respectively. In addition, the wafer DUT to be tested may be defined with an upper surface and a lower surface. The upper surface may be the light-emitting surface of the light-emitting unit in the wafer DUT to be tested, and the lower surface may be the side surface opposite to the light-emitting surface, and the contact pads of each light-emitting unit may be exposed on the lower surface. A person with ordinary knowledge in the relevant technical field should be able to understand the meaning of the light-emitting surface. The present embodiment does not limit the light-emitting unit to only emit light from the light-emitting surface. In an example, the light-emitting unit may emit most of the light from the light-emitting surface, but the light-emitting unit may leak light from the side surface other than the light-emitting surface, so that light may also be visible on the lower surface of the wafer DUT to be tested.

[0051] The wafer testing device 1 may include a wafer testing carrier 10, a soft conductive layer 11, an optical detection module 12, a temperature control component 13, a horizontal movement module 14, an airtight box 15, a processing module 16, a pressurizing module 17, and an exhaust module 18. The processing module 16 is electrically connected to the wafer testing carrier 10, the optical detection module 12, the temperature control component 13, the horizontal movement module 14, the pressurizing module 17, and the exhaust module 18. The wafer testing carrier 10 is used to carry the soft conductive layer 11 and the wafer DUT to be tested so as to perform a detection procedure on the wafer DUT to be tested. Here, the wafer testing carrier 10 may be placed on a carrier (not shown). Figure 1A), and the surface (first surface) on one side of the wafer test carrier 10 can be used to contact the soft conductive layer 11. The soft conductive layer 11 does not necessarily need to be fixed on the wafer test carrier 10. For example, the soft conductive layer 11 is detachably arranged on the first surface. In practice, the soft conductive layer 11 can be composed of a piece of soft insulating material, and a large number of metal wires are vertically penetrated in the insulating material, so that the soft conductive layer 11 can be conductive in the vertical direction but not conductive in the horizontal direction. Those with general knowledge in the relevant technical field should understand that when the wafer DUT to be tested is placed on the soft conductive layer 11, any position on the wafer DUT to be tested will be electrically connected to the corresponding position of the wafer test carrier 10 directly below through the soft conductive layer 11. In addition, unlike directly placing the wafer DUT to be tested on the first surface of the wafer test carrier 10, the wafer DUT to be tested may not be able to fit tightly to the first surface of the wafer test carrier 10 because the surface of the wafer DUT to be tested is uneven. Since the soft conductive layer 11 of the present embodiment is not made of a hard material, even if the surface of the wafer DUT to be tested is uneven, the wafer test carrier 10 can contact the wafer DUT to be tested more efficiently through the soft conductive layer 11 .

[0052] Since the soft conductive layer 11 has been installed on the wafer test carrier 10, when the wafer DUT to be tested is correctly placed on the soft conductive layer 11, the wafer DUT to be tested is also carried by the wafer test carrier 10. The processing module 16 can drive the horizontal movement module 14 to perform positioning and calibration of the wafer DUT to be tested according to different detection areas on the wafer DUT to be tested. In other words, the processing module 16 can be electrically connected to the horizontal movement module 14 and generate a movement instruction, the horizontal movement module 14 moves the carrier according to the movement instruction, and the carrier is linked to the wafer test carrier 10, so that the wafer DUT to be tested carried on the wafer test carrier 10 moves together.

[0053] In one example, if the wafer testing device 1 is to test a specific light-emitting unit on the wafer DUT to be tested, the horizontal moving module 14 needs to move the carrier so that the carrier drives the wafer test carrier 10 and the wafer DUT to be tested, so that the specific light-emitting unit on the wafer DUT to be tested can be aligned with the optical detection module 12. Preferably, the specific light-emitting unit on the wafer DUT to be tested can be aligned with the light receiving part (not shown) of the optical detection module 12, so that after the specific light-emitting unit on the wafer DUT to be tested is driven or lit, the light generated by the specific light-emitting unit can vertically enter the light receiving part to avoid the light from being scattered and affecting the detection result. In a practical example, the optical detection module 12 can be an integrating sphere, which is used to receive the light generated by the light-emitting unit on the wafer DUT to be tested to generate a digital detection result. In this way, the processing module 16 can analyze whether the specific light-emitting unit emits light correctly and stably based on the detection result provided by the optical detection module 12 to determine whether the specific light-emitting unit is working properly.

[0054] On the other hand, the present embodiment does not limit the means by which the horizontal moving module 14 drives the carrier. For example, the horizontal moving module 14 may have a track, and the carrier is fixed on the track, so that the horizontal moving module 14 can pull or push the carrier. Because the wafer DUT to be tested is placed on the wafer test carrier 10, when the horizontal moving module 14 moves the carrier according to the movement instruction of the processing module 16, the wafer DUT to be tested can of course move with the wafer test carrier 10 and the carrier. In the detection procedure, the horizontal moving module 14 of the present embodiment only needs to move the carrier and the wafer test carrier 10 on a horizontal plane, and does not need to move vertically, and the horizontal plane can be roughly parallel to the light-emitting surface of the wafer DUT to be tested. It is known to those with general knowledge in the relevant technical field that if the carrier and the wafer test carrier 10 do not need to be moved vertically, the steps of refocusing or adjusting the optical path of the optical detection module 12 can be eliminated.

[0055] In addition, a wafer test carrier 10 can be set on one side of the carrier, and the surface of the other side can be used to contact the temperature control component 13. In other words, the temperature control component 13 and the wafer DUT to be tested will be located on the opposite sides of the wafer test carrier 10, that is, the surface (second surface) of the other side of the wafer test carrier 10 will be adjacent to the temperature control component 13. For example, the first surface of the wafer test carrier 10 contacts the wafer DUT to be tested, and the second surface of the wafer test carrier 10 contacts the carrier. Here, the temperature control component 13 can be connected to the processing module 16 with an electric wire and controlled by the processing module 16. In addition, the temperature control component 13 can be heated using a heater of a resistor or an active component, and the temperature control component 13 can also be cooled using a thermoelectric cooler. There are many ways to heat or cool, and this embodiment is not limited thereto. For example, liquid or gas can also be used to heat or cool. It is known to those skilled in the art that when the temperature control component 13 is heated or cooled, the temperature of the wafer test carrier 10 can be adjusted by heat conduction because the temperature control component 13 contacts the second surface of the wafer test carrier 10. Thus, the soft conductive layer 11 in contact with the first surface of the wafer test carrier 10 and the wafer DUT under test can also change temperature by heat conduction.

[0056] In practice, the temperature control component 13 of this embodiment can control the temperature of the wafer DUT to be tested. For example, the processing module 16 can use a temperature detector (not shown) to detect the temperature of the wafer DUT to be tested. When the temperature measured by the wafer DUT to be tested is too high, the processing module 16 can start the temperature control component 13 (such as a thermoelectric cooling component) to cool it down. On the contrary, when the temperature measured by the wafer DUT to be tested is too low, the processing module 16 can start the temperature control component 13 (such as a heater of a resistor or active component) to heat it up. The temperature detector can be set on the carrier, for example, and this embodiment is not limited. Thereby, through the heat conduction between the temperature control component 13 and the carrier, the wafer test carrier 10, the soft conductive layer 11 and the wafer DUT to be tested on the carrier can maintain a constant temperature. In actual operation, it is often necessary to detect the photoelectric characteristics of the light-emitting unit in the wafer DUT under test at various temperatures. The processing module 16 can set the temperature control component 13 to maintain multiple different temperatures. For example, the processing module 16 can set the temperature control component 13 to maintain at 25 degrees, 50 degrees or 70 degrees.

[0057] In addition, the wafer testing device 1 may further include an airtight box 15, a pressurizing module 17 and an exhaust module 18. The airtight box 15 may be used to accommodate the wafer testing carrier 10, the soft conductive layer 11, the temperature control component 13 and the wafer DUT to be tested. Figure 1A and Figure 1B , Figure 1B1 is a schematic diagram of the structure of a partial wafer testing device according to an embodiment of the present application. As shown in the figure, the wafer test carrier 10, the soft conductive layer 11, the temperature control component 13, the carrier 19 and the wafer DUT to be tested can be accommodated in the interior (accommodation space) of the airtight box 15. The pressurizing module 17 is used to increase the air pressure in the accommodation space of the airtight box 15. In one example, the pressurizing module 17 is not arranged in the accommodation space, for example, it is connected to the accommodation space of the airtight box 15 by a gas pipeline. The exhaust module 18 is used to extract the air between the wafer DUT to be tested and the soft conductive layer 11. Preferably, the exhaust module 18 can extract the air between the wafer DUT to be tested and the soft conductive layer 11 to near vacuum. For another example, the exhaust module 18 is not arranged in the accommodation space, for example, the exhaust module 18 can be connected to the wafer DUT to be tested and the soft conductive layer 11 by a gas pipeline. In an example, the wafer testing device 1 tightly presses the wafer DUT to be tested onto the soft conductive layer 11 through the cooperation of the soft conductive layer 11, the pressurizing module 17 and the exhaust module 18, so that the wafer testing carrier 10 can contact the wafer DUT to be tested more efficiently through the soft conductive layer 11.

[0058] For example, if there is no airtight box 15, the ambient pressure is generally about 1 atmosphere (1atm). If the exhaust module 18 extracts the space between the wafer DUT and the soft conductive layer 11 to a near vacuum, it can be seen that the difference between the wafer DUT and the soft conductive layer 11 and the outside is 1atm, that is, the wafer DUT will be subjected to a pressure of 1.0336 kilograms per square centimeter (1.0336kgw / cm 2 ) is pressed against the soft conductive layer 11. The conductive impedance of the soft conductive layer 11 is related to the pressure. Insufficient pressure will cause the conductive impedance to be too high and affect the correctness of the test. Although the soft conductive layer 11 can still adhere to the surface of the wafer DUT to be tested, under certain test conditions, especially high current testing, appropriate pressure must be applied to reduce the conductive impedance to an acceptable range in order to produce correct test results.

[0059] In accordance with the above, if there is an airtight box 15, the pressurizing module 17 can pressurize the inside of the airtight box 15 to exceed the ambient pressure, for example, to make the pressure value of the accommodating space greater than 1atm. For example, if the pressurizing module 17 can pressurize the inside of the airtight box 15 to 5atm, at this time, if the exhaust module 18 extracts the space between the wafer DUT to be tested and the soft conductive layer 11 to near vacuum, it can be known that the difference between the wafer DUT to be tested and the soft conductive layer 11 and the outside is 5atm, that is, the wafer DUT to be tested will be subjected to a pressure of 5.168 kilograms per square centimeter (5.168kgw / cm 2) is pressed toward the soft conductive layer 11. Obviously, by pressing the wafer DUT to be tested more tightly against the soft conductive layer 11, the wafer test carrier 10 can contact the wafer DUT to be tested more efficiently through the soft conductive layer 11. In practice, the degree of pressure of the pressure module 17 can also be freely adjusted, for example, engineers can set different pressure instructions. If the surface flatness of the wafer DUT to be tested is poor, the degree of pressure of some pressure modules 17 can be increased through pressure instructions during operation, so that the pressure per square centimeter of the wafer DUT to be tested is increased. For another example, if the surface flatness of the wafer DUT to be tested is good, the degree of pressure of some pressure modules 17 can be reduced through pressure instructions during operation, so that the pressure per square centimeter of the wafer DUT to be tested is reduced. Of course, the degree of pressure of the pressure module 17 is also related to the conductive impedance of the soft conductive layer 11. It is known to those skilled in the art that if the wafer DUT to be tested is simply placed on the soft conductive layer 11, even if the wafer DUT to be tested is electrically connected to the soft conductive layer 11, the conductive impedance between the wafer DUT to be tested and the soft conductive layer 11 is still relatively high. In order to reduce the conductive impedance of the soft conductive layer 11, the pressurizing module 17 should be appropriately pressurized to press the wafer DUT to be tested against the soft conductive layer 11.

[0060] In addition, the exhaust module 18 is controlled by the exhaust command of the processing module 16. When the exhaust module 18 receives the exhaust command and starts to exhaust, the space between the wafer DUT to be tested and the soft conductive layer 11 is evacuated to near vacuum, so that the wafer DUT to be tested can be adsorbed on the soft conductive layer 11 and the wafer test carrier 10. In this way, when the wafer test carrier 10 is moved, unnecessary shaking or deviation of the wafer DUT to be tested can be avoided. Taking a practical example, when the wafer test device 1 is in the detection state, the exhaust module 18 should keep exhausting so that the wafer DUT to be tested can be firmly adsorbed on the soft conductive layer 11 and the wafer test carrier 10, and when the wafer test device 1 is in the non-detection state, the exhaust module 18 can stop exhausting so that the staff can replace or adjust the wafer DUT to be tested.

[0061] In order to more clearly illustrate the structure of the wafer test carrier, this embodiment specifically draws the wafer test carrier separately. Figure 2 as well as Figure 3A , Figure 2 FIG. 1 is a top view schematic diagram of a wafer test carrier according to an embodiment of the present application. Figure 3AIt is a schematic top view of a part of the detection part according to an embodiment of the present application. As shown in the figure, the wafer test carrier 2 of the present embodiment may have a first surface 20, and the first surface 20 is provided with a plurality of detection parts 200. In an example, the wafer test carrier 2 may be a plate body, which is placed on a carrier. When carrying the wafer DUT to be tested, the first surface 20 of the wafer test carrier 2 may face the lower surface of the wafer DUT to be tested, and the plurality of detection parts 200 may correspond to a plurality of light-emitting units. In practice, the wafer test carrier 2 may change with the wafer to be tested. For example, different wafers to be tested may use different wafer test carriers, or new wafer test carriers may be designed according to the wafer to be tested.

[0062] In one example, each detection unit 200 corresponds to a light-emitting unit. In other words, if multiple light-emitting units in the wafer DUT to be tested are arranged into a first array, then multiple detection units 200 in the wafer test carrier 2 will also be arranged into a first array, but the present application does not limit the detection unit 200 and the light-emitting unit to a one-to-one correspondence. In another example, multiple detection units can also correspond to only certain light-emitting units in an area, sampling and detecting some of the light-emitting units in the wafer to be tested, rather than detecting every light-emitting unit.

[0063] When the plurality of inspection units 200 in the wafer test carrier 2 are arranged into a first array, for the convenience of description, Figure 3A For example, there are detection parts 200a, detection parts 200b, detection parts 200c and detection parts 200d. Detection parts 200a and detection parts 200b may be, for example, located in the same column of the first array, detection parts 200c and detection parts 200d may be, for example, located in the same column of the first array, detection parts 200a and detection parts 200c may be, for example, located in the same row of the first array, and detection parts 200b and detection parts 200d may be, for example, located in the same row of the first array, so that detection parts 200a, detection parts 200b, detection parts 200c and detection parts 200d are arranged in a 2x2 array.

[0064] In practice, the plurality of detection units 200 may be arranged into a plurality of arrays, for example Figure 2The multiple detection units 200 can be divided into one 5x11 array, two 3x5 arrays, four 2x1 arrays and four 1x1 arrays. As long as the detection units 200 in each array can correspond to the light-emitting units of the wafer to be tested, they should all fall within the scope of this embodiment. From another perspective, the multiple detection units 200 do not necessarily need to be arranged in an array, and can also be arranged in one or more specific patterns. Similarly, as long as the detection units 200 in the pattern can correspond to the light-emitting units of the wafer to be tested, they should all fall within the scope of this embodiment. It is worth mentioning that even if a small number of detection units 200 do not correspond to the light-emitting units of the wafer to be tested, as long as these detection units 200 that do not correspond to the light-emitting units do not cause failure or damage to the detection program, or these detection units 200 that do not correspond to the light-emitting units can be easily bypassed, they should still fall within the scope of simple variations of this embodiment.

[0065] by Figure 3A For example, one of the detection parts 200a is shown in the example. The detection part 200a may include a conductive member 202a (or a first conductive member) and a conductive member 204a (or a second conductive member). The conductive member 202a and the conductive member 204a may correspond to two contact pads of the same light-emitting unit in the wafer DUT to be tested. For example, the conductive member 202a may correspond to the contact pad of the anode, and the conductive member 204a may correspond to the contact pad of the cathode. Thus, when the detection part 200a is driven, the conductive member 202a may pass the driving current through the soft conductive layer (not shown). Figure 3A ) is fed into the anode of the corresponding light-emitting unit, and the driving current leaving the cathode of the light-emitting unit is received by the conductive member 204a through the soft conductive layer, forming a complete current loop. Of course, this embodiment only illustrates the corresponding relationship between the conductive member in the detection unit and the contact pad in the light-emitting unit. The conductive member 202a may also correspond to the contact pad of the cathode, and the conductive member 204a may also correspond to the contact pad of the anode. As long as the detection unit corresponds to one light-emitting component and the two conductive members correspond to different contact pads, this embodiment does not limit the first conductive member and the second conductive member to correspond to the anode or cathode.

[0066] In one example, in the same array, the first conductive elements of the detection units in the same row are electrically connected to each other, and the second conductive elements of the detection units in the same column are electrically connected to each other. In other words, since the detection unit 200a and the detection unit 200c are located in the same row of the first array, the conductive element 202a of the detection unit 200a and the conductive element 202c of the detection unit 200c can be electrically connected to each other. And, since the detection unit 200a and the detection unit 200b are located in the same column of the first array, the conductive element 204a of the detection unit 200a and the conductive element 204b of the detection unit 200b can be electrically connected to each other. Similarly, the conductive element 202b of the detection unit 200b and the conductive element 202d of the detection unit 200d can be electrically connected to each other, and the conductive element 204c of the detection unit 200c and the conductive element 204d of the detection unit 200d can be electrically connected to each other.

[0067] In practice, in the detection process, the detection unit 200a, the detection unit 200b, the detection unit 200c and the detection unit 200d can be driven in a certain order. Figure 3A and Figure 3B , Figure 3B 1 is a functional block diagram of a part of the detection unit according to an embodiment of the present application. As shown in the figure, the wafer test carrier 2 can further have a first drive circuit 206 and a second drive circuit 208, the first drive circuit 206 can have a plurality of first ports (not shown), each of which can be electrically connected to a row of detection units, and the second drive circuit 208 can have a plurality of second ports (not shown), each of which can be electrically connected to a column of detection units.

[0068] by Figure 3B For example, the first (one of) first ports of the first driving circuit 206 can be connected to the detection unit 200a and the detection unit 200c, and in particular, electrically connected to the conductive member 202a and the conductive member 202c, while the second (another) first port of the first driving circuit 206 can be connected to the detection unit 200b and the detection unit 200d, and in particular, electrically connected to the conductive member 202b and the conductive member 202d. On the other hand, the first (one of) second ports of the second driving circuit 208 can be connected to the detection unit 200a and the detection unit 200b, and in particular, electrically connected to the conductive member 204a and the conductive member 204b, while the second (another) second port of the second driving circuit 208 can be connected to the detection unit 200c and the detection unit 200d, and in particular, electrically connected to the conductive member 204c and the conductive member 204d.

[0069] This embodiment does not limit whether the first driving circuit 206 and the second driving circuit 208 are disposed on the first surface 20. In one example, the first driving circuit 206 and the second driving circuit 208 can be disposed on the first surface 20 to avoid obstructing the placement of the wafer DUT on the opposite side of the first surface 20 (the second surface). In addition, the first driving circuit 206 and the second driving circuit 208 can not only be two separate physical circuits, but can also be integrated into the same chip in practice. In one example, if the wafer test device has Figure 1A When the exhaust module 18 receives the exhaust command and starts exhausting, the wafer DUT to be tested can be adsorbed on the wafer test carrier 2. In another example, an airtight structure (not shown) can be provided on the first surface 20. Figure 1A The soft conductive layer 11 can be substantially airtight with the first surface 20. When the wafer DUT to be tested is placed on the soft conductive layer and the first surface 20, the exhaust module 18 can smoothly extract the gas between the wafer DUT to be tested and the soft conductive layer, forming a negative pressure environment and pressing the wafer DUT to be tested toward the soft conductive layer and the first surface 20.

[0070] In actual operation, when the wafer test carrier 2 is to detect the light-emitting unit corresponding to the detection part 200a, it must first ensure that the light-emitting unit corresponding to the detection part 200a is in the correct position. In an example, the optical detection module is fixed, and only the wafer test carrier 2 can be moved by the horizontal movement module. At this time, the processing module can output a movement instruction to control the horizontal movement module based on the default coordinate parameters to move the light-emitting unit corresponding to the detection part 200a to just below the light receiving part of the optical detection module. Then, the processing module can control the first drive circuit 206 to output a drive signal to the first first port to turn on the conductive element 202a and the conductive element 202c, and the processing module can simultaneously control the second drive circuit 208 to output a drive signal to the first second port to turn on the conductive element 204a and the conductive element 204b. At this time, since the conductive element 202a and the conductive element 204a are turned on at the same time, the light-emitting unit corresponding to the detection part 200a is driven to generate light. After the light receiving part of the optical detection module receives the light generated by the light emitting unit, it can output the detection result for the processing module to make subsequent judgments. Here, other detection parts such as detection part 200c or detection part 200b, because two conductive parts are not turned on at the same time, the processing module will not mistakenly drive the light emitting unit corresponding to the detection part 200c or detection part 200b, so that the detection result will not be disturbed.

[0071] Of course, if the wafer test carrier 2 is to detect the light-emitting unit of the detection part 200b, the processing module can also output a movement instruction to control the horizontal movement module based on the preset coordinate parameters, and move the light-emitting unit corresponding to the detection part 200b to the bottom of the light receiving part of the optical detection module. It is known to those with ordinary knowledge in the relevant technical field that when the optical detection module remains stationary and only the wafer test carrier 2 is moved horizontally, the distance from the optical detection module to the light-emitting unit should remain the same, thereby saving the time for adjusting the optical path again. Then, the processing module can control the first drive circuit 206 to output a drive signal to the second first port to turn on the conductive element 202b and the conductive element 202d, and the processing module can simultaneously control the second drive circuit 208 to output a drive signal to the first second port to turn on the conductive element 204a and the conductive element 204b. At this time, since the conductive element 202b and the conductive element 204b are turned on at the same time, the light-emitting unit corresponding to the detection part 200b is driven to generate light. Similarly, after the light receiving part of the optical detection module receives the light generated by the light emitting unit, it can output the detection result for the processing module to make subsequent judgments.

[0072] In addition, in order to more quickly ensure that the light-emitting unit corresponding to the detection part is in the correct position to facilitate subsequent detection, the wafer test carrier can also have a positioning part. Figure 4 , Figure 4 FIG. 2 is a top view schematic diagram of a wafer test carrier according to another embodiment of the present application. Figure 4 As shown, the same as the previous embodiment is that the wafer test carrier 4 of this embodiment also has a first surface 40 (for example, Figure 4 The first surface 40 is a surface viewed from inside, and a plurality of detection parts 400 are arranged on the first surface 40. Different from the previous embodiment, the first surface 40 may further have a positioning part 40a, and the positioning part 40a has a special appearance shape, and the appearance shape is related to the positioning structure of the wafer DUT to be tested. In practice, when the wafer DUT to be tested is completed, a notch is often cut in advance on one side of the wafer DUT to be tested. This notch is the positioning structure of the wafer DUT to be tested. The appearance shape of the positioning part 40a of the first surface 40 may be similar to the positioning structure of the wafer DUT to be tested, so that the positioning structure of the wafer DUT to be tested can be aligned with the positioning part 40a first, so that the wafer DUT to be tested can be quickly placed in the correct position on the first surface 40. The present embodiment does not limit the number of positioning parts 40a. If the wafer DUT to be tested is pre-designed with multiple positioning structures, the wafer test carrier 4 may also be designed with positioning parts 40a corresponding to the number of positioning structures. In addition, the present embodiment does not limit the appearance of the positioning portion 40a. As long as the appearance of the positioning portion 40a can facilitate the alignment of the positioning structure of the wafer DUT under test, it falls within the scope of the positioning portion 40a of the present embodiment. In one example, the soft conductive layer (not shown) placed on the first surface 40 Figure 4 ) may also have a positioning portion. Since the soft conductive layer will be pre-aligned to the correct position on the first surface 40, the wafer DUT to be tested may also be quickly placed to the correct position according to the positioning portion of the soft conductive layer.

[0073] In addition, in order to make the exhaust module exhaust more efficiently, in one example, an exhaust hole can be provided on the first surface of the wafer test carrier. Figure 5A and Figure 5B , Figure 5A FIG. 4 is a top view schematically showing a wafer testing carrier according to yet another embodiment of the present application. Figure 5B is based on Figure 5A As shown in the figure, the wafer test carrier 5 of this embodiment also has a first surface 50 (for example, Figure 5A The first surface 50 is provided with a plurality of detection parts 500, and the plurality of detection parts 500 can be arranged in a first array or a first pattern. Different from the previous embodiment, the first surface 50 can further have a plurality of air extraction holes 506, and the air extraction holes 506 can be arranged in a second array or a second pattern, and one end of the air extraction hole 506 is exposed to the first surface 50.

[0074] In practice, the number of the air extraction holes 506 may be the same as the number of the detection units 500, that is, one air extraction hole 506 is correspondingly provided in each detection unit 500. Figure 5B For example, any detection portion 500a on the first surface 50 may have a gas extraction hole 506a in addition to the conductive member 502a and the conductive member 504a. In this way, the first array should be the same as the second array, and the first pattern should be similar to the second pattern. However, because the gas extraction hole 506 is inside the detection portion 500, the length and width (or area) of the second pattern may be slightly smaller than the first pattern.

[0075] This embodiment does not limit the position of the air extraction hole 506a inside the detection part 500a, or the appearance shape of the air extraction hole 506a. In an example, the air extraction hole 506a can be symmetrical to the conductive member 502a and the conductive member 504a, that is, the center of the air extraction hole 506a can be on the center line of the conductive member 502a and the conductive member 504a. The advantage of this is that the air extraction can be more uniform, allowing the contact pad to be evenly pressed on the conductive member 502a and the conductive member 504a through the soft conductive layer, avoiding pressure concentration on a certain conductive member. In addition, the appearance shape of the air extraction hole 506a exposed to the first surface can be circular, rectangular or other appropriate shapes, which is not limited in this embodiment. In practice, the air extraction hole 506a is open at one end to the first surface 50, and the other end is connected to the air extraction module. Here, the present embodiment does not limit which surface of the wafer test carrier 5 the opening of the other end of the exhaust hole 506a is opened on. For example, the opening of the other end of the exhaust hole 506a can be opened on the second surface of the wafer test carrier 5, and the second surface can be exactly the back of the first surface, so that the exhaust hole 506a can be a vertical through hole, and is connected to the exhaust module from the second surface of the wafer test carrier 5. For another example, the opening of the other end of the exhaust hole 506a can be opened on the side surface of the wafer test carrier 5, and the side surface is not the first surface or the second surface mentioned above, so that the exhaust hole 506a can vertically enter the wafer test carrier 5 from the first surface 50, and is a horizontal through hole inside the wafer test carrier 5, and is connected to the exhaust module from the side surface of the wafer test carrier 5.

[0076] In addition, the air extraction holes 506 can be connected to the air extraction module individually, or multiple air extraction holes 506 can be connected to each other in the wafer test carrier 5 and integrated into one opening connected to the air extraction module, which is not limited in this embodiment. In addition, this embodiment also does not limit the area of ​​each air extraction hole 506 exposed to the first surface. For example, the area occupied by the air extraction hole 506a in the detection part 500a on the first surface can be substantially the same as the area occupied by the conductive member 502a or the conductive member 504a on the first surface.

[0077] For a clearer explanation of how the DUT is attached to the wafer test carrier, please refer to Figure 6 , Figure 6 FIG. 2 is a schematic diagram showing the structure of a portion of a wafer testing device according to another embodiment of the present application. Figure 6As shown, it is assumed that the wafer DUT to be tested, the wafer test carrier 60, the soft conductive layer 61, the temperature control component 63 and the carrier 69 are all placed in the accommodation space inside the airtight box 65, and the soft conductive layer 61 and the temperature control component 63 are respectively located on both sides of the wafer test carrier 60. In detail, the wafer DUT to be tested is placed on the soft conductive layer 61, the soft conductive layer 61 is placed on the wafer test carrier 60, and the wafer test carrier 60 is placed on the carrier 69, so that the wafer DUT to be tested, the soft conductive layer 61, the wafer test carrier 60 and the carrier 69 are stacked in sequence. Here, the wafer test carrier 60 can have a plurality of connected exhaust holes 600, the soft conductive layer 61 can also have a plurality of through holes 610, and each exhaust hole 600 can correspond to one through hole 610. In other words, the arrangement of the exhaust holes 600 and the arrangement of the through holes 610 can be substantially the same (for example, both are the second pattern). As mentioned above, the exhaust hole 600 can vertically pass through the wafer test carrier 60, and the corresponding exhaust pipe 690 on the corresponding carrier 69. The exhaust pipe 690 can extend horizontally inside the carrier 69 and be exposed on the side surface of the carrier 69, and then can be connected to the exhaust module (not shown) outside the airtight box 65 by other pipes 692. The upper side of the airtight box 65 can be adjacent to the light-emitting surface of the wafer DUT to be tested, and the upper side can be made of light-transmitting material. Therefore, during the test process of the wafer DUT to be tested, the light emitted by the light-emitting unit of the wafer DUT to be tested can penetrate the airtight box 65. And therefore, the aforementioned optical detection module can be placed above the airtight box 65 to detect the light emitted by the light-emitting unit.

[0078] Back to Figure 5A , Figure 5A Although the number of the exhaust holes 506 can be the same as the number of the detection parts 500, and each detection part 500 has a corresponding exhaust hole 506, in practice, as long as the exhaust efficiency of the exhaust module is good and in order to take into account the structural strength of the wafer test carrier 5, the number of the exhaust holes can be less than the number of the detection parts. Figure 5A and Figure 7 , Figure 7 FIG. 1 is a top view schematic diagram of a wafer test carrier according to another embodiment of the present application. As shown in the figure, similar to the above embodiment, the wafer test carrier 7 of this embodiment also has a first surface 70 (e.g., Figure 7The first surface 70 is provided with a plurality of detection parts 700, and the plurality of detection parts 700 can be arranged into a first array or a first pattern, and the first surface 70 also has a plurality of air extraction holes 706, and the air extraction holes 706 can be arranged into a second array or a second pattern. Different from the previous embodiment, the number of air extraction holes 706 on the first surface 70 is relatively small, and not one air extraction hole 706 is correspondingly arranged in each detection part 700, but air extraction holes 706 are arranged in every other row of detection parts 700. In this way, the first array should be larger than the second array, and the area occupied by the first pattern should also be larger than the area occupied by the second pattern.

[0079] Of course, this embodiment does not limit the number of air extraction holes. Figure 7 and Figure 8 , Figure 8 FIG. 1 is a top view schematic diagram of a wafer test carrier according to another embodiment of the present application. As shown in the figure, similar to the above embodiment, the wafer test carrier 8 of this embodiment also has a first surface 80, and the first surface 80 has a first surface (e.g., Figure 8 The first surface 80 is provided with a plurality of detection parts 800, which can be arranged into a first array or a first pattern, and the first surface 80 also has a plurality of air extraction holes 806, which can be arranged into a second array or a second pattern. Different from the previous embodiment, the number of air extraction holes 806 on the first surface 80 is even smaller, and air extraction holes 806 are only provided for detection parts 800 that are separated by a row and a column. Of course, the first array should be larger than the second array, and the area occupied by the first pattern should also be larger than the area occupied by the second pattern.

[0080] Figure 5A , Figure 7 or Figure 8 The illustrated exhaust holes can be located within the periphery of the first surface in practice. In addition, in order to maintain a better exhaust effect, when the wafer DUT to be tested is placed on the first surface, the wafer DUT to be tested should be able to cover these exhaust holes, so that when the exhaust module is exhausting air, each exhaust hole can play the function of extracting the gas between the wafer DUT to be tested and the first surface. In addition, each exhaust hole has at least a first distance from the adjacent first conductive part or second conductive part, and each exhaust hole has at least a second distance from another adjacent exhaust hole, and the first distance is less than or equal to the second distance. Figure 5A and Figure 5B For example, the distances from the conductive member 502a and the conductive member 504a to the air extraction hole 506a are substantially equal, which is defined as the first distance. The distance between adjacent air extraction holes 506 is defined as the second distance, which is actually greater than the first distance. Figure 8The example is more obvious, the adjacent air pumping holes 806 are separated by at least a distance of the entire detection part 800, which is significantly greater than the distance from the conductive member in the same detection part 800 to the air pumping hole.

[0081] In one example, if the grains in the wafer DUT to be tested are relatively small, the corresponding size of the detection part 800 should also be relatively small. In this case, the first distance can be between 0.2-0.4 mm, and in practice, the difference between the second distance and the first distance can be relatively large. Taking the first distance of 0.25 mm as an example, in order to take into account the structural strength, the effects of exhaust and heat dissipation, the second distance can be twice the first distance, that is, 0.5 mm. In another example, if the grains in the wafer DUT to be tested are relatively large, the corresponding size of the detection part 800 is naturally relatively large. In this case, the first distance can be between 0.5-20 mm, and in practice, the difference between the second distance and the first distance can be relatively small. Taking the first distance of 0.5 mm as an example, in order to take into account the structural strength, the effects of exhaust and heat dissipation, the second distance can be exactly the first distance, that is, 0.5 mm.

[0082] In one example, the air extraction hole is at a third distance from the periphery of the first surface, and the first distance is less than or equal to the third distance. Figure 8 The example of FIG. 8 shows that the distance from the air extraction hole 806 to the edge of the first surface 80 is defined as the third distance, and the third distance should be greater than or equal to the distance from the conductive member in the same detection unit 800 to the air extraction hole. In this way, it is possible to avoid the problem of air leakage or the structural strength of the first surface 80 being insufficient due to the air extraction hole 806 being too close to the edge of the first surface 80.

[0083] In summary, the wafer testing device provided by the present application can directly detect a large number of light-emitting unit dies on the wafer to be tested without contacting the light-emitting surface of the wafer to be tested. In addition, the wafer testing device provided by the present application has a soft conductive layer, and the light-emitting unit can be electrically connected to the detection unit via the soft conductive layer, which can overcome the problem of poor contact. In addition, the temperature control component provided by the present application can make the wafer to be tested on the wafer test carrier operate at a standardized temperature.

[0084] The embodiments and / or implementation methods described above are only used to illustrate the preferred embodiments and / or implementation methods for realizing the technology of the present application, and are not intended to limit the implementation methods of the technology of the present application in any form. Any technical personnel in this field may make slight changes or modifications to other equivalent embodiments without departing from the scope of the technical means disclosed in the content of this application, but they should still be regarded as technologies or embodiments that are essentially the same as those of the present application.

Claims

1. A wafer testing device for testing a wafer to be tested, wherein the wafer to be tested has a plurality of light emitting units, characterized in that: The wafer testing device includes: A wafer testing carrier having a first surface, on which a plurality of detection parts are disposed; and a soft conductive layer, detachably disposed on the first surface, the soft conductive layer is conductive in a vertical direction and non-conductive in a horizontal direction; An optical detection module having a light receiving portion for receiving light to generate a detection result; a horizontal moving module, controlled by a moving instruction, to move the wafer test carrier so that one of the detection parts is aligned with the light receiving part of the optical detection module; as well as a processing module electrically connected to the wafer test carrier, the optical detection module and the horizontal movement module, for executing a detection program to generate the movement instruction and receive the detection result; When testing the wafer to be tested, the wafer to be tested is placed on the soft conductive layer, and each of the light-emitting units in the vertical direction is electrically connected to one of the detection parts via the soft conductive layer; The wafer test carrier further has a plurality of exhaust holes, the exhaust holes are arranged in a second array, and one end of the exhaust holes is exposed to the first surface; The soft conductive layer has a plurality of through holes, which are arranged into the second array, and each of the through holes corresponds to one of the air extraction holes.

2. The wafer testing device according to claim 1, characterized in that: Each of the detection parts has a first conductive element and a second conductive element, and the detection parts are arranged into a first array, wherein among the detection parts in the same row of the first array, the first conductive elements of adjacent detection parts are electrically connected to each other, and among the detection parts in the same column of the first array, the second conductive elements of adjacent detection parts are electrically connected to each other.

3. The wafer testing device according to claim 2, characterized in that: Each of the detection parts corresponds to one of the light-emitting units, the first conductive element of each of the detection parts is electrically connected to a first contact pad of the corresponding light-emitting unit via the soft conductive layer, and the second conductive element of each of the detection parts is electrically connected to a second contact pad of the corresponding light-emitting unit via the soft conductive layer.

4. The wafer testing device according to claim 1, wherein: The invention further comprises an air extraction module, which is connected to the air extraction holes and extracts gas from the air extraction holes according to an air extraction instruction.

5. The wafer testing device according to claim 4, characterized in that: It further comprises an airtight box and a pressurizing module. At least the wafer testing carrier and the soft conductive layer are arranged in a containing space of the airtight box. The pressurizing module is used to pressurize the containing space so that the air pressure value of the containing space is greater than 1atm.

6. The wafer testing device according to claim 1, wherein: The invention further comprises a temperature control component, which is adjacent to a second surface of the wafer test carrier. The second surface is opposite to the first surface. The temperature control component is used to increase or decrease the temperature of the wafer test carrier.

7. The wafer testing device according to claim 1, wherein: When testing the wafer to be tested, a non-light-emitting surface of the wafer to be tested contacts the soft conductive layer.

8. A wafer testing device for testing a wafer to be tested, wherein the wafer to be tested has a plurality of light emitting units, characterized in that: The wafer testing device includes: A wafer test carrier having a first surface and a plurality of exhaust holes, a plurality of detection parts are arranged on the first surface, each of the detection parts has a first conductive member and a second conductive member, one end of each exhaust hole is exposed to the first surface, the detection parts are arranged in a first pattern, and the exhaust holes are arranged in a second pattern; as well as a soft conductive layer, detachably disposed on the first surface, the soft conductive layer is conductive in a vertical direction and non-conductive in a horizontal direction; The soft conductive layer has a plurality of through holes, the through holes are arranged in the second pattern, and each of the through holes corresponds to one of the air extraction holes; Each of the air pumping holes has at least a first distance from the adjacent first conductive member or the second conductive member, and each of the air pumping holes has at least a second distance from another adjacent air pumping hole, and the first distance is less than or equal to the second distance.

9. The wafer testing device according to claim 8, characterized in that: The air extraction holes are located within the periphery of the first surface, and there is a third distance between the air extraction holes and the periphery of the first surface, and the first distance is less than or equal to the third distance.

10. The wafer testing device according to claim 8, characterized in that: When testing the wafer to be tested, the wafer to be tested is placed on the soft conductive layer, a non-light-emitting surface of the wafer to be tested contacts the soft conductive layer, and the air extraction holes correspond to the periphery of the non-light-emitting surface.

11. The wafer testing device according to claim 8, characterized in that: The first pattern is a first array. In the detection parts in the same row of the first array, the first conductive elements of adjacent detection parts are electrically connected. In the detection parts in the same column of the first array, the second conductive elements of adjacent detection parts are electrically connected.

12. The wafer testing device according to claim 8, characterized in that: The invention further comprises a temperature control component, which is adjacent to a second surface of the wafer test carrier. The second surface is opposite to the first surface. The temperature control component is used to increase or decrease the temperature of the wafer test carrier.

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