Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same, comprising a substrate and a first III-V compound layer, wherein the first III-V compound layer is disposed on the substrate. The first III-V compound layer comprises a plurality of lattices and each lattice has a prism face. The semiconductor device further comprises a second III-V compound layer, wherein the second III-V compound layer is disposed on the first III-V compound layer. The semiconductor device comprises a source electrode, a drain electrode and a gate electrode, which are disposed on the second III-V compound layer. The source electrode and the drain electrode define a channel region in the first III-V compound layer, wherein the channel region has a plurality of carrier channels. The normal direction of the prism face defines an m-axis, and each carrier channel is parallel to the m-axis. The semiconductor device of the present invention can effectively reduce the on-resistance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device for high electron mobility transistors (HEMT) devices and a method for manufacturing the same. Background Art

[0002] In the semiconductor industry, gallium nitride (GaN) is often used to form various integrated circuit devices due to its characteristics, such as high electron mobility transistor (HEMT) devices. High electron mobility transistors, also known as heterostructure FETs (HFETs) or modulation-doped FETs (MODFETs), are composed of semiconductor materials with different energy gaps. A two-dimensional electron gas (2DEG) layer is generated at the interface formed by adjacent different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, high electron mobility transistors can have advantages such as high breakdown voltage, high electron mobility and low input capacitance, making them suitable for use in high-power devices.

[0003] However, although the existing high electron mobility transistors generally meet the requirements, they are not satisfactory in every aspect and still need to be further improved to enhance performance and have wider applications. Summary of the invention

[0004] An embodiment of the present invention includes a semiconductor device. The semiconductor device includes a substrate and a first III-V compound layer, and the first III-V compound layer is disposed on the substrate. The first III-V compound layer includes a plurality of lattices and each lattice has a prism face. The semiconductor device further includes a second III-V compound layer, and the second III-V compound layer is disposed on the first III-V compound layer. The semiconductor device includes a source electrode, a drain electrode, and a gate electrode, which are disposed on the second III-V compound layer. The source electrode and the drain electrode define a channel region in the first III-V compound layer, and the channel region has a plurality of carrier channels. The normal direction of the prism face defines an m-axis, and each carrier channel is parallel to the m-axis.

[0005] An embodiment of the present invention includes a semiconductor device. The semiconductor device includes a substrate and a first III-V compound layer, and the first III-V compound layer is disposed on the substrate. The first III-V compound layer includes a plurality of lattices and each lattice has an m-plane. The semiconductor device further includes a second III-V compound layer, and the second III-V compound layer is disposed on the first III-V compound layer. The semiconductor device includes a source electrode, a drain electrode, and a gate electrode, which are disposed on the second III-V compound layer. The source electrode and the drain electrode define a channel region in the first III-V compound layer, and the channel region has a plurality of carrier channels. Each carrier channel is parallel to the normal direction of the m-plane.

[0006] An embodiment of the present invention includes a method for manufacturing a semiconductor device. The manufacturing method includes forming and providing a substrate. The manufacturing method also includes forming a first III-V compound layer on the substrate. The first III-V compound layer includes a plurality of lattices and each lattice has a prism face. The manufacturing method includes forming a second III-V compound layer on the first III-V compound layer. The manufacturing method further includes forming a source electrode, a drain electrode and a gate electrode on the second III-V compound layer. The source electrode and the drain electrode define a channel region in the first III-V compound layer, and the channel region has a plurality of carrier channels. The normal direction of the prism face defines an m-axis, and each carrier channel is parallel to the m-axis.

[0007] The semiconductor device of the present invention can effectively reduce the on-resistance of the semiconductor device by aligning each carrier channel in the channel region of the semiconductor device in parallel with the m-axis. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following will be described in detail with reference to the accompanying drawings. It should be noted that the various characteristic components are not drawn to scale and are only used for illustration. In fact, the size of the device may be enlarged or reduced to clearly show the technical features of the embodiment of the present invention.

[0009] Figures 1 to 4 According to some embodiments of the present invention, the formation Figure 4 The diagram shows a partial cross-sectional view of a semiconductor device at different process stages.

[0010] Figure 5A A partial top view of a substrate and a first III-V compound layer is shown.

[0011] Figure 5B Schematic diagram showing an enlarged top view of a single lattice.

[0012] Figure 6 A schematic diagram showing a single crystal lattice.

[0013] Figure 7 A partial top view of a semiconductor device according to an embodiment of the present invention is shown.

[0014] Reference numerals:

[0015] 1. Semiconductor devices

[0016] 10~Substrate

[0017] 20~First III-V compound layer

[0018] 21~Lattice

[0019] 21a~a plane

[0020] 21m~m plane

[0021] 30~Second III-V compound layer

[0022] 30T~Top surface

[0023] 41~Source electrode

[0024] 41S~Side

[0025] 43~Drain electrode

[0026] 43S~Side

[0027] 45~Gate electrode

[0028] 47~Channel area

[0029] A-A'~Hatch Line

[0030] a~a axis

[0031] m~m axis DETAILED DESCRIPTION

[0032] The following invention content provides many different embodiments or examples to implement the different features of the present invention. The following invention content describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes a first characteristic component formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and may also include an embodiment in which an additional characteristic component is formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact.

[0033] It should be understood that additional operating steps may be implemented before, during or after the method, and in other embodiments of the method, some operating steps may be replaced or omitted.

[0034] In addition, spatially related terms may be used, such as "below", "below", "lower", "above", "above", "higher" and similar terms. These spatially related terms are used to facilitate the description of the relationship between one (or some) device or feature component and another (or some) device or feature component in the diagram. These spatially related terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially related adjectives used therein will also be interpreted according to the orientation after the rotation.

[0035] In the specification, the terms "about", "approximately", "generally" usually mean within 20%, within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The numbers given here are approximate numbers, that is, in the absence of specific description of "about", "approximately", "generally", the meaning of "about", "approximately", "generally" can still be implied.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which this invention belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0037] The different embodiments of the invention described below may repeatedly use the same reference symbols and / or marks. These repetitions are for the purpose of simplicity and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0038] On-resistance (R on ) is an important factor affecting the power consumption of semiconductor devices, and its resistance value is proportional to the power consumption of the semiconductor device. Embodiments of the present invention provide semiconductor devices and methods for manufacturing the same, which are particularly suitable for high electron mobility transistor (HEMT) devices. In the semiconductor device of the embodiment of the present invention, by arranging the charge carrier channel (or source electrode and drain electrode) of the semiconductor device in a specific direction relative to the lattice of the III-V compound layer (e.g., gallium nitride (GaN)), the on-resistance of the semiconductor device can be effectively reduced. The following will be described with reference to the embodiments shown in the drawings.

[0039] Figures 1 to 4 According to some embodiments of the present invention, the formation Figure 4The semiconductor device 1 is shown as a partial cross-sectional schematic diagram at various process stages. It should be noted that in order to more clearly show the features of the embodiment of the present invention, Figures 1 to 4 Some components may be omitted.

[0040] Reference Figure 1 , providing a substrate 10. In some embodiments, the substrate 10 may be a semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or a similar semiconductor substrate. In some embodiments, the substrate 10 may be a substrate in which a semiconductor is located on an insulator, such as a silicon on insulator (SOI) substrate. In some embodiments, the substrate 10 may be a glass substrate or a ceramic substrate, such as a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a sapphire substrate. However, the embodiments of the present invention are not limited thereto.

[0041] In some embodiments, the substrate 10 is a QST substrate. Here, the QST substrate refers to a substrate produced by Qromis Technology, Inc. of the United States. For example, the QST substrate may include a core, a barrier layer, a bonding layer, and a single crystalline layer. In some embodiments, the barrier layer may encapsulate the core, the bonding layer may be disposed on the barrier layer, and the single crystalline layer may be disposed on the bonding layer, but the embodiments of the present invention are not limited thereto.

[0042] In some embodiments, the core material may include polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN), polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium (III) trioxide (Ga2O3), other suitable materials or combinations thereof, but the present invention is not limited thereto. In some embodiments, the polycrystalline ceramic material may include a bonding material such as yttrium oxide (yttria).

[0043] In some embodiments, the material of the barrier layer may be an amorphous material, such as silicon nitride, silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum nitride (AlN), silicon carbide (SiC), other suitable materials or combinations thereof, but the embodiments of the present invention are not limited thereto. In some embodiments, the barrier layer may be formed by a low-pressure chemical vapor deposition (LPCVD) process, but the embodiments of the present invention are not limited thereto. In some embodiments, the barrier layer may be a one or more multi-layer structure, which includes one or more materials stacked in a composite manner, but the embodiments of the present invention are not limited thereto.

[0044] In some embodiments, the barrier layer can be used to prevent the components in the core (e.g., yttrium oxide, oxygen, metal impurities, other trace elements, etc.) from diffusing and / or releasing into the environment of the semiconductor processing chamber. In the semiconductor processing chamber, the QST substrate can be epitaxially grown, for example, at high temperatures (e.g., 1,000° C.).

[0045] In some embodiments, the material of the bonding layer may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials or combinations thereof. In some embodiments, the bonding layer may be formed on (part of) the top surface of the barrier layer by chemical vapor deposition (CVD), atomic layer deposition (ALD) or spin coating. For example, the chemical vapor deposition method may be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0046] In some embodiments, the material of the single crystal layer may include silicon (Si), aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), silicon carbide (SiC), other suitable materials or a combination of the foregoing, but the embodiments of the present invention are not limited thereto. The single crystal layer may be a single layer or a multi-layer structure. In some embodiments, the single crystal layer may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods or a combination of the foregoing, but the embodiments of the present invention are not limited thereto.

[0047] In some embodiments, the substrate 10 may further include a plurality of adhesion layers and a conductive layer. The adhesion layer and the conductive layer may be disposed between the core and the barrier layer. For example, the adhesion layer may be disposed between the core and the conductive layer, and the adhesion layer may be disposed between the conductive layer and the barrier layer, but the embodiments of the present invention are not limited thereto.

[0048] In some embodiments, the material of the adhesive layer may include tetraethylorthosiliate (TEOS), silicon oxide (Si x O y ), other suitable materials or the combination thereof, but the embodiments of the present invention are not limited thereto. In some embodiments, the adhesive layer can be formed around the core by chemical vapor deposition (CVD), atomic layer deposition (ALD) or spin coating.

[0049] In some embodiments, the conductive layer may include a highly conductive material that is doped (e.g., doped with boron). In some embodiments, the doping concentration may be between 1×10 19 cm -3 Up to 1x10 20 cm -3 , to provide high conductivity. Other dopants with different doping concentrations (e.g., doping concentrations of 1x10 16 cm -3 Up to 5x10 18 cm -3 Phosphorus, arsenic, bismuth, etc.) can also be used to provide N-type or P-type semiconductor materials suitable for use in the conductive layer, but the present invention is not limited to this.

[0050] The detailed structure of the QST substrate can be referred to in U.S. Patent Application No. 15 / 621,335 filed on June 13, 2017 and U.S. Patent Application No. 15 / 621,335 filed on June 13, 2017, and will not be described in detail here. However, the embodiments of the present invention are not limited thereto.

[0051] Reference Figure 2 , a first III-V compound layer 20 is formed on the substrate 10. In some embodiments, the material of the first III-V compound layer 20 may include one or more III-V compound semiconductor materials, such as III-nitride. In some embodiments, the material of the first III-V compound layer 20 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium gallium aluminium nitride (InGaAlN), similar materials or a combination thereof. In some embodiments, the thickness of the first III-V compound layer 20 may be between 0.01 μm and 10 μm. In some embodiments, the first III-V compound layer 20 may have a dopant, such as an n-type dopant or a p-type dopant. The first III-V compound layer 20 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods or a combination thereof. For example, the first III-V compound layer 20 may be formed by metal organic chemical vapor deposition (MOCVD) using a gallium-containing precursor and a nitrogen-containing precursor. The gallium-containing precursor may include trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemicals; the nitrogen-containing precursor may include ammonia (NH3), tertiarybutylamine (TBAm), phenylhydrazine, or other suitable chemicals. However, the embodiments of the present invention are not limited thereto.

[0052] Reference Figure 3, forming a second III-V compound layer 30 on the first III-V compound layer 20. In some embodiments, the material of the second III-V compound layer 30 may include one or more III-V compound semiconductors, such as III-nitrides. In some embodiments, the material of the second III-V compound layer 30 may include aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (InGaAlN), similar materials, or a combination of the foregoing. In some embodiments, the thickness of the second III-V compound layer 30 may be between 1 nm and 500 nm. In some embodiments, the second III-V compound layer 30 may have a dopant, such as an n-type dopant or a p-type dopant. The second III-V compound layer 30 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or a combination of the foregoing. For example, the second III-V compound layer 30 can be formed by metal organic vapor phase epitaxy (MOCVD) using an aluminum-containing precursor, a gallium-containing precursor, and a nitrogen-containing precursor. The aluminum-containing precursor includes trimethylaluminum (TMA), triethylaluminum (TEA), or other suitable chemicals; the gallium-containing precursor includes trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemicals; the nitrogen-containing precursor includes ammonia (NH3), tert-butylamine (TBAm), phenyl hydrazine, or other suitable chemicals. However, the embodiments of the present invention are not limited thereto.

[0053] Reference Figure 4 A source electrode 41, a drain electrode 43 and a gate electrode 45 are formed on the second III-V compound layer 30 to form the semiconductor device 1. In the embodiment of the present invention, the source electrode 41, the drain electrode 43 and the gate electrode 45 can be arranged in a specific manner, which will be described in detail with reference to the drawings later.

[0054] In some embodiments, the material of the source electrode 41 may include a conductive material, such as a metal, a metal silicide, a semiconductor material, other suitable materials, or a combination of the foregoing materials. The metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), a combination of the foregoing, an alloy of the foregoing, or a multilayer of the foregoing. The semiconductor material may be polysilicon or polycrystalline germanium. However, the embodiments of the present invention are not limited thereto. In some embodiments, the material of the drain electrode 43 may be the same or similar to the material of the source electrode 41, and no further details will be given herein.

[0055] The step of forming the source electrode 41 and the drain electrode 43 may include depositing a conductive material on the second III-V compound layer 30, and performing a patterning process on the conductive material to form the source electrode 41 and the drain electrode 43 on the top surface 30T of the second III-V compound layer 30. The deposition process for forming the conductive material may include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) (for example, sputtering), other suitable processes or a combination of the foregoing. It should be particularly noted that. Although Figure 4 The source electrode 41 and the drain electrode 43 are shown to be formed on the top surface 30T of the second III-V compound layer 30, but the embodiment of the present invention is not limited thereto. In some embodiments, part of the source electrode 41 and part of the drain electrode 43 may also be formed in the second III-V compound layer 30, or may be connected to the first III-V compound layer 20, which may be adjusted according to actual needs.

[0056] In some embodiments, the material of the gate electrode 45 may include a conductive material, such as a metal, a metal silicide, a semiconductor material, other suitable materials, or a combination of the foregoing materials. The metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), a combination of the foregoing, an alloy of the foregoing, or a multilayer of the foregoing. The semiconductor material may be polysilicon or polycrystalline germanium. However, the embodiments of the present invention are not limited thereto.

[0057] The step of forming the gate electrode 45 may include depositing a conductive material on the second III-V compound layer 30, and performing a patterning process on the conductive material to form the gate electrode 45 on the top surface 30T of the second III-V compound layer 30. The deposition process for forming the conductive material may include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) (e.g., sputtering), other suitable processes, or a combination thereof.

[0058] In some embodiments, the semiconductor device 1 may further include a doped compound semiconductor layer (not shown), and the doped compound semiconductor layer may be formed between the second III-V compound layer 30 and the gate electrode 45. In some embodiments, the doped compound semiconductor layer may include a p-type doped III-V compound, such as p-type doped gallium nitride. The p-type doped gallium nitride may be doped with at least one of magnesium (Mg), calcium (Ca), zinc (Zn), beryllium (Be), and carbon (C), and may be doped with other dopants (e.g., selected from the group consisting of strontium (Sr), barium (Ba), and radium (Ra)), but the embodiment of the present invention is not limited thereto. In some embodiments, the doped compound semiconductor layer may be formed by metal organic chemical vapor deposition (MOCVD) or other suitable deposition processes, photolithography patterning processes, and etching processes. In some embodiments, the thickness of the doped compound semiconductor layer may be between about 1 nm and about 100 nm, but the embodiment of the present invention is not limited thereto.

[0059] Reference Figure 4 The band gap discontinuity and the piezoelectric effect between the first III-V compound layer 20 and the second III-V compound layer 30 generate a carrier channel with highly mobile conduction electrons near the interface between the first III-V compound layer 20 and the second III-V compound layer 30, which is called a two-dimensional electron gas (2-DEG). Figure 4 As shown by the dotted line. Figure 4 The semiconductor device 1 shown may be a high electron mobility transistor (HEMT) using two-dimensional electron gas (2DEG) as a conductive carrier.

[0060] Figure 5A A partial top view of the display substrate 10 and the first III-V compound layer 20. Figure 5A In the embodiment, the first III-V compound layer 20 is arranged in a plurality of lattices 21, but Figure 5A The size of each lattice 21 shown in FIG. 1 is for illustration only. The actual size of the lattice 21 relative to the substrate 10 is not necessarily Figure 5A As shown. Figure 5A In the illustrated embodiment, the material of the first III-V compound layer 20 is gallium nitride (GaN), and the crystal lattice 21 of GaN belongs to the hexagonal crystal system. Figure 5B An enlarged schematic top view of a single crystal lattice 21 is shown. Figure 6 A schematic perspective view of a single crystal lattice 21 is shown. Figure 7 A partial top view of a semiconductor device 1 according to an embodiment of the present invention is shown.

[0061] It should be noted that in order to more clearly show the features of the embodiments of the present invention, FIG. 5A to FIG. 7 Some components may be omitted. For example, Figure 7 Only the source electrode 41, the drain electrode 43, the gate electrode 45 and the channel region 47 defined by the source electrode 41 and the drain electrode 43 of the semiconductor device 1 are shown. Figure 4 For example, Figure 7 The cross-sectional view is taken along the line AA' in FIG. 1 , but the embodiment of the present invention is not limited thereto.

[0062] Also refer to Figure 5A , Figure 5B and Figure 6 , the lattice 21 has a prism plane. In the present invention, the prism plane refers to the rectangular plane on the side of the hexagonal column of the lattice 21 of the hexagonal crystal system, that is, the m-plane (m-plane) 21m of the lattice 21, which can be understood by technicians in the technical field to which the present invention belongs. The prism plane (m-plane 21m) belongs to the plane family {1-100}. For example, the prism plane can be expressed as plane (10-10), but the embodiments of the present invention are not limited to this. In other embodiments, the prism plane can also be expressed as plane (-1010), plane (1-100), plane (-1100), plane (01-10) or plane (0-110).

[0063] like Figure 5A , Figure 5B As shown, the normal direction of the prism surface can define an m-axis (i.e. Figure 5A , Figure 5B For example, when the prism surface is a plane (10-10), the m-axis is [10-10]; when the prism surface is a plane (-1010), the m-axis is [-1010]; when the prism surface is a plane (1-100), the m-axis is [1-100]; when the prism surface is a plane (-1100), the m-axis is [-1100]; when the prism surface is a plane (01-10), the m-axis is [01-10]; when the prism surface is a plane (0-110), the m-axis is [0-110].

[0064] Also refer to Figure 5A and Figure 7The source electrode 41 and the drain electrode 43 may define a channel region 47 in the first III-V compound layer 20, and the channel region 47 may have a plurality of carrier channels. In the embodiment of the present invention, each carrier channel is parallel to the m-axis. In other words, in the embodiment of the present invention, each carrier channel is parallel to the normal direction of the m-plane of the lattice.

[0065] In some embodiments, the extension direction of the source electrode 41 and the drain electrode 43 may be perpendicular to the m-axis (perpendicular to the normal direction of the m-plane), that is, the source electrode 41 and the drain electrode 43 extend along Figure 5A and Figure 7 In some embodiments, the source electrode 41 and the drain electrode 43 are separated from each other along the m-axis (the normal direction of the m-plane). Figure 7 As shown, in some embodiments, the source electrode 41 and the drain electrode 43 are arranged opposite to each other and in parallel, and the projection of a side wall of the source electrode 41 facing the drain electrode 43 on the substrate 10 is a side edge 41S, and the side edge 41S is perpendicular to the m-axis (perpendicular to the normal direction of the m-plane); or, the projection of a side wall of the drain electrode 43 facing the source electrode 41 on the substrate 10 is a side edge 43S, and the side edge 43S is perpendicular to the m-axis (perpendicular to the normal direction of the m-plane).

[0066] In the embodiment of the present invention, the carriers (electrons or holes) moving in the channel region 47 defined by the source electrode 41 and the drain electrode 43 may have a higher carrier mobility than that of conventional semiconductor devices, which may have a greater impact on the on-resistance (R on ) have a beneficial impact.

[0067] However, it should be noted that the arrangement of the source electrode 41, the drain electrode 43 and the gate electrode 45 of the present invention is not limited to Figure 7 As long as each carrier channel in the channel region 47 is parallel to the m-axis, the carriers moving in the channel region 47 defined by the source electrode 41 and the drain electrode 43 can have a higher carrier mobility.

[0068] Table 1 shows the performance comparison results of the semiconductor device 1 of the embodiment of the present invention and the semiconductor device of a comparative example. The structure of the semiconductor device 1 of the embodiment of the present invention can be referred to Figures 4 to 7, and each carrier channel in the channel region 47 of the semiconductor device 1 of the embodiment of the present invention is parallel to the m-axis (e.g., [10-10]). The semiconductor device of the comparative example has a structure similar to that of the semiconductor device 1 of the embodiment of the present invention, except that each carrier channel in the channel region of the semiconductor device of the comparative example is parallel to the a-axis (i.e., the normal direction of the a-plane 21a of the lattice 21, e.g., [11-20]) (refer to Figure 5A , Figure 5B ).

[0069] Table 1

[0070] performance Example Comparative Example <![CDATA[R on (mΩ)]]> 20.5 115 <![CDATA[Area (mm 2 )]]> 10.38 5.18 <![CDATA[R on,sp (mΩ)]]> 2.13 5.96

[0071] In Table 1, R on is the on-resistance, R on,sp is the characteristic on-resistance. on,sp It is defined as the on-resistance distributed per square unit. As shown in Table 1, the characteristic on-resistance R of the semiconductor device 1 of the embodiment on,sp Compared with the characteristic on-resistance R of the semiconductor device 1 of the comparative example on,sp That is, by arranging each carrier channel in the channel region 47 of the semiconductor device 1 in a specific direction relative to the lattice 21 of the first III-V compound layer 20 (GaN), the on-resistance of the semiconductor device 1 can be effectively reduced.

[0072] In summary, in the semiconductor device of the embodiment of the present invention, by aligning each carrier channel in the channel region of the semiconductor device parallel to the m-axis (i.e., the normal direction of the prism plane of the lattice forming the first III-V compound layer), the on-resistance of the semiconductor device can be effectively reduced.

[0073] The foregoing text summarizes the characteristic components of many embodiments, so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the invention of the embodiments of the present invention. Without departing from the spirit and scope of the invention of the embodiments of the present invention, various changes, substitutions or modifications may be made to the embodiments of the present invention, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. In addition, although the present invention has been invented as above with several preferred embodiments, it is not intended to limit the present invention, and not all advantages have been described in detail herein.

[0074] Each claim of the present invention may be an independent embodiment, and the scope of the present invention includes the combination of each claim and each embodiment of the present invention.

Claims

1. A semiconductor device, It is characterized in that include: a substrate; a first III-V compound layer disposed on the substrate, wherein the first III-V compound layer includes a plurality of crystal lattices and each crystal lattice has a prism face; a second III-V compound layer disposed on the first III-V compound layer; and A source electrode, a drain electrode and a gate electrode are disposed on the second III-V compound layer, wherein the source electrode and the drain electrode define a channel region in the first III-V compound layer, wherein the channel region has a plurality of carrier channels; The normal direction of the prism surface defines an m-axis, and each carrier channel extends along a single direction parallel to the m-axis.

2. The semiconductor device according to claim 1, It is characterized in that The substrate is a semiconductor substrate, a semiconductor-on-insulator substrate, a glass substrate or a ceramic substrate.

3. The semiconductor device according to claim 1, It is characterized in that The substrate is a QST substrate.

4. The semiconductor device according to claim 1, It is characterized in that The m-axis is one of [10-10], [-1010], [1-100], [-1100], [01-10], and [0-110].

5. The semiconductor device according to claim 1, It is characterized in that The source electrode and the drain electrode are opposite to each other, and a projection of a side wall of the source electrode facing the drain electrode on the substrate is perpendicular to the m-axis.

6. The semiconductor device according to claim 1, It is characterized in that The source electrode and the drain electrode are separated from each other along the direction of the m-axis.

7. A semiconductor device, It is characterized in that include: a substrate; a first III-V compound layer disposed on the substrate, wherein the first III-V compound layer includes a plurality of crystal lattices and each crystal lattice has an m-plane; a second III-V compound layer disposed on the first III-V compound layer; and A source electrode, a drain electrode and a gate electrode are disposed on the second III-V compound layer, wherein the source electrode and the drain electrode define a channel region in the first III-V compound layer, wherein the channel region has a plurality of carrier channels; Each carrier channel extends along a single direction parallel to the normal direction of the m-plane.

8. The semiconductor device according to claim 7, It is characterized in that The substrate is a semiconductor substrate, a semiconductor-on-insulator substrate, a glass substrate or a ceramic substrate.

9. The semiconductor device according to claim 7, It is characterized in that The substrate is a QST substrate.

10. The semiconductor device according to claim 7, It is characterized in that The m-plane is one of the plane (10-10), the plane (-1010), the plane (1-100), the plane (-1100), the plane (01-10) and the plane (0-110).

11. The semiconductor device according to claim 7, It is characterized in that The source electrode and the drain electrode are opposite to each other, and a projection of a side wall of the source electrode facing the drain electrode on the substrate is perpendicular to a normal direction of the m-plane.

12. The semiconductor device according to claim 7, It is characterized in that The source electrode and the drain electrode are separated from each other along a normal direction of the m-plane.

13. A method for manufacturing a semiconductor device, It is characterized in that include: forming and providing a substrate; forming a first III-V compound layer on the substrate, wherein the first III-V compound layer comprises a plurality of crystal lattices and each crystal lattice has a prism face; forming a second III-V compound layer on the first III-V compound layer; and forming a source electrode, a drain electrode and a gate electrode on the second III-V compound layer, wherein the source electrode and the drain electrode define a channel region in the first III-V compound layer, and the channel region has a plurality of carrier channels; The normal direction of the prism surface defines an m-axis, and each carrier channel extends along a single direction parallel to the m-axis.

14. The manufacturing method according to claim 13, It is characterized in that The substrate is a semiconductor substrate, a semiconductor-on-insulator substrate, a glass substrate or a ceramic substrate.

15. The manufacturing method according to claim 13, It is characterized in that The substrate is a QST substrate.

16. The manufacturing method according to claim 13, It is characterized in that The m-axis is one of [10-10], [-1010], [1-100], [-1100], [01-10], and [0-110].

17. The manufacturing method according to claim 13, It is characterized in that The source electrode and the drain electrode are opposite to each other, and a projection of a side wall of the source electrode facing the drain electrode on the substrate is perpendicular to the m-axis.

18. The manufacturing method according to claim 13, It is characterized in that The source electrode and the drain electrode are separated from each other along the direction of the m-axis.

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