Display panel and display device

Abstract

The embodiment of the present invention discloses a display panel. It includes: a substrate; a first signal line, the first signal line is located on the substrate, the first signal line includes a first sub-signal line and a second sub-signal line that are electrically connected to each other and located in different layers, the first sub-signal line is located on the side of the second sub-signal line facing the substrate; a planarization layer, the planarization layer is located on the side of the first signal line away from the substrate; a light-emitting element and a pixel spacing layer, the light-emitting element and the pixel spacing layer are located on the side of the planarization layer away from the substrate; wherein the planarization layer includes a first opening, in a direction perpendicular to the substrate, the first sub-signal line at least partially overlaps with the first opening. The technical solution provided by the embodiment of the present invention can alleviate the problem that the first signal line is easily corroded by water and oxygen, thereby improving the yield of the display panel.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, liquid crystal display panels and organic light-emitting display panels have gradually become the two mainstream display panels, and are widely used in electronic devices such as mobile phones, computers and notebooks.

[0003] The existing display panel generally includes a planarization layer, which is used to planarize the film layer located thereunder, and based on the consideration of the planarization effect, the planarization layer is generally made of organic materials. However, organic materials will form a water and oxygen transmission path, and water and oxygen will pass through the planarization layer into the display area, affecting the normal display of the display panel. Summary of the invention

[0004] The present invention provides a display panel and a display device to improve the problem that a first signal line is easily corroded by water and oxygen, thereby improving the yield of the display panel.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0006] substrate substrate;

[0007] A first signal line, the first signal line is located on the substrate, the first signal line comprises a first sub-signal line and a second sub-signal line which are electrically connected to each other and located in different layers, the first sub-signal line is located on a side of the second sub-signal line facing the substrate;

[0008] a planarization layer, the planarization layer being located on a side of the first signal line away from the substrate;

[0009] A light emitting element and a pixel spacing layer, wherein the light emitting element and the pixel spacing layer are located on a side of the planarization layer away from the base substrate;

[0010] in,

[0011] The planarization layer includes a first opening, and in a direction perpendicular to the base substrate, the first sub-signal line at least partially overlaps with the first opening.

[0012] In a second aspect, an embodiment of the present invention further provides a display device, which includes the display panel described in the second aspect.

[0013] The display panel provided by an embodiment of the present invention, by setting a first signal line including a first sub-signal line and a second sub-signal line electrically connected to each other, the first sub-signal line is located on the side of the second sub-signal line facing the base substrate, and the first sub-signal line and the first opening on the planarization layer have an orthographic projection on the base substrate at least partially overlapped, so that the first sub-signal line originally on the same layer as the second sub-signal line can be moved down by at least one layer, so that the insulating layer between the first sub-signal line and the second sub-signal line can at least cover a portion of the first sub-signal line, thereby reducing the risk of the first sub-signal line being exposed by the first opening, improving the problem of corrosion caused by the exposure of the first sub-signal line, and thereby improving the yield of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural schematic diagram of a display panel provided by the related technology;

[0015] Figure 2 yes Figure 1 The cross-section along the AA' direction;

[0016] Figure 3 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 4 yes Figure 3 A cross-sectional view along the BB' direction;

[0018] Figure 5 yes Figure 3 Another cross-sectional view along the BB' direction;

[0019] Figure 6 yes Figure 3 Another cross-sectional view along the BB' direction;

[0020] Figure 7 yes Figure 3 Another cross-sectional view along the BB' direction;

[0021] Figure 8 yes Figure 3 A cross-sectional view along the BB' direction;

[0022] Fig. 9 yes Figure 3 Another cross-sectional view along the BB' direction;

[0023] Fig.10 yes Figure 3 Another cross-sectional view along the BB' direction;

[0024] Fig.11 yes Figure 3 Another cross-sectional view along the BB' direction;

[0025] Fig.12 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0026] Fig.13 yes Fig.12 A cross-section along CC';

[0027] Fig.14 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0028] Fig.15 yes Fig.14 A cross-section along DD';

[0029] Fig.16 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0030] Fig.17 yes Fig.16 A kind of profile along EE';

[0031] Fig.18 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0032] Fig.19 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0033] Fig. 20 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0034] Fig.21 yes Fig. 20 A cross-section along the FF' direction;

[0035] Fig. 22 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0036] Fig.23 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0037] Fig.24 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0038] Fig.25 yes Fig.24 A cross-section along the GG' direction;

[0039] Fig.26 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0040] Fig. 27 yes Figure 3 A cross-sectional view along the BB' direction;

[0041] Fig.28 yes Figure 3 Another cross-sectional view along the BB' direction

[0042] Fig.29 yes Figure 3 Another cross-sectional view along the BB' direction;

[0043] Fig.30 yes Figure 3 Another cross-sectional view along the BB' direction;

[0044] Fig.31 yes Figure 3 A cross-sectional view along the BB' direction;

[0045] Fig.32 yes Figure 3 Another cross-sectional view along the BB' direction;

[0046] Fig.33 yes Figure 3 Another cross-sectional view along the BB' direction;

[0047] Fig.34 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0049] In connection with the problems pointed out in the background technology, although removing the planarization layer between the display area and the non-display area can cut off the water and oxygen transmission path, it will expose the film layer under the planarization layer, affecting the normal operation of the film layer under the planarization layer, and further affecting the normal operation of the display panel. Figure 1 It is a structural schematic diagram of a display panel provided by the related technology. Figure 2 yes Figure 1 The cross-section along the AA' direction. Figure 1 The display panel includes a display area AZ' and a non-display area DZ' surrounding the display area, and the non-display area DZ' includes an organic film clearance area OZ'. Figure 2The display panel includes a substrate 10', a source-drain metal layer 20' (a metal layer where the source and drain of the transistor are located) and a planarization layer 30'. The planarization layer 30' is arranged on the side of the source-drain metal layer 20' away from the substrate 10', and the first signal line 21' is arranged in the source-drain metal layer 20'. In order to block water and oxygen, the planarization layer 30' in the organic film clearance area DZ' is usually removed, thereby blocking the path for water and oxygen to spread from the non-display area DZ' to the display area AZ'. However, the first signal line 21' located in the organic film clearance area OZ' is exposed and easily corroded by water and oxygen, which leads to a decrease in the yield of the display panel.

[0050] Based on the above technical problems, an embodiment of the present invention provides a display panel, comprising: a base substrate; a first signal line, the first signal line is located on the base substrate, the first signal line comprises a first sub-signal line and a second sub-signal line which are electrically connected to each other and located at different layers, the first sub-signal line is located on the side of the second sub-signal line facing the base substrate; a planarization layer, the planarization layer is located on the side of the first signal line away from the base substrate; a light-emitting element and a pixel spacing layer, the light-emitting element and the pixel spacing layer are located on the side of the planarization layer away from the base substrate; wherein the planarization layer comprises a first opening, and in a direction perpendicular to the base substrate, the first sub-signal line at least partially overlaps with the first opening. By adopting the above-mentioned technical scheme, by setting the first signal line to include a first sub-signal line and a second sub-signal line electrically connected to each other, the first sub-signal line is located on the side of the second sub-signal line facing the substrate, and the first sub-signal line and the first opening on the planarization layer have at least a partial overlap in their orthographic projection on the substrate. The first sub-signal line originally on the same layer as the second sub-signal line can be moved down by at least one layer. In this way, the insulating layer between the first sub-signal line and the second sub-signal line can at least partially cover the first sub-signal line, reducing the risk of the first sub-signal line being exposed by the first opening, improving the problem of corrosion caused by the exposure of the first sub-signal line, reducing the risk of the first sub-signal line being exposed by the first opening, and thereby improving the yield of the display panel.

[0051] The above is the core idea of ​​the present application. The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] Figure 3 It is a structural schematic diagram of a display panel provided by an embodiment of the present invention. Figure 4 yes Figure 3 A cross-sectional view along the BB' direction. Figure 5 yes Figure 3 Another cross-sectional view along the BB' direction. Figure 1-Figure 3 The display panel includes: a base substrate 11; a first signal line 20, the first signal line 20 is located on the base substrate 11, the first signal line 20 includes a first sub-signal line 21 and a second sub-signal line 22 that are electrically connected to each other and located in different layers, the first sub-signal line 21 is located on the side of the second sub-signal line 22 facing the base substrate 11; a planarization layer 12, the planarization layer 12 is located on the side of the first signal line 20 away from the base substrate 11; a light-emitting element 30 and a pixel spacing layer 13, the light-emitting element 30 and the pixel spacing layer 13 are located on the side of the planarization layer 12 away from the base substrate 11; wherein the planarization layer 12 includes a first opening 121, in a direction perpendicular to the base substrate 11, the first sub-signal line 21 at least partially overlaps with the first opening 121.

[0053] Specifically, the display panel includes an organic light emitting display panel or other display panels known to those skilled in the art, which are not limited here.

[0054] Specifically, the base substrate 11 is used to support and protect the film layer located thereon. The base substrate 11 may be a rigid substrate, for example, the material of the base substrate 11 is glass, or the base substrate 11 may be a flexible substrate, for example, the material of the base substrate 11 may include one or more combinations of polymer resins of polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate. Here, the material of the base substrate 11 is not limited.

[0055] Specifically, the planarization layer 12 provides a flat surface. The material of the planarization layer 12 includes an organic material, for example, one or more combinations of polyimide, polyethylene terephthalate, polycarbonate, polyethylene or polyacrylate. Here, the material of the planarization layer 12 is not limited.

[0056] Specifically, a first opening 121 is provided on the planarization layer 12, and the first opening 121 is used to improve the problem of failure of the display panel caused by the transmission of water and oxygen from the non-display area DZ to the display area AZ. The orthographic projection of the first opening 121 on the base substrate 11 at least partially surrounds the display area AZ. Optionally, the orthographic projection of the first opening 121 on the base substrate 11 fully surrounds the display area AZ. In this way, the first opening 121 can completely block the path for the transmission of water and oxygen from the non-display area DZ to the display area AZ. The specific morphology of the first opening 121 can be set by those skilled in the art according to actual conditions, and is not limited here. For example, the cross-section of the first opening 121 can be rectangular (such as Figure 4 As shown), trapezoidal, arc-shaped, stepped (as shown Figure 5As shown) or other shapes known to those skilled in the art; the orthographic projection of the first opening 121 on the base substrate 11 may be a rectangular ring, a circular ring or other shapes known to those skilled in the art.

[0057] Specifically, the light-emitting element 30 includes an anode layer 31, a cathode layer 33 and a light-emitting layer 32, and the light-emitting layer 32 is located between the anode layer 31 and the cathode layer 33. A plurality of discrete openings are provided on the pixel spacing layer 13, and the light-emitting layer 32 is provided in the opening, so that adjacent light-emitting elements 30 can be separated by the pixel spacing layer 13. The light-emitting element 30 may also include an auxiliary light-emitting layer, which is used to promote the recombination of holes provided by the anode and electrons provided by the cathode in the light-emitting layer. For example, the auxiliary light-emitting layer includes one or more layers of an electron injection layer, an electron transport layer, an electron blocking layer, a hole blocking layer, a hole transport layer, and a hole injection layer, which are not limited here. Specifically, the light-emitting element 30 may include one or more of a red light-emitting element, a green light-emitting element, a blue light-emitting element, a white light-emitting element, a yellow light-emitting element, a cyan light-emitting element, and a magenta light-emitting element, which are not limited here.

[0058] Specifically, the first signal line 20 is used to transmit signals, and the specific signal type transmitted can be set by those skilled in the art according to actual conditions, and is not limited here. For example, the first signal line 20 is used to transmit data signals, power signals, etc. Specifically, the first signal line 20 includes a first sub-signal line 21 and a second sub-signal line 22, and the orthographic projections of the first sub-signal line 21 and the first opening 121 on the base substrate 11 at least partially overlap. At this time, if the first sub-signal line 21 is located on the surface of the planarization layer 12 facing the base substrate 11, the first opening 121 will expose the first sub-signal line 21, and the exposed first sub-signal line 21 is easily corroded. However, in the present application, by arranging the first sub-signal line 21 and the second sub-signal line 22 in different layers, in other words, sinking the first sub-signal line 21, which was originally in the same layer as the second sub-signal line 22, at least partially covers the first sub-signal line 21 with the insulating layer between the first sub-signal line 21 and the second sub-signal line 22. In this way, the area of ​​the first sub-signal line 21 exposed by the first opening 121 can be reduced, thereby reducing the risk of the first sub-signal line 21 being corroded by water and oxygen. It should be noted that the portion where the orthographic projection of the first sub-signal line 21 on the base substrate 11 overlaps with the orthographic projection of the first opening 121 on the base substrate 11 is the exposed signal segment, and the area of ​​the exposed signal segment covered by the insulating layer between the first sub-signal line 21 and the second sub-signal line 22 can be set by those skilled in the art according to actual conditions and is not limited here. Optionally, the exposed signal segment is completely covered by the insulating layer between the first sub-signal line 21 and the second sub-signal line 22, such as Figure 4 and Figure 5As shown, in this way, the first sub-signal line 21 can be prevented from being exposed to the outside and from being corroded by water and oxygen.

[0059] The display panel provided by the embodiment of the present invention, by setting the first signal line to include a first sub-signal line and a second sub-signal line electrically connected to each other, the first sub-signal line is located on the side of the second sub-signal line facing the base substrate, and the first sub-signal line and the first opening on the planarization layer have an orthographic projection on the base substrate at least partially overlapped, so that the first sub-signal line originally on the same layer as the second sub-signal line can be moved down by at least one layer, so that the insulating layer between the first sub-signal line and the second sub-signal line can at least partially cover the first sub-signal line, reducing the risk of the first sub-signal line being exposed by the first opening, improving the problem of corrosion caused by the exposure of the first sub-signal line, reducing the risk of the first sub-signal line being exposed by the first opening, and thereby improving the yield of the display panel.

[0060] Continue to see Figure 4 Optionally, in a direction perpendicular to the base substrate 11 , an overlapping area of ​​the first sub-signal line 21 and the first opening 121 is S1, and an overlapping area of ​​the second sub-signal line 22 and the first opening 121 is S2, wherein S1>S2≥0.

[0061] It can be understood that, relative to the first sub-signal line 21, the second sub-signal line 22 is closer to the planarization layer 12 and is more easily exposed by the first opening 121, that is, the risk of the second sub-signal line 22 being exposed by the first opening 121 is greater. Therefore, by setting S1>S2, the risk of the first signal line 20 being exposed can be relatively small, and even if it is exposed by the first opening 121, the exposed area can be minimized, thereby reducing the risk of the first signal line 20 being corroded by water and oxygen.

[0062] Figure 6 yes Figure 3 Another cross-sectional view along the BB' direction. Figure 6 Optionally, the second sub-signal line 22 includes a first side edge 221 close to the first opening 121 , and the planarization layer 12 completely covers the first side edge 221 .

[0063] Specifically, the second sub-signal line 22 can be made of titanium-aluminum-titanium material with a relatively small sheet resistance value, that is, the second sub-signal line 22 includes three layers, two titanium film layers sandwiching an aluminum film layer, so that the resistance of the second sub-signal line 22 can be reduced, and the signal loss can be reduced. It can be understood that compared with titanium, aluminum is more easily corroded by water and oxygen. By setting the first side 221 of the second sub-signal line 22 to be completely covered by the planarization layer, the part of the second sub-signal line 22 that is most easily corroded by water and oxygen can be prevented from being exposed, thereby reducing the risk of the second sub-signal line 22 being corroded by water and oxygen.

[0064] It can also be understood that by setting the planarization layer 12 to completely cover the first side 221, the second sub-signal line 22 can be completely covered by the planarization layer 12, so that the second sub-signal line 22 can be prevented from being exposed, thereby reducing the risk of the first signal line 20 being corroded by water and oxygen.

[0065] Continue to see Figure 6 Optionally, the first sub-signal line 21 extends along the first direction X, and in the first direction X, the length of the first sub-signal line 21 is greater than the length of the first opening 121 .

[0066] Specifically, the first signal sub-line 21 includes two second side edges 211 located at two ends of the first signal sub-line 21 . In a direction perpendicular to the base substrate 11 , the two second side edges 211 do not overlap with the first opening 121 .

[0067] Specifically, the first sub-signal line 21 can be made of titanium aluminum titanium material with a smaller block resistance value, so that the resistance of the first sub-signal line 21 can be reduced and the signal loss can be reduced. It can be understood that in the first direction X, by setting the length of the first sub-signal line 21 to be greater than the length of the first opening 121, the first sub-signal line 21 can be used for routing at the first opening 121. When the first sub-signal line 21 passes a certain distance from the first opening 121, it is replaced by the second sub-signal line 22 for routing. In this way, the part of the first sub-signal line 21 that is most susceptible to water and oxygen corrosion is not exposed to the outside, and the failure of the second sub-signal line 22 due to corrosion can be fully avoided. It should be noted that in the first direction X, the length of the first sub-signal line 21 and the length of the first opening 121 can be set by those skilled in the art according to actual conditions, and are not limited here.

[0068] Figure 7 yes Figure 3 Another cross-sectional view along the BB' direction. Figure 7 Optionally, the second sub-signal line 22 includes a first line segment 222 and a second line segment 223, at least part of the first line segment 222 extends to the display area AZ of the display panel, and the first sub-signal line 21 is located in the non-display area DZ of the display panel; wherein the first end of the first sub-signal line 21 is connected to one end of the first line segment 222 through a first via hole 410, the first via hole 410 is located in the non-display area DZ, and the projection direction is perpendicular to the base substrate 11, and there is no overlap between the first via hole 410 and the first opening 121.

[0069] It can be understood that by setting the direction perpendicular to the base substrate 11 as the projection direction, there is no overlap between the first via hole 410 and the first opening 121, so that the first via hole 410 is not set at the first opening 121, so that the failure of the second sub-signal line 22 due to water and oxygen corrosion can be avoided. It should be noted that the distance between the vertical projections of the first via hole 410 and the first opening 121 on the base substrate 11 can be set by those skilled in the art according to actual conditions, and is not limited here.

[0070] Continue to see Figure 7 Optionally, the second line segment 223 is located in the non-display area DZ, and the second end of the first sub-signal line 21 is connected to one end of the second line segment 223 through a second via hole 420; the second via hole 420 is located in the non-display area DZ, and in a direction perpendicular to the base substrate 11, there is no overlap between the second via hole 420 and the first opening 121.

[0071] It can be understood that by setting the direction perpendicular to the base substrate 11 as the projection direction, there is no overlap between the second via hole 420 and the first opening 121, so that the second via hole 420 is not set at the first opening 121, so that the failure of the second sub-signal line 22 due to water and oxygen corrosion can be further avoided. It should be noted that the distance between the vertical projections of the second via hole 420 and the first opening 121 on the base substrate 11 can be set by those skilled in the art according to actual conditions, and is not limited here.

[0072] Continue to see Figure 7 Optionally, the second signal sub-line 22 is connected to the active layer of a transistor through the third via hole 430 in the display area AZ of the display panel, wherein in the direction perpendicular to the base substrate 11, the depth of the first via hole 410 is H1, and the depth of the third via hole 430 is H3, wherein H1≤1 / 2×H3. Optionally, the depth of the second via hole 420 is H2, wherein H2≤1 / 2×H3.

[0073] It can be understood that by setting H1≤1 / 2×H3, the depth of the first via 410 can be made shallower, so that the transmission loss of the first signal line 20 due to the first via 410 can be reduced, and if the depth of the first via 410 is shallower, the process requirements will be relatively low, which is conducive to simplifying the process. The same is true for the second via 420, which will not be repeated here. Exemplarily, when the first signal line 20 is used to transmit the first power signal (PVDD signal), the PVDD signal will be transmitted to the transistor through the second line segment 223, the second via 420, the first sub-signal line 21, the first via 410, the first line segment 222 and the third via 430 in sequence. Setting the depth of the first via 410 (or the second via 420) to be shallower can make the loss of the PVDD signal in the entire transmission process relatively small, thereby avoiding affecting the size of the driving current and ensuring the accurate driving of the display panel. It should be noted that the specific depths of the first via hole 410 , the second via hole 420 , and the third via hole 430 can be set by those skilled in the art according to actual conditions and are not limited here.

[0074] Continue to see Figure 7 Optionally, the second sub-signal line 22 is connected to the active layer of a transistor through the third via hole 430 in the display area AZ of the display panel, wherein, in the plane where the side of the first via hole 410 in contact with the second sub-signal line 22 is located, the area of ​​the first via hole 410 is larger than the area of ​​the third via hole 430. Optionally, in the plane where the side of the second via hole 420 in contact with the second sub-signal line 22 is located, the area of ​​the second via hole 420 is larger than the area of ​​the third via hole 430.

[0075] It can be understood that by setting the area of ​​the first via 410 to be larger than the area of ​​the third via 430, the area of ​​the first via 410 can be relatively large, so that the transmission loss on the first signal line 20 due to the first via 410 can be reduced. The same is true for the second via 420, which will not be repeated here. Exemplarily, when the first signal line 20 is used to transmit a PVDD signal, the portion of the first signal line 20 located in the non-display area DZ is called the first power transmission line (PVDD transmission line), and the portion of the first signal line 20 located in the display area AZ is called the PVDD signal line, and the line width of the PVDD transmission line is greater than the line width of the PVDD signal line. By setting the area of ​​the first via 410 to be larger than the area of ​​the third via 430, the line widths of the first via 410 and the PVDD transmission line can be matched, and at the same time, the line widths of the third via 430 and the PVDD signal line can be matched, and the signal loss on the PVDD transmission line can be reduced. It should be noted that the specific areas of the first via hole 410 , the second via hole 420 , and the third via hole 430 can be set by those skilled in the art according to actual conditions and are not limited here.

[0076] Figure 8 yes Figure 3 A cross-sectional view along the BB' direction. Figure 8 Optionally, the first sub-signal line 21 includes a first layer routing 212 and a second layer routing 213 which are electrically connected to each other and stacked; in a direction perpendicular to the base substrate 11, the first layer routing 212 and the second layer routing 213 at least partially overlap with the first opening 121.

[0077] Specifically, the first layer wiring 212 can be located on the side of the second layer wiring 213 facing the base substrate 11, or on the side of the second layer wiring 213 facing away from the base substrate 11, which is not limited here. The first layer wiring 212 and the second layer wiring 214 can be connected by vias.

[0078] It can be understood that by setting the first sub-signal line 21 as a double-layer routing line, the resistance on the first sub-signal line 21 can be sufficiently reduced, thereby reducing signal loss.

[0079] Fig. 9 yes Figure 3 Another cross-sectional view along the BB' direction. Fig. 9 Optionally, the second sub-signal line 22 includes a third-layer routing 224 and a fourth-layer routing 225 that are electrically connected to each other, the fourth-layer routing 225 is located on the side of the planarization layer 12 away from the third-layer routing 224, and the third-layer routing 224 is electrically connected to the fourth-layer routing 225 through a via; in a direction perpendicular to the base substrate 11, there is no overlap between the third-layer routing 224 and the fourth-layer routing 225 and the first opening 121.

[0080] It can be understood that by setting the second signal sub-line 22 as a double-layer routing line, the resistance on the second signal sub-line 22 can be sufficiently reduced, thereby reducing signal loss.

[0081] Continue to see Figure 2-Figure 9 Optionally, in a direction perpendicular to the base substrate 11 , a first insulating layer 14 is included between the first sub-signal line 21 and the first opening 121 , and the first insulating layer 14 includes silicon oxide or silicon oxynitride.

[0082] It is understandable that among the devices inside the display panel, some devices are very sensitive to the hydrogen content in the display panel. Since silicon oxide and silicon oxynitride have a good effect of blocking hydrogen, the first insulating layer 14 is provided to include silicon oxide or silicon oxynitride, so that the first insulating layer 14 can play a better role in preventing hydrogen from entering the device inside the display panel. In addition, silicon nitride also has a good effect of blocking water and oxygen. When the first insulating layer 14 includes silicon nitride, the silicon nitride above the first sub-signal line 21 can also effectively prevent it from being corroded by water and oxygen, thereby improving the yield of the display panel. It should be noted that the thickness of the first insulating layer 14 can be set by those skilled in the art according to actual conditions, and is not limited here.

[0083] Fig.10 yes Figure 3 Another cross-sectional view along the BB' direction. Fig.10 Optionally, in a direction perpendicular to the base substrate 11 , a second insulating layer 15 stacked with the first insulating layer 14 is included between the first sub-signal line 21 and the first opening 121 , the second insulating layer 15 includes silicon nitride, and the first insulating layer 14 is located on a side of the second insulating layer 15 facing the first sub-signal line 21 .

[0084] It is understandable that, compared with silicon nitride, silicon oxide has a better effect of blocking hydrogen; compared with silicon oxide, silicon nitride has a better effect of blocking water and oxygen. Therefore, silicon nitride is first set at a position closer to the first opening 121 to block water and oxygen. In other words, silicon nitride with a stronger ability to block water and oxygen is set near the starting point of water and oxygen invasion, which can strongly block water and oxygen as early as possible to prevent water and oxygen from invading the display panel and affecting other devices. Then, silicon oxide is set closer to the first sub-signal line 21 to block hydrogen. It should be noted that the specific thickness of the first insulating layer 14 and the second insulating layer 15 can be set by those skilled in the art according to actual conditions and is not limited here.

[0085] Continue to see Fig.10 Optionally, the thickness of the first insulating layer 14 is greater than the thickness of the second insulating layer 15 .

[0086] It can be understood that, generally, the hydrogen content in silicon nitride is higher than that in silicon oxide, and hydrogen can be more fully blocked by setting the thickness of the first insulating layer 14 to be greater than the thickness of the second insulating layer 15 .

[0087] Optionally, the hydrogen content of the first insulating layer 14 on a side facing the first sub-signal line 21 is smaller than the hydrogen content of the first insulating layer 14 on a side away from the first sub-signal line 21 .

[0088] It is understandable that by setting the hydrogen content of the first insulating layer 14 on the side facing the first sub-signal line 21 to be less than the hydrogen content on the side away from the first sub-signal line 21, hydrogen can be more fully blocked. It should be noted that the hydrogen content of each part in the first insulating layer 14 can be set by those skilled in the art according to actual conditions, and is not limited here. Exemplarily, the first insulating layer 14 includes a plurality of first sub-insulating layers, and as the distance between the first sub-insulating layer and the first sub-signal line 21 is closer, the hydrogen content of the first sub-insulating layer is smaller.

[0089] Fig.11 yes Figure 3 Another cross-sectional view along the BB' direction. Fig.11Optionally, the display panel also includes an encapsulation layer 40, the encapsulation layer 40 includes a first inorganic layer 41, a second inorganic layer 43, and an organic layer 42 located between the first inorganic layer 41 and the second inorganic layer 43, the second inorganic layer 43 is located on the side of the first inorganic layer 41 away from the base substrate 11; wherein the encapsulation layer 40 fills the first opening 121, and the first inorganic layer 41 covers the surface of the first opening 121 facing the encapsulation layer 40; at least one insulating layer is included between the first inorganic layer 41 and the first sub-signal line 21.

[0090] Specifically, the encapsulation layer 40 plays a role in blocking water and oxygen. The materials of the first inorganic layer 41 and the second inorganic layer 43 can be aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium oxide, zirconium oxide or zinc oxide, or other inorganic materials known to those skilled in the art, and the material of the organic layer 42 can be polyimide, polyethylene terephthalate, polycarbonate, polyethylene or polyacrylate, or other organic materials known to those skilled in the art, which are not limited here.

[0091] Specifically, the first inorganic layer 41 covers the bottom and sidewalls of the first opening 121. In other words, the first inorganic layer 41 fills the first opening 121. It can be understood that the encapsulation layer 40 covers the first opening 121, and at least one insulating layer is included between the first inorganic layer 41 and the first sub-signal line 21, so that the first sub-signal line 21 is protected by the insulating layer to prevent the first sub-signal line 21 from being corroded.

[0092] Fig.12 Optionally, the display panel further includes a second signal line 50, the second signal line 50 and the second sub-signal line 22 are located in the same film layer, and in a direction perpendicular to the base substrate 11, the first sub-signal line 21 and the second signal line 50 at least partially overlap.

[0093] It should be noted that the same film layer described here and below refers to a film layer prepared by the same process and generally has the same material.

[0094] Specifically, the second signal line 50 is used to transmit a signal, and the specific signal type transmitted can be set by a person skilled in the art according to actual conditions, and is not limited here. For example, the second signal line 50 is used to transmit a second power signal (PVEE signal). It can be understood that when the second signal line 50 is used to transmit a PVEE signal, in order to achieve that the second signal line 50 does not overlap with the first opening 121 as much as possible in the direction perpendicular to the base substrate 11, and the second signal line 50 is allowed to surround the display area AZ as much as possible, it is necessary to set the first sub-signal line 21 to at least partially overlap with the second signal line 50, so that the design difficulty of the first signal line 20 and the second signal line 50 can be reduced.

[0095] Continue to see Fig.12 Optionally, in a direction perpendicular to the base substrate 11, the second signal line 50 does not overlap with the first opening 121. In this way, the second signal line 50 can be prevented from being exposed by the first opening 121 and corroded by water and oxygen, which is beneficial to improving the yield of the display panel.

[0096] Continue to see Fig.12 Optionally, the display panel includes a display area AZ and a non-display area DZ, the first opening 121 is located in the non-display area DZ, and the second signal line 50 is located on a side of the first opening 121 away from the display area AZ.

[0097] Specifically, by arranging the second signal line 50 to be located outside the first opening 121, it is possible to achieve that the second signal line 50 does not overlap with the first opening 121, thereby preventing the second signal line 50 from being exposed by the first opening 121. It should be noted that the distance between the orthographic projection of the second signal line 50 and the first opening 121 on the base substrate 11 can be set by those skilled in the art according to actual conditions, and is not limited here.

[0098] Fig.13 yes Fig.12 A cross-section along CC'. Fig.13 Optionally, the display panel includes a display area AZ and a non-display area DZ, and the first opening 121 is located in the non-display area DZ; the light-emitting element includes a cathode layer 33, and in a direction perpendicular to the base substrate 11, the cathode layer 33 and the first opening 121 have no overlap; the display panel also includes a connecting electrode layer 60, and the second signal line 50 is electrically connected to the cathode layer 33 through the connecting electrode layer 60; the connecting electrode layer 60 is connected to the second signal line 50 on a side of the first opening 121 away from the display area AZ, and is connected to the cathode layer 33 on a side of the first opening 121 close to the display area AZ.

[0099] It is understandable that the material of the cathode layer 33 is usually a magnesium-aluminum alloy, which is also easily corroded by water and oxygen when exposed to the outside. By setting the cathode layer 33 and the first opening 121 to have no overlap, the cathode layer 33 can be prevented from being corroded by water and oxygen. The second signal line 50 and the cathode layer 33 are located on both sides of the first opening 121. The electrical connection between the second signal line 50 and the cathode layer 33 can be achieved by setting a connecting electrode layer 60 to connect the second signal line 50 and the cathode layer 33, so that the PVEE signal can be smoothly transmitted from the second signal line 50 to the cathode layer 33. It should be noted that the shape of the positive projection of the connecting electrode layer 60 on the base substrate 11 can be set by those skilled in the art according to actual conditions, and is not limited here.

[0100] Fig.14 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig.14Optionally, the display panel includes a display area AZ and a non-display area DZ, the first opening 121 is located in the non-display area DZ, the second signal line 50 includes a third sub-signal line 51 and a fourth sub-signal line 52, the third sub-signal line 51 is located on a side of the first opening 121 close to the display area AZ, and the fourth sub-signal line 52 is located on a side of the first opening 121 away from the display area AZ; the display panel also includes a connecting line 53, the third sub-signal line 51 and the fourth sub-signal line 52 are electrically connected through the connecting line 53; the connecting line 53 and the first sub-signal line 21 are arranged in the same layer, and in a direction perpendicular to the base substrate 11, the connecting line 53 and the first opening 121 at least partially overlap.

[0101] Specifically, the third sub-signal line 51 and the fourth sub-signal line 52 are located on both sides of the first opening 121, and they are electrically connected through the connecting line 53. Fig.13 As shown, when the second signal line 50 is used to transmit the PVEE signal, the third sub-signal line 51 can surround the display area AZ, so that the cathode layer 33 in the display panel is easily connected to the third sub-signal line 51.

[0102] It is understandable that in the direction perpendicular to the base substrate 11, the third sub-signal line 51 does not overlap with the first opening 121, and at the same time, the fourth sub-signal line 52 does not overlap with the first opening 121. In this way, the first opening 121 can be prevented from exposing the second signal line 50, thereby preventing them from being corroded by water and oxygen.

[0103] It can also be understood that by setting the connecting wire 53 and the first sub-signal wire 21 in the same layer, the connecting wire 53 can be at least partially covered by the insulating layer between the first sub-signal wire 21 and the second sub-signal wire 22, so that the area of ​​the connecting wire 53 exposed by the first opening 121 can be reduced, thereby reducing the risk of the connecting wire 53 being corroded by water and oxygen. It should be noted that the part where the orthographic projection of the connecting wire 53 on the base substrate 11 overlaps with the orthographic projection of the first opening 121 on the base substrate 11 is the exposed connecting section, and the area of ​​the exposed connecting section covered by the insulating layer between the first sub-signal wire 21 and the second sub-signal wire 22 can be set by those skilled in the art according to actual conditions, and is not limited here. Optionally, the exposed connecting section is completely covered by the insulating layer between the first sub-signal wire 21 and the second sub-signal wire 22, so that the connecting wire 53 can be prevented from being exposed to the outside and corroded by water and oxygen.

[0104] Fig.15 yes Fig.14 A cross-section along DD'. Fig.15Optionally, the light emitting element includes a cathode layer 33 , and in a direction perpendicular to the base substrate 11 , the cathode layer 33 has no overlap with the first opening 121 ; the display panel also includes a connecting electrode layer 60 , and the third sub-signal line 51 is electrically connected to the cathode layer 33 through the connecting electrode layer 60 .

[0105] It is understandable that the third sub-signal line 51 and the cathode layer 33 are usually not located in the same layer. By setting a connecting electrode layer 60 to connect the third sub-signal line 51 and the cathode layer 33, the electrical connection between the second signal line 50 and the cathode layer 33 can be achieved, so that the PVEE signal can be smoothly transmitted from the second signal line 50 to the cathode layer 33. It should be noted that the shape of the positive projection of the connecting electrode layer 60 on the base substrate 11 can be set by those skilled in the art according to actual conditions, and is not limited here. It should be noted that in the direction perpendicular to the base substrate 11, the connecting electrode layer 60 can overlap with the first opening 121, and can also not overlap with the first opening 121, which is not limited here.

[0106] Fig.16 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig.16 Optionally, in a direction perpendicular to the base substrate 11 , the second signal line 50 at least partially overlaps with the first opening 121 , and any side edge of the second signal line 50 does not overlap with the first opening 121 .

[0107] Specifically, in the direction perpendicular to the base substrate 11, the degree of overlap between the second signal line 50 and the first opening 121 can be set by those skilled in the art according to actual conditions, and is not limited here. It can be understood that the greater the degree of overlap between the second signal line 50 and the first opening 121, the smaller the area of ​​the non-display zone DZ occupied by the second signal line 50 and the first opening 121, which is more conducive to achieving a narrow frame.

[0108] Specifically, the second signal line 50 can be made of titanium-aluminum-titanium material with a smaller block resistance value, that is, the second signal line 50 includes three layers, two titanium film layers sandwiching aluminum film layers, so that the resistance of the second signal line 50 can be reduced and the signal loss can be reduced. Compared with titanium, aluminum is more easily corroded by water and oxygen. By setting any side edge of the second signal line 50 without overlapping with the first opening 121, aluminum is not exposed to the outside, reducing the risk of the second signal line 50 being corroded by water and oxygen. It should be noted that the distance between the orthographic projection of each side edge of the second signal line 50 on the base substrate 11 and the orthographic projection of the first opening 121 on the base substrate 11 can be set by those skilled in the art according to actual conditions and is not limited here.

[0109] Continuing to refer to FIG. 16 , optionally, in a direction perpendicular to the base substrate 11 , the orthographic projection of the first opening 121 on the base substrate 11 is located within the orthographic projection of the second signal line 50 on the base substrate 11 .

[0110] It can be understood that, in the direction perpendicular to the base substrate 11, by setting the orthographic projection of the first opening 121 on the base substrate 11 to be within the orthographic projection of the second signal line 50 on the base substrate 11, there is no need to reserve a separate area in the non-display area DZ for setting the first opening 121, which is beneficial to reducing the area of ​​the non-display area DZ and thereby improving the screen-to-body ratio.

[0111] Fig.17 yes Fig.16 A cross-section along EE'. Fig.17 Optionally, the display panel includes a display area AZ and a non-display area DZ, and the first opening 121 is located in the non-display area DZ; the light-emitting element includes a cathode layer 33, and in a direction perpendicular to the base substrate 11, the cathode layer 33 and the first opening 121 have no overlap; the display panel also includes a connecting electrode layer 60, and the second signal line 50 is electrically connected to the cathode layer 33 through the connecting electrode layer 60; the connecting electrode layer 60 is connected to the second signal line 50 at the location of the first opening 121, and is connected to the cathode layer 33 on the side of the first opening 121 close to the display area AZ.

[0112] It is understandable that the cathode layer 33 and the second signal line 50 are usually located in different film layers, and the electrical connection between the second signal line 50 and the cathode layer 33 can be achieved by setting a connecting electrode layer 60 to connect the second signal line 50 and the cathode layer 33, so that the PVEE signal can be smoothly transmitted from the second signal line 50 to the cathode layer 33. It is also understandable that by setting the connecting electrode layer 60 to connect with the second signal line 50 at the location of the first opening 121, there is no need for additional separate drilling to achieve the connection between the second signal line 50 and the cathode layer 33, which is conducive to simplifying the preparation process of the display panel and reducing costs. It should be noted that the shape of the positive projection of the electrode connection layer on the base substrate 11 can be set by those skilled in the art according to actual conditions, and is not limited here.

[0113] Fig.18 It is a structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.19 It is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig. 20 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 18-Figure 20Optionally, the display panel also includes a second opening 122 located on a side of the first opening 121 away from the display area AZ; in a direction perpendicular to the base substrate 11, the second signal line 50 and the second opening 122 do not overlap; or, in a direction perpendicular to the base substrate 11, the second signal line 50 and the second opening 122 at least partially overlap, and there is no overlap between any side edge of the second signal line 50 and the second opening 122.

[0114] Specifically, there are many specific implementations for the second signal line 50 and the second opening 122 not to overlap in the direction perpendicular to the base substrate 11, which can be set by those skilled in the art according to actual conditions and are not limited here. A typical example is described below. For example, see Fig.18 , the second opening 122 is located in the non-display area DZ, and the second signal line 50 is located on a side of the second opening 122 away from the display area AZ. Fig.19 The second signal line 50 includes a third sub-signal line 51 and a fourth sub-signal line 52. The third sub-signal line 51 is located on the side of the second opening 122 close to the display area AZ, and the fourth sub-signal line 52 is located on the side of the second opening 122 away from the display area AZ. The display panel also includes a connecting line 53, and the third sub-signal line 51 and the fourth sub-signal line 52 are electrically connected through the connecting line 53. The connecting line 53 and the first sub-signal line 21 are arranged in the same layer, and in the direction perpendicular to the base substrate 11, the connecting line 53 and the second opening 122 at least partially overlap. It should be noted that Fig.19 The figure only exemplarily shows that the third sub-signal line 51 is located on the side of the first opening 121 close to the display area AZ, but this is not a limitation of the present application. In other embodiments, the third sub-signal line 51 can also be arranged between the first opening 121 and the second opening 122.

[0115] It is understandable that, in the direction perpendicular to the base substrate 11 , by arranging the second signal line 50 and the second opening 122 to not overlap, the second signal line 50 can be prevented from being exposed by the second opening 122 and corroded by water and oxygen, which is beneficial to improving the yield of the display panel.

[0116] Specifically, in the direction perpendicular to the base substrate 11, when the second signal line 50 and the second opening 122 at least partially overlap, the degree of overlap between the second signal line 50 and the second opening 122 can be set by a person skilled in the art according to actual conditions, and is not limited here. It can be understood that the greater the degree of overlap between the second signal line 50 and the second opening 122, the smaller the area of ​​the non-display zone DZ occupied by the second signal line 50 and the second opening 122, which is more conducive to achieving a narrow frame. Optionally, see Fig. 20In the direction perpendicular to the base substrate 11, the orthographic projection of the second opening 122 on the base substrate 11 is located within the orthographic projection of the second signal line 50 on the base substrate 11. In this way, there is no need to reserve a separate area in the non-display zone DZ for arranging the second opening 122, which is conducive to reducing the area of ​​the non-display zone DZ and thus improving the screen-to-body ratio.

[0117] It is understandable that the second signal line 50 can be made of titanium-aluminum-titanium material with a smaller square resistance value to reduce the resistance of the second signal line 50 and reduce signal loss. Compared with titanium, aluminum is more easily corroded by water and oxygen. By setting any side edge of the second signal line 50 without overlapping with the second opening 122, aluminum is not exposed to the outside, reducing the risk of the second signal line 50 being corroded by water and oxygen. It should be noted that the distance between the orthographic projection of each side edge of the second signal line 50 on the base substrate 11 and the orthographic projection of the second opening 122 on the base substrate 11 can be set by those skilled in the art according to actual conditions and is not limited here.

[0118] It can also be understood that by providing the planarization layer 12 with a second opening 122, a protection against water and oxygen transmission from the non-display area DZ to the display area AZ can be added, thereby improving the ability of the display panel to block water and oxygen. Figure 18-Figure 20 The second opening 122 is only exemplarily shown to surround the display area AZ, but this is not a limitation of the embodiment of the present invention. For example, in other implementations, the second opening 122 may be arranged to half surround the display area AZ.

[0119] Fig.21 yes Fig. 20 A cross-section along the FF' direction. Fig.21 Optionally, in a direction perpendicular to the base substrate 11, the second signal line 50 at least partially overlaps with the second opening 122, and there is no overlap between any side edge of the second signal line 50 and the second opening 122; the connecting electrode layer 60 is also connected to the second signal line 50 at the location of the second opening 122.

[0120] It can be understood that by arranging the connection electrode layer 60 to be connected to the second signal line 50 at the location of the second opening 122 , the contact area between the second signal line 50 and the cathode layer 33 can be increased, thereby improving the electrical connection quality between the two.

[0121] Continuing with FIG. 21 , optionally, a first retaining wall 71 is disposed between the first opening 121 and the second opening 122 , and the first retaining wall 71 is disposed on the same layer as the pixel spacing layer 13 .

[0122] Specifically, the first retaining wall 71 is used to prevent the organic layer 42 in the encapsulation layer 40 from continuing to spread in the direction from the display area AZ to the non-display area DZ. For the area in the non-display area DA where the first retaining wall 71 is far away from the display area AZ, when covering the encapsulation layer 40, due to the effect of the first retaining wall 71, the area will not cover the organic layer 42, so the external water and oxygen will not spread from the encapsulation layer 40 to the display area AZ, and due to the effect of the first opening 121 and the second opening 122, the planarization layer 12 is disconnected at the second opening 122, so the external water and oxygen will not spread from the planarization layer 12 to the display area AZ. It can be seen that the first retaining wall 71, the first opening 121 and the second opening 122 reduce the possibility of external water and oxygen invading the display area AZ, and enhance the ability of the display panel to block water and oxygen.

[0123] It can be understood that by arranging the first retaining wall 71 and the pixel spacing layer 13 in the same layer, there is no need to add an additional process for preparing the first retaining wall 71 , thus simplifying the manufacturing process of the display panel and reducing costs.

[0124] Fig. 22 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig. 22 Optionally, the display panel further includes a third opening 123 located on a side of the second opening 122 away from the display area AZ, and in a direction from the non-display area DZ to the display area AZ, a width of the third opening 123 is greater than a width of the second opening 122 and a width of the first opening 121.

[0125] It is understandable that by providing the planarization layer 12 with the third opening 123 , an additional protection against the transmission of water and oxygen from the non-display area DZ to the display area AZ can be provided, thereby improving the ability of the display panel to block water and oxygen.

[0126] It can also be understood that there are process fluctuations in the actual preparation process. The larger the width of the opening set on the planarization layer 12, the smaller the risk that the opening cannot penetrate the planarization layer 12 due to process fluctuations, and the stronger the ability to block water and oxygen. Therefore, in the direction from the non-display area DZ to the display area AZ, by setting the width of the third opening 123 to be greater than the width of the second opening 122 and the width of the first opening 121, it is equivalent to setting the opening with the strongest blocking ability close to the starting point of water and oxygen invasion, which can strongly block water and oxygen as early as possible to prevent water and oxygen from invading the display panel and affecting other devices.

[0127] Fig.23 It is a structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.24 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 22-Figure 24Optionally, in a direction perpendicular to the substrate 11, the second signal line 50 and the third opening 123 do not overlap; or, in a direction perpendicular to the substrate 11, the second signal line 50 and the third opening 123 at least partially overlap, and there is no overlap between any side edge of the second signal line 50 and the third opening 123.

[0128] Specifically, there are many specific implementations for the second signal line 50 and the third opening 123 not to overlap in the direction perpendicular to the substrate 11, which can be set by those skilled in the art according to actual conditions and are not limited here. A typical example is described below. For example, see Fig. 22 , the third opening 123 is located in the non-display area DZ, and the second signal line 50 is located on a side of the third opening 123 away from the display area AZ. Fig.23 The second signal line 50 includes a third sub-signal line 51 and a fourth sub-signal line 52. The third sub-signal line 51 is located on the side of the first opening 121 close to the display area AZ, and the fourth sub-signal line 52 is located on the side of the third opening 123 away from the display area AZ. The display panel also includes a connecting line 53, and the third sub-signal line 51 and the fourth sub-signal line 52 are electrically connected through the connecting line 53. The connecting line 53 and the first sub-signal line 21 are arranged in the same layer, and in the direction perpendicular to the base substrate 11, the connecting line 53 at least partially overlaps with the first opening 121 and the third opening 123. It should be noted that Fig.23 The figure only illustrates that the third sub-signal line 51 is located on the side of the first opening 121 close to the display area AZ, but this is not a limitation of the present application. In other embodiments, the third sub-signal line 51 can also be arranged between the first opening 121 and the second opening 122, or between the second opening 122 and the third opening 123.

[0129] It is understandable that, in the direction perpendicular to the base substrate 11 , by arranging the second signal line 50 and the third opening 123 not to overlap, the second signal line 50 can be prevented from being exposed by the third opening 123 and from being corroded by water and oxygen, which is beneficial to improving the yield of the display panel.

[0130] Specifically, in the direction perpendicular to the base substrate 11, when the second signal line 50 overlaps with the third opening 123, the degree of overlap between the second signal line 50 and the third opening 123 can be set by those skilled in the art according to actual conditions, and is not limited here. It can be understood that the greater the degree of overlap between the second signal line 50 and the third opening 123, the smaller the area of ​​the non-display zone DZ occupied by the second signal line 50 and the third opening 123, which is more conducive to achieving a narrow frame. Optionally, see Fig.24In the direction perpendicular to the base substrate 11, the orthographic projection of the third opening 123 on the base substrate 11 is located within the orthographic projection of the second signal line 50 on the base substrate 11. In this way, there is no need to reserve an area in the non-display area DZ for setting the third opening 123, which is conducive to reducing the area of ​​the non-display area DZ and thus improving the screen-to-body ratio.

[0131] It is understandable that the second signal line 50 can be made of titanium-aluminum-titanium material with a smaller square resistance value to reduce the resistance of the second signal line 50 and reduce signal loss. Compared with titanium, aluminum is more easily corroded by water and oxygen. By setting any side edge of the second signal line 50 without overlapping with the third opening 123, aluminum is not exposed to the outside, reducing the risk of the second signal line 50 being corroded by water and oxygen. It should be noted that the distance between the orthographic projection of each side edge of the second signal line 50 on the base substrate 11 and the orthographic projection of the third opening 123 on the base substrate 11 can be set by those skilled in the art according to actual conditions and is not limited here.

[0132] It can also be understood that by providing the planarization layer 12 with a third opening 123, an additional protection can be provided to block the transmission of water and oxygen from the non-display area DZ to the display area AZ, thereby improving the ability of the display panel to block water and oxygen. Figure 22-Figure 24 It is only exemplarily shown that the third opening 123 surrounds the display area AZ, but this is not a limitation of the embodiment of the present invention. For example, in other implementations, the third opening 123 may be arranged to half surround the display area AZ.

[0133] It should be noted that the shapes of the second opening 122 and the third opening 123 can be set with reference to the first opening 121 , which will not be described here in detail and can be understood by referring to the above text.

[0134] Fig.25 yes Fig.24 A cross-section along the GG' direction. Fig.25 Optionally, a second retaining wall 72 is disposed between the second opening 122 and the third opening 123 , and at least a portion of the second retaining wall 72 is disposed on the same layer as the pixel spacing layer 13 .

[0135] Specifically, the second retaining wall 72 is used to prevent the organic layer 42 in the encapsulation layer 40 from continuing to spread in the direction from the display area AZ to the non-display area DZ. When covering the encapsulation layer 40, due to the effect of the second retaining wall 72, the area in the non-display area DZ located on the side of the second retaining wall 72 away from the display area AZ will not cover the organic layer, so the external water and oxygen will not spread to the display area AZ through the encapsulation layer 40, and due to the effect of the first opening 121, the second opening 122 and the third opening 123, the planarization layer 12 is disconnected at the second opening 122, so the external water and oxygen will not spread from the planarization layer 12 to the display area AZ. It can be seen that the combined effect of the second retaining wall 72, the first opening 121, the second opening 122 and the third opening 123 greatly reduces the possibility of external water and oxygen invading the display area AZ, and enhances the ability of the display panel to block water and oxygen.

[0136] It can be understood that by setting at least part of the second retaining wall 72 on the same layer as the pixel spacer layer 13, the part of the second retaining wall 72 that is set on the same layer as the pixel spacer layer 13 can be formed through the same preparation process as the pixel spacer layer 13, which is beneficial to simplify the preparation process of the second retaining wall 72 and thus reduce the cost of the display panel.

[0137] Continue to see Fig.25 Optionally, in a direction perpendicular to the base substrate 11 , a height of the second retaining wall 72 is greater than a height of the pixel spacing layer 13 .

[0138] It is understandable that by setting the height of the second retaining wall 72 to be greater than the height of the pixel spacing layer 13, the height of the second retaining wall 72 can be higher, thereby making the second retaining wall 72 more capable of blocking the organic layer 42. In addition, when the display panel is covered with a cover plate, the second retaining wall 72 can also play a supporting role.

[0139] Continue to see Fig.12 , Fig.14 , Fig.16 , Figure 18-Figure 20 , Figure 22-Figure 24 Optionally, the first signal line 20 provides a first power signal for the pixel circuit of the display panel, and the second signal line 50 provides a second power signal for the light-emitting element of the display panel. One of the first power signal and the second power signal is a high level signal and the other is a low level signal.

[0140] Specifically, the first power signal, namely, the PVDD signal, provides a signal for the anode of the light-emitting element, and the second power signal, namely, the PVEE signal, provides a signal for the cathode of the light-emitting element.

[0141] It should be noted that for the convenience of drawing, Fig.12 , Fig.14 , Fig.16 , Figure 18-Figure 20 , Figure 22-Figure 24 The portion where the first signal line 20 extends to display AZ is not shown, which can be understood by those skilled in the art based on the prior art and will not be described in detail here.

[0142] Fig.26 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig.26 Optionally, the first signal line 20 is used to provide a data signal to a pixel circuit of the display panel.

[0143] Specifically, the data signal, namely the Vdata signal, determines the magnitude of the driving current flowing through the light-emitting element, and further determines the light-emitting brightness of the light-emitting element.

[0144] Continue to see Figure 4-Figure 11 Optionally, the display panel includes a first transistor 80 and a second transistor 90; the first transistor 80 includes a first gate 81, a first source 82, a first drain 83 and a first active layer 84; the second transistor 90 includes a second gate 91, a second source 92, a second drain 93 and a second active layer 94; wherein the first active layer 84 includes an oxide semiconductor, the second active layer 94 includes silicon, and the first active layer 84 is located on a side of the second active layer 94 away from the substrate 11; the second sub-signal line 22 is located on the same layer as at least one of the first source 82, the first drain 83, the second source 92 and the second drain 93.

[0145] Specifically, the specific material of the first active layer 84 can be set by those skilled in the art according to actual conditions, and is not limited here. Exemplarily, the material of the first active layer 84 can be selected from indium gallium zinc oxide, etc. Specifically, the specific materials of the first gate 81, the second gate 91, the first source 82, the first drain 83, the second source 92, and the second drain 93 can also be set by those skilled in the art according to actual conditions, and are not limited here. Exemplarily, the materials of the first gate 81 and the second gate 91 can be molybdenum, titanium aluminum titanium, etc. The materials of the first source 82, the first drain 83, the second source 92, and the second drain 93 can be molybdenum aluminum molybdenum, titanium aluminum titanium, etc. It should be noted that the formation method of each structure in the first transistor 80 and the second transistor 90 can be physical vapor deposition, chemical vapor deposition, inkjet printing, or other methods known to those skilled in the art, and the formation method of each structure can be set according to the actual needs of the display panel manufacturing method, and is not limited here.

[0146] Specifically, the first transistor 80 and the second transistor 90 can be a top gate structure or a bottom gate structure, which is not limited here. Specifically, there are various relative position relationships among the first source 82, the first drain 83, the second source 92 and the second drain 93, which can be set by those skilled in the art according to actual conditions, which is not limited here. Exemplarily, the first source 82 and the first drain 83 are located on the same layer, the second source 92 and the second drain 93 are located on the same layer, the first drain 83 and the second drain 93 can be located on the same layer or on different layers. Optionally, the first source 82, the first drain 83, the second source 92, and the second drain 93 are located on the same layer (such as Figure 4-Figure 11 As shown), they can be prepared by the same process, which is beneficial to simplify the process and to achieve a thin display panel.

[0147] Specifically, the material of the second sub-signal line 22 can be set by a person skilled in the art according to actual conditions, and is not limited here. For example, the material of the second sub-signal line 22 can be titanium aluminum titanium, molybdenum aluminum, etc. Optionally, the material of the second sub-signal line 22 is titanium aluminum titanium with a smaller sheet resistance value, so that the resistance of the second sub-signal line 22 can be smaller, which is conducive to reducing signal loss.

[0148] Continue to see Figure 4-Figure 11 Optionally, the first gate 81 is located on a side of the second gate 91 facing away from the substrate 11 .

[0149] Specifically, when the first active layer 84 is located on the side of the second active layer 94 away from the substrate 11, the first gate 81 is located on the side of the second gate 91 away from the substrate 11, and the first source 82, the first drain 83, the second source 92, and the second drain 93 are located on the same layer, by setting the first gate 81 to be located on the side of the second gate 91 away from the substrate 11, the depth of the via hole in the first transistor 80 can be relatively shallow, and the process requirements are relatively low. The via hole in the transistor described here and below refers to the via hole used to connect the active layer and the source electrode, and the via hole used to connect the active layer and the drain electrode, for example Figure 7 The third via hole 430 in FIG.

[0150] Continue to see Figure 4 , Figure 6 , Figure 7 as well as Fig. 9 Optionally, the first sub-signal line 21 is located on a side of the first active layer 84 away from the base substrate 11 .

[0151] Specifically, the material of the first sub-signal line 21 can be set by a person skilled in the art according to actual conditions, and is not limited here. Exemplarily, the material of the first sub-signal line 21 can be titanium-aluminum-titanium, molybdenum-aluminum-molybdenum, etc. Optionally, the material of the first sub-signal line 21 is titanium-aluminum-titanium with a smaller sheet resistance value, so that the resistance of the first sub-signal line 21 can be smaller, which is beneficial to reduce signal loss.

[0152] It can be understood that the first active layer 84 is located on the side of the second active layer 94 away from the base substrate 11. When the first source 82, the first drain 83, the second source 92, and the second drain 93 are located on the same layer, the via hole in the first transistor 80 is relatively shallow, and the via hole in the second transistor 90 is relatively deep. By arranging the first sub-signal line 21 to be located on the side of the first active layer 84 away from the base substrate 11, the via hole (for example, Figure 7 The depths of the first via hole 410 and the second via hole 420 are relatively shallow, so that the signal loss of the first signal line 20 due to the via holes can be minimized. Moreover, if the via holes are shallow, the process requirements are relatively low, which is conducive to simplifying the process.

[0153] Continue to see Figure 4 , Figure 6 , Figure 7 as well as Fig. 9 Optionally, the first sub-signal line 21 and the first gate 81 are located in the same film layer.

[0154] It is understandable that by arranging the first sub-signal line 21 and the first gate 81 in the same film layer, the first sub-signal line 21 and the first gate 81 can be manufactured through the same process, which is beneficial to reducing costs and achieving a thinner display panel.

[0155] Continue to see Figure 7 , Fig. 9 as well as Fig.11 Optionally, the first transistor 80 also includes a third gate 85, the first gate 81 is located on the side of the first active layer 84 away from the substrate 11, and the third gate 85 is located on the side of the first active layer 84 toward the substrate 11; wherein the first gate 81 and the third gate 85 are both located on the side of the second gate 91 away from the substrate 11, and the first sub-signal line 21 and the first gate 81 or the third gate 85 are located in the same film layer.

[0156] Specifically, the material of the third gate 85 can be set by a person skilled in the art according to actual conditions, and is not limited here. For example, the material of the third gate 85 can be molybdenum, titanium aluminum titanium, etc. It can be understood that by setting the first transistor 80 to a dual-gate structure, it is beneficial to reduce the leakage current of the first transistor 80.

[0157] It can be understood that by setting the first sub-signal line 21 and the first gate 81 or the third gate 85 in the same film layer, that is, setting the first sub-signal line 21 and the first gate 81 or the third gate 85 on the side closer to the first opening 121 in the same film layer, the via hole used to connect the first sub-signal line 21 and the second sub-signal line 22 can be made relatively shallow, which can reduce the signal loss of the first signal line 20 caused by the via hole, and the process requirements are also relatively low, which is conducive to simplifying the process.

[0158] It can also be understood that when the first sub-signal line 21 is in the same layer as the first gate 81 or the third gate 85 and a titanium-aluminum-titanium material is used, since the titanium-aluminum-titanium material is not resistant to high temperatures, it is not suitable to perform a high-temperature dehydrogenation step on the second active layer 94 after forming a via hole for filling the second source 92 and the second drain 93. The performance of the second transistor 90 is slightly worse than that of the transistor that has undergone the high-temperature dehydrogenation step. At this time, the first transistor 80 can be selected as the driving transistor in the pixel driving circuit. Generally speaking, in a pixel circuit, the transistor whose gate is connected to the scanning signal or the light-emitting control signal is a switching transistor, and the transistor other than the switching transistor in the pixel circuit is a driving transistor. The driving transistor is arranged in series on the transmission path of the first power supply signal (PVDD signal), and the gate of the driving transistor is written with a data signal. As the data signal is written, the gate potential of the driving transistor changes.

[0159] Continue to see Figure 5 ,as well as Fig.10 Optionally, the first sub-signal line 21 and the second gate 91 are located in the same film layer.

[0160] It can be understood that when the second gate 91 is located on the side of the second active layer 94 away from the base substrate 11, by arranging the first sub-signal line 21 and the second gate 91 to be located in the same film layer, the depth of the via used to connect the first sub-signal line 21 and the second sub-signal line 22 can be smaller than the depth of the via in the second transistor 90, that is, the depth of the via used to connect the first sub-signal line 21 and the second sub-signal line 22 is relatively shallow, which is beneficial to reduce the signal loss of the first signal line 20 caused by the via, and the process requirements are also relatively low, which is beneficial to simplify the process.

[0161] It can also be understood that when the first sub-signal line 21 and the second gate 91 are located in the same film layer and titanium-aluminum-titanium material is used, due to the different thermal expansion coefficients of titanium and aluminum, aluminum is prone to shrinkage and cause cracks. Therefore, compared with the transistor whose second gate 91 material is molybdenum, the performance of the second transistor 90 is slightly worse. At this time, the second transistor 90 can be selected as the driving transistor.

[0162] Fig. 27 yes Figure 3 A cross-sectional view along the BB' direction. Fig. 27 Optionally, the display panel also includes a first capacitor 110, the first capacitor 110 includes a first electrode 111 and a second electrode 112; wherein the first electrode 111 and the second electrode 112 are located on the side of the second active layer 94 away from the base substrate 11; wherein the first sub-signal line 21 and the one of the first electrode 111 and the second electrode 112 away from the base substrate 11 are located in the same film layer.

[0163] Specifically, the materials of the first electrode plate 111 and the second electrode plate 112 can be set by those skilled in the art according to actual conditions, and are not limited here. Exemplarily, the materials of the first electrode plate 111 and the second electrode plate 112 can be selected from materials such as molybdenum, titanium aluminum titanium, etc. Specifically, the specific positions of the first electrode plate 111 and the second electrode plate 112 in the display panel can be set by those skilled in the art according to actual conditions, and are not limited here. Typical examples will be described below, and will not be described here first.

[0164] It can be understood that by arranging the first signal sub-line 21 and the one of the first electrode plate 111 and the second electrode plate 112 which is far from the base substrate 11 in the same film layer, for example, Fig. 27 As shown, the first electrode plate 111 is located on the side of the second electrode plate 112 away from the base substrate 11, and the first sub-signal line 21 and the first electrode plate 111 are located in the same film layer. In this way, the via hole used to connect the first sub-signal line 21 and the second sub-signal line 22 can be shallower than the via hole in the second transistor 90, that is, the via hole used to connect the first sub-signal line 21 and the second sub-signal line 22 is relatively shallow, which is conducive to reducing the signal loss of the first signal line 20 caused by the via hole, and the process requirements are relatively low, which is conducive to simplifying the process.

[0165] Fig.28 yes Figure 3 Another cross-sectional view along the BB' direction. Fig. 27 and Fig.28 Optionally, the first transistor 80 further includes a third gate 85, the first gate 81 is located on the side of the first active layer 84 away from the substrate 11, and the third gate 85 is located on the side of the first active layer 84 facing the substrate 11; the second gate 91 is reused as the second electrode 112, and the first electrode 111 and the third gate 85 are located in the same film layer (such as Fig. 27 Alternatively, the third gate 85 is reused as the first electrode 111, and the second electrode 112 and the second gate 91 are located in the same film layer (as shown in FIG. Fig.28 shown).

[0166] It can be understood that by setting the second gate 91 to be reused as the second electrode 112, the first electrode 111 and the third gate 85 are located in the same film layer, so that the second gate 91 and the second electrode 112 can be prepared and formed by the same process, and the first electrode 111 and the third gate 85 are formed by the same preparation process, which is conducive to simplifying the preparation process of the display panel and reducing costs. Similarly, by setting the third gate 85 to be reused as the first electrode 111, the second electrode 112 and the second gate 91 are located in the same film layer, the third gate 85 and the first electrode 111 can be prepared and formed by the same process, and the second electrode 112 and the second gate 91 are formed by the same preparation process, which is conducive to simplifying the preparation process of the display panel and reducing costs.

[0167] It can also be understood that when the first capacitor 110 is used as a storage capacitor in the pixel driving circuit and is electrically connected to the driving transistor, it can be set in a direction perpendicular to the substrate 11, and the first capacitor 110 overlaps the driving transistor. Exemplarily, when the first transistor 80 is a driving transistor, the third gate 85 can be set to be reused as the first electrode 111, and the second electrode 112 and the second gate 91 are located in the same film layer; when the second transistor 90 is a driving transistor, the second gate 91 can be set to be reused as the second electrode 112, and the first electrode 111 and the third gate 85 are located in the same film layer, so that the connection between the first capacitor 110 and the driving transistor is easily realized.

[0168] Fig.29 yes Figure 3 Another cross-sectional view along the BB' direction. Fig.29 Optionally, the first transistor 80 also includes a third gate 85, the first gate 81 is located on the side of the first active layer 84 away from the substrate 11, and the third gate 85 is located on the side of the first active layer 84 toward the substrate 11; the first electrode 111 is located on the side of the second electrode 112 away from the substrate 11, wherein the first sub-signal line 21 and the first electrode 111 are located in the same film layer, the second gate 91 is reused as the second electrode 112, and the second gate 91 and the third gate 85 are located in the same film layer.

[0169] It can be understood that when the first sub-signal line 21 and the first electrode 111 are located in the same film layer and titanium-aluminum-titanium material is used, due to the different thermal expansion coefficients of titanium and aluminum, aluminum is prone to shrinkage and cause cracks. Therefore, the first sub-signal line 21 can be selected not to be in the same layer as the third gate 85. In this way, cracks in the third gate 85 can be avoided, thereby improving the performance of the first transistor 80. At this time, the first transistor 80 can also be used as a driving transistor.

[0170] Fig.30 yes Figure 3 Another cross-sectional view along the BB' direction. Figure 8 and Fig.30 Optionally, the first sub-signal line 21 includes a first layer routing 212 and a second layer routing 213 which are electrically connected to each other and stacked, and the second layer routing 213 is located on the side of the first layer routing 212 facing the substrate 11; the first layer routing 212 is connected to the second sub-signal line 22 through the first via 410 and / or the second via 420; the second layer routing 213 is connected to the first layer routing 212 through the fourth via 440 and / or the fifth via 450.

[0171] It can be understood that by setting the first sub-signal line 21 as a double-layer routing, the resistance on the first sub-signal line 21 can be fully reduced to avoid signal loss. In addition, compared with the second sub-signal line 22 being directly connected to the first sub-signal line 21 through a one-step via, the connection between the first sub-signal line 21 and the second sub-signal line 22 is achieved through two-step vias, so that the depth of each step of the via can be shallower, which is beneficial to reducing the signal loss of the first signal line 20 caused by the via, and the process requirements are relatively low, which is beneficial to simplifying the process.

[0172] Fig.31 yes Figure 3 A cross-sectional view along the BB' direction. Fig.31 Optionally, the display panel also includes a shading layer 16, which is located on the side of the second active layer 94 facing the base substrate 11; wherein the first layer wiring 212 and the second layer wiring 213 are located in any two layers of the first gate 81, the second gate 91, the third gate 85 and the film layer where the shading layer 16 is located.

[0173] Specifically, the light shielding layer 16 includes a plurality of light shielding blocks for preventing external light from irradiating the first active layer 84 of the first transistor 80 and the second active layer 94 of the second transistor 90, thereby preventing the first transistor 80 and the second transistor 90 from generating leakage current due to light.

[0174] Specifically, there are many specific implementation methods for the first layer routing 212 and the second layer routing 213, and a typical example is described below. For example, when the first layer routing 212 is located at the first gate 81 layer, the second layer routing 213 can be located at the second gate 91 layer, the third gate 85 layer, or the light shielding layer 16; when the first layer routing 212 is located at the third gate 85 layer, the second layer routing 213 can be located at the second gate 91 layer or the light shielding layer 16; when the first layer routing 212 is located at the second gate 91 layer, the second layer routing 213 can be located at the light shielding layer 16.

[0175] Fig.32 yes Figure 3 Another cross-sectional view along the BB' direction. Fig.32Optionally, the second transistor 90 includes a third source 95 and a third drain 96, the third source 95 is located between the second source 92 and the second active layer 94, and the third drain 96 is located between the second drain 93 and the second active layer 94; the third source 95 is connected to the second active layer 94 through a via, the second source 92 is connected to the third source 95 through a via, the third drain 96 is connected to the second active layer 94 through a via, and the second drain 93 is connected to the third drain 96 through a via.

[0176] Specifically, the specific materials of the third drain electrode 96 and the third source electrode 95 can be set by those skilled in the art according to actual conditions, and are not limited here. For example, the materials of the third drain electrode 96 and the third source electrode 95 can be molybdenum aluminum molybdenum, titanium aluminum titanium, etc.

[0177] It is understandable that when the first sub-signal line 21 is located on the side of the second source 92 and the second drain 93 facing the base substrate 11, and the titanium-aluminum-titanium material is used, since the titanium-aluminum-titanium material is not resistant to high temperatures, it is not suitable to perform a high-temperature dehydrogenation step on the second active layer 94 after forming the via holes for filling the second source 92 and the second drain 93. However, by adding the third source 95 and the third drain 96, the step of performing high-temperature dehydrogenation on the second active layer 94 can be placed after forming the via holes for filling the third source 95 and the third drain 96 and before forming the first sub-signal line 21. In this way, the performance of the second transistor 90 can be improved without damaging the first sub-signal line 21, which is beneficial to improving the yield of the display panel. At this time, the second transistor can be used as a driving transistor.

[0178] It can also be understood that, compared with directly connecting the second source 92 and the second drain 93 to the second active layer 94 through a one-step via, connecting the second source 92, the second drain 93 and the second active layer 94 through two-step vias can make the depth of each via shallower, and the process requirements are relatively low, which is conducive to simplifying the process.

[0179] Fig.33 yes Figure 3 Another cross-sectional view along the BB' direction. Fig.33 Optionally, the first sub-signal line 21 and at least one of the third source 95 and the third drain 96 are located in the same film layer.

[0180] Specifically, when the second sub-signal line 22 and the second source 92 (second drain 93) are located in the same film layer, by setting the first sub-signal line 21 and the third source 95 (third drain 96) to be located in the same film layer, the via for connecting the first sub-signal line 21 and the second sub-signal line 22 and the via for connecting the second source 92 (second drain 93) and the third source 95 (third drain 96) can be formed through the same process, and there is no need to prepare the via for connecting the first sub-signal line 21 and the second sub-signal line 22 through a separate process, which is beneficial to simplify the preparation process of the display panel and reduce costs.

[0181] For example, Fig.33 It is shown that the first source 82, the first drain 83, the second source 92, the second drain 93 and the second sub-signal line 22 are located in the same film layer, and the third source 95, the third drain 96 and the first sub-signal are located in the same film layer. The vias for connecting the second source 92 and the third source 95, the vias for connecting the second drain 93 and the third drain 96, and the vias for connecting the first sub-signal line 21 and the second sub-signal line 22 can be formed by the same process, so that the preparation process of the display panel is simple.

[0182] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel described in any embodiment of the present invention. Therefore, the display device has the beneficial effects of the display panel provided in the embodiment of the present invention, and the similarities can be understood by referring to the above, and will not be repeated here.

[0183] For example, Fig.34 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. Fig.34 As shown, the display device 200 provided in the embodiment of the present invention includes the display panel 100 provided in the embodiment of the present invention. The display device 200 can be exemplarily any electronic device with display function, such as a touch screen, a mobile phone, a tablet computer, a laptop computer or a television.

[0184] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: substrate substrate; A first signal line, the first signal line is located on the substrate, the first signal line comprises a first sub-signal line and a second sub-signal line which are electrically connected to each other and located in different layers, the first sub-signal line is located on a side of the second sub-signal line facing the substrate; a planarization layer, the planarization layer being located on a side of the first signal line away from the substrate; A light emitting element and a pixel spacing layer, wherein the light emitting element and the pixel spacing layer are located on a side of the planarization layer away from the base substrate; in, The planarization layer comprises a first opening, and in a direction perpendicular to the substrate, the first sub-signal line at least partially overlaps with the first opening; A first insulating layer is included between the first sub-signal line and the first opening, and the first insulating layer includes silicon oxide or silicon oxynitride.

2. The display panel according to claim 1, characterized in that: In a direction perpendicular to the base substrate, an area where the first sub-signal line overlaps with the first opening is S1, and an area where the second sub-signal line overlaps with the first opening is S2, wherein S1>S2≥0.

3. The display panel according to claim 1, characterized in that: The second signal sub-line includes a first side edge close to the first opening, and the planarization layer completely covers the first side edge.

4. The display panel according to claim 1, characterized in that: The first sub-signal line extends along a first direction. In the first direction, a length of the first sub-signal line is greater than a length of the first opening.

5. The display panel according to claim 1, characterized in that: The second sub-signal line includes a first line segment and a second line segment, at least a portion of the first line segment extends to the display area of ​​the display panel, and the first sub-signal line is located in the non-display area of ​​the display panel; wherein, The first end of the first sub-signal line is connected to one end of the first line segment through a first via hole. The first via hole is located in the non-display area and has a projection direction perpendicular to the base substrate. There is no overlap between the first via hole and the first opening.

6. The display panel according to claim 5, characterized in that: The second line segment is located in the non-display area, and the second end of the first sub-signal line is connected to one end of the second line segment through a second via hole; The second via hole is located in the non-display area, and in a direction perpendicular to the base substrate, the second via hole and the first opening do not overlap.

7. The display panel according to claim 5, characterized in that: The second sub-signal line is connected to an active layer of a transistor through a third via hole in the display area of ​​the display panel, wherein: In a direction perpendicular to the base substrate, the depth of the first via hole is H1, and the depth of the third via hole is H3, wherein H1≤1 / 2×H3.

8. The display panel according to claim 5, characterized in that: The second sub-signal line is connected to an active layer of a transistor through a third via hole in the display area of ​​the display panel, wherein: In a plane where a side of the first via hole in contact with the second sub-signal line is located, an area of ​​the first via hole is greater than an area of ​​the third via hole.

9. The display panel according to claim 1, characterized in that: The first signal sub-line includes a first layer of wiring and a second layer of wiring that are electrically connected to each other and stacked; In a direction perpendicular to the substrate, the first layer of wiring, the second layer of wiring, and the first opening at least partially overlap.

10. The display panel according to claim 1, characterized in that: The second sub-signal line includes a third-layer routing and a fourth-layer routing electrically connected to each other, the fourth-layer routing is located on a side of the planarization layer away from the third-layer routing, and the third-layer routing is electrically connected to the fourth-layer routing through a via; In a direction perpendicular to the substrate, the third layer wiring and the fourth layer wiring do not overlap with the first opening.

11. The display panel according to claim 1, characterized in that: In a direction perpendicular to the base substrate, a second insulating layer stacked with the first insulating layer is included between the first sub-signal line and the first opening, the second insulating layer includes silicon nitride, and the first insulating layer is located on a side of the second insulating layer facing the first sub-signal line.

12. The display panel according to claim 11, characterized in that: The thickness of the first insulating layer is greater than the thickness of the second insulating layer.

13. The display panel according to claim 1, characterized in that: A hydrogen content of the first insulating layer on a side facing the first signal sub-line is smaller than a hydrogen content of the first insulating layer on a side away from the first signal sub-line.

14. The display panel according to claim 1, characterized in that: The display panel further includes an encapsulation layer, the encapsulation layer including a first inorganic layer, a second inorganic layer, and an organic layer located between the first inorganic layer and the second inorganic layer, the second inorganic layer being located on a side of the first inorganic layer away from the base substrate; wherein, The encapsulation layer fills the first opening, and the first inorganic layer covers the surface of the first opening facing the encapsulation layer; At least one insulating layer is included between the first inorganic layer and the first sub-signal line.

15. The display panel according to claim 1, characterized in that: The display panel further includes a second signal line, wherein the second signal line and the second sub-signal line are located in the same film layer, and in a direction perpendicular to the base substrate, the first sub-signal line and the second signal line at least partially overlap.

16. The display panel according to claim 15, characterized in that: In a direction perpendicular to the base substrate, the second signal line does not overlap with the first opening.

17. The display panel according to claim 16, characterized in that: The display panel includes a display area and a non-display area. The first opening is located in the non-display area. The second signal line is located at a side of the first opening away from the display area.

18. The display panel according to claim 16, characterized in that: The display panel includes a display area and a non-display area, and the first opening is located in the non-display area; The light emitting element comprises a cathode layer, and in a direction perpendicular to the substrate, the cathode layer does not overlap with the first opening; The display panel further comprises a connecting electrode layer, and the second signal line is electrically connected to the cathode layer through the connecting electrode layer; The connecting electrode layer is connected to the second signal line at a side of the first opening away from the display area, and is connected to the cathode layer at a side of the first opening close to the display area.

19. The display panel according to claim 16, characterized in that: The display panel comprises a display area and a non-display area, the first opening is located in the non-display area, the second signal line comprises a third sub-signal line and a fourth sub-signal line, the third sub-signal line is located at a side of the first opening close to the display area, and the fourth sub-signal line is located at a side of the first opening far from the display area; The display panel further comprises a connection line, and the third sub-signal line and the fourth sub-signal line are electrically connected through the connection line; The connecting line and the first sub-signal line are arranged in the same layer, and in a direction perpendicular to the base substrate, the connecting line at least partially overlaps with the first opening.

20. The display panel according to claim 19, characterized in that: The light emitting element comprises a cathode layer, and in a direction perpendicular to the substrate, the cathode layer does not overlap with the first opening; The display panel further includes a connecting electrode layer, and the third sub-signal line is electrically connected to the cathode layer through the connecting electrode layer.

21. The display panel according to claim 15, characterized in that: In a direction perpendicular to the substrate, the second signal line at least partially overlaps with the first opening, and any side edge of the second signal line does not overlap with the first opening.

22. The display panel according to claim 21, characterized in that: In a direction perpendicular to the base substrate, an orthographic projection of the first opening on the base substrate is located within an orthographic projection of the second signal line on the base substrate.

23. The display panel according to claim 21, characterized in that: The display panel includes a display area and a non-display area, and the first opening is located in the non-display area; The light emitting element comprises a cathode layer, and in a direction perpendicular to the substrate, the cathode layer does not overlap with the first opening; The display panel further comprises a connecting electrode layer, and the second signal line is electrically connected to the cathode layer through the connecting electrode layer; The connecting electrode layer is connected to the second signal line at the location of the first opening, and is connected to the cathode layer at a side of the first opening close to the display area.

24. The display panel according to claim 23, characterized in that: The display panel further comprises a second opening located at a side of the first opening away from the display area; In a direction perpendicular to the substrate, the second signal line and the second opening do not overlap; or, In a direction perpendicular to the substrate, the second signal line at least partially overlaps with the second opening, and any side edge of the second signal line does not overlap with the second opening.

25. The display panel according to claim 24, characterized in that: In a direction perpendicular to the substrate, the second signal line at least partially overlaps with the second opening, and any side edge of the second signal line does not overlap with the second opening; The connection electrode layer is also connected to the second signal line at the location of the second opening.

26. The display panel according to claim 24, characterized in that: A first retaining wall is disposed between the first opening and the second opening, and the first retaining wall is disposed at the same layer as the pixel spacing layer.

27. The display panel according to claim 24, characterized in that: The display panel further includes a third opening located on a side of the second opening away from the display area, and a width of the third opening in a direction from the non-display area to the display area is greater than a width of the second opening and a width of the first opening.

28. The display panel according to claim 27, characterized in that: In a direction perpendicular to the substrate, the second signal line and the third opening do not overlap; or In a direction perpendicular to the substrate, the second signal line at least partially overlaps with the third opening, and any side edge of the second signal line does not overlap with the third opening.

29. The display panel according to claim 27, characterized in that: A second retaining wall is disposed between the second opening and the third opening, and at least a portion of the second retaining wall is disposed in the same layer as the pixel spacing layer.

30. The display panel according to claim 29, characterized in that: In a direction perpendicular to the base substrate, a height of the second barrier wall is greater than a height of the pixel spacing layer.

31. The display panel according to claim 15, characterized in that: The first signal line provides a first power signal for the pixel circuit of the display panel, and the second signal line provides a second power signal for the light-emitting element of the display panel. One of the first power signal and the second power signal is a high level signal, and the other is a low level signal.

32. The display panel according to claim 1, characterized in that: The display panel includes a first transistor and a second transistor; The first transistor includes a first gate, a first source, a first drain and a first active layer; The second transistor includes a second gate, a second source, a second drain and a second active layer; wherein, The first active layer includes an oxide semiconductor, the second active layer includes silicon, and the first active layer is located on a side of the second active layer away from the substrate; The second sub-signal line is located in a same layer as at least one of the first source, the first drain, the second source, and the second drain.

33. The display panel according to claim 32, characterized in that: The first gate is located on a side of the second gate away from the substrate.

34. The display panel according to claim 32, characterized in that: The first sub-signal line is located on a side of the first active layer away from the base substrate.

35. The display panel according to claim 32, characterized in that: The first sub-signal line and the first gate are located in the same film layer.

36. The display panel according to claim 32, characterized in that: The first transistor further includes a third gate, the first gate is located on a side of the first active layer away from the substrate, and the third gate is located on a side of the first active layer facing the substrate; wherein, The first gate and the third gate are both located on a side of the second gate away from the base substrate, and the first sub-signal line and the first gate or the third gate are located in the same film layer.

37. The display panel according to claim 32, characterized in that: The first sub-signal line and the second gate are located in the same film layer.

38. The display panel according to claim 32, characterized in that: The display panel further includes a first capacitor, which includes a first electrode plate and a second electrode plate; wherein, The first electrode plate and the second electrode plate are located on a side of the second active layer away from the base substrate; wherein, The first signal sub-line and one of the first electrode plate and the second electrode plate that is away from the base substrate are located in the same film layer.

39. The display panel according to claim 38, characterized in that: The first transistor further includes a third gate, the first gate is located on a side of the first active layer away from the substrate, and the third gate is located on a side of the first active layer facing the substrate; The second gate is reused as the second electrode plate, and the first electrode plate and the third gate are located in the same film layer; or The third grid is reused as the first electrode plate, and the second electrode plate and the second grid are located in the same film layer.

40. The display panel according to claim 32, characterized in that: The first sub-signal line includes a first layer of routing and a second layer of routing that are electrically connected to each other and stacked, and the second layer of routing is located on a side of the first layer of routing that faces the substrate; The first layer routing line is connected to the second sub-signal line through a first via hole and / or a second via hole; The second layer routing is connected to the first layer routing through a fourth via and / or a fifth via.

41. The display panel according to claim 40, characterized in that: The display panel further includes a light shielding layer, and the light shielding layer is located on a side of the second active layer facing the base substrate; wherein, The first layer wiring and the second layer wiring are located in any two layers of the film layer where the first gate, the second gate, the third gate and the light shielding layer are located.

42. The display panel according to claim 32, characterized in that: The second transistor comprises a third source and a third drain, the third source is located between the second source and the second active layer, and the third drain is located between the second drain and the second active layer; The third source is connected to the second active layer through a via hole, the second source is connected to the third source through a via hole, the third drain is connected to the second active layer through a via hole, and the second drain is connected to the third drain through a via hole.

43. The display panel according to claim 42, characterized in that: The first signal sub-line and at least one of the third source and the third drain are located in the same film layer.

44. A display device, characterized in that: A display panel comprising any one of claims 1-43.

Images