Ohmic contact structure and semiconductor device

Abstract

The present disclosure provides an ohmic contact structure and a semiconductor device. The ohmic contact structure includes: a first contact structure, arranged along the gate width direction of the transistor, located at the center of the upper surface of the active region in the gate width direction, and having a first length; a second contact structure, arranged along the gate width direction, located on both sides of the first contact structure along the gate width direction, aligned with the center of the first contact structure in the gate width direction, and having a second length greater than the first length; a third contact structure, arranged along the gate width direction, located on the side of the second contact structure away from the first contact structure along the gate width direction, aligned with the center of the first contact structure in the gate width direction, and having a third length greater than the second length. The ohmic contact structure provided by the embodiment of the present disclosure can safely implement the ESD function.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and in particular to an ohmic contact structure and a semiconductor device for ESD. Background Art

[0002] In the related art, due to the limitation of the manufacturing process, the ohmic contact structure connected to the same metal area is usually arranged discontinuously (such as Figure 1 As the device size decreases, the size of the ohmic contact structure also decreases accordingly, and the resistance increases accordingly, affecting the performance of the device. The slot contact structure has a larger contact area and smaller resistance (as shown in Figure 2). Figure 2 However, when the slot-type contact structure faces an electrostatic discharge (ESD) scenario, it will be thermally burned due to poor heat dissipation of the long slot contact. Therefore, an ohmic contact structure that can better cope with the electrostatic discharge scenario is needed.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The embodiments of the present disclosure provide an ohmic contact structure and a semiconductor device to which the ohmic contact structure can be applied, which are used to at least to some extent overcome the problem of thermal burnout of the related contact structure in an electrostatic discharge scenario due to limitations and defects of the related technology.

[0005] According to a first aspect of the present disclosure, an ohmic contact structure is provided, comprising: a first contact structure, arranged along a gate width direction, located at the center of an upper surface of an active region along the gate width direction, and having a first length; a second contact structure, arranged along the gate width direction, located at both sides of the first contact structure along the gate width direction, aligned with the center of the first contact structure in the gate width direction, and having a second length greater than the first length; a third contact structure, arranged along the gate width direction, located at a side of the second contact structure away from the first contact structure along the gate width direction, aligned with the center of the first contact structure in the gate width direction, and having a third length greater than the second length.

[0006] In an exemplary embodiment of the present disclosure, the first length is 1 micrometer, the second length is 1.5 to 3 micrometers, and the third length is 2 to 5 micrometers.

[0007] In an exemplary embodiment of the present disclosure, the widths of the first contact structure, the second contact structure, and the third contact structure in the channel direction are the same.

[0008] In an exemplary embodiment of the present disclosure, the first contact structure, the second contact structure, and the third contact structure are all disposed at the source of the transistor or at the drain of the transistor.

[0009] In an exemplary embodiment of the present disclosure, the first contact structure, the second contact structure, and the third contact structure, which are all disposed at the source of the transistor or are all disposed at the drain of the transistor, are all electrically connected to the same metal structure.

[0010] In an exemplary embodiment of the present disclosure, the first contact structure, the second contact structure, and the third contact structure are all disposed at a source and a drain of a transistor.

[0011] In an exemplary embodiment of the present disclosure, the first contact structure, the second contact structure, and the third contact structure located at the source and the drain of the transistor are distributed axially symmetrically with respect to the gate of the transistor.

[0012] In an exemplary embodiment of the present disclosure, the first contact structure, the second contact structure, and the third contact structure located at the source and drain of the transistor are asymmetrically distributed relative to the gate of the transistor, and the two first contact structures respectively located at the source and drain of the transistor are flush in the channel direction, the two second contact structures respectively located at the source and drain of the transistor are flush in the channel direction, and the two third contact structures respectively located at the source and drain of the transistor are flush in the channel direction.

[0013] In an exemplary embodiment of the present disclosure, the first contact structure, the second contact structure, and the third contact structure located at the source of the transistor have the same first width in the channel direction, and the first contact structure, the second contact structure, and the third contact structure located at the drain of the transistor have the same second width in the channel direction, and the second width is greater than the first width.

[0014] In an exemplary embodiment of the present disclosure, the first contact structure, the second contact structure, and the third contact structure located at the source of the transistor are all electrically connected to the first metal structure, and the first contact structure, the second contact structure, and the third contact structure located at the drain of the transistor are all electrically connected to the second metal structure.

[0015] In an exemplary embodiment of the present disclosure, in a channel direction, the second metal structure has a greater width than the first metal structure.

[0016] According to another aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a gate; a source, located on one side of the gate, having a first groove array, the first groove array having at least three grooves, and the shapes and areas of the grooves are not completely the same; a drain, located on the other side of the gate, having a second groove array, the second groove array having at least three grooves, and the shapes and areas of the grooves are not completely the same.

[0017] In an exemplary embodiment of the present disclosure, it also includes a first doping region, wherein the first groove array is located in the first doping region; and a second doping region, wherein the second groove array is located in the second doping region, and the concentration of the second doping region is greater than or equal to the concentration of the first doping region.

[0018] In an exemplary embodiment of the present disclosure, the grooves are filled with a conductive medium, which includes metal silicide, metal oxide and metal; the conductive medium of the first groove array is electrically connected to the first metal structure, and the conductive medium of the second groove array is electrically connected to the second metal structure.

[0019] In an exemplary embodiment of the present disclosure, the grooves in the second groove array are centrally aligned along the gate width direction, and the areas of the grooves in the second groove array increase sequentially from the edge of the semiconductor device to the center of the semiconductor device.

[0020] In an exemplary embodiment of the present disclosure, the multiple grooves in the second groove array are all rectangular, and the widths of the multiple grooves along the channel direction are the same. From the edge of the semiconductor device to the center of the semiconductor device, the lengths of the grooves in the second groove array along the gate width direction decrease sequentially.

[0021] In an exemplary embodiment of the present disclosure, the number of grooves in the second groove array is equal to that in the first groove array, and the nth groove in the second groove array is aligned with the center of the nth groove in the first groove array along the channel direction, and n is the ordinal number of the groove calculated from the edge of the semiconductor device.

[0022] In an exemplary embodiment of the present disclosure, the number of grooves in the first groove array and the second groove array is 5, and the grooves in the first groove array and the second groove array are symmetrically distributed along the center line of the semiconductor device in the gate width direction.

[0023] The ohmic contact structure provided in the embodiment of the present disclosure can increase the resistance of the ohmic structure in the center of the device and reduce the resistance of the ohmic structure at the edge of the device by arranging multiple ohmic contact structures in sequence from short to long along the center of the device to the edge of the device, thereby directing a large current to the edge of the device when an electrostatic discharge current flows through, reducing the heat generated in the center of the device due to the flow of large current, and preventing the ohmic contact structure located in the center of the device from being burned by the heat generated by the large current.

[0024] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0026] Figure 1 It is a schematic diagram of a point contact structure in the related art.

[0027] Figure 2 It is a schematic diagram of a groove contact structure in the related art.

[0028] Figure 3 Schematic diagram of the ohmic contact structure in the first embodiment of the present disclosure.

[0029] Figure 4A and Figure 4B Schematic diagram of the thermal effect of the ohmic contact structure in the embodiment of the present disclosure.

[0030] Figure 5 Schematic diagram of the ohmic contact structure in the second embodiment of the present disclosure.

[0031] Figure 6 Schematic diagram of the ohmic contact structure in the third embodiment of the present disclosure.

[0032] Figure 7 Schematic diagram of the ohmic contact structure in the fourth embodiment of the present disclosure.

[0033] Figure 8 Schematic diagram of the ohmic contact structure in the fifth embodiment of the present disclosure.

[0034] Fig. 9 Schematic diagram of the ohmic contact structure in the sixth embodiment of the present disclosure.

[0035] Fig.10 Schematic diagram of the ohmic contact structure in the seventh embodiment of the present disclosure.

[0036] Fig.11 is a schematic diagram of a semiconductor device in one embodiment of the present disclosure.

[0037] Fig.12 yes Fig.11 A top view of the semiconductor device shown.

[0038] Fig.13 yes Fig.11 Schematic diagram of the connection of the semiconductor device shown. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0040] In addition, the drawings are only schematic illustrations of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0041] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0042] Figure 3 It is a schematic structural diagram of the ohmic contact structure in the first embodiment of the present disclosure.

[0043] refer to Figure 3 , the ohmic contact structure 100 may include:

[0044] The first contact structure 11 is arranged along the gate width direction of the transistor, is located at the center of the upper surface of the active region in the gate width direction, and has a first length L1;

[0045] The second contact structure 12 is arranged along the gate width direction, is located on both sides of the first contact structure 11 along the gate width direction, is aligned with the center of the first contact structure 11 in the gate width direction, and has a second length L2 greater than the first length L1;

[0046] The third contact structure 13 is arranged along the gate width direction, located on a side of the second contact structure 12 away from the first contact structure 11 along the gate width direction, aligned with the center of the first contact structure 11 in the gate width direction, and has a third length L3 greater than the second length L2.

[0047] The contact structures in the embodiments of the present disclosure all refer to metal-semiconductor contact structures.

[0048] The applicant discovered through ESD / TLP testing that when the existing ohmic contact structure is burned in an electrostatic discharge scenario, the burn point is often at the center of the width of the semiconductor device.

[0049] Therefore, in the embodiment of the present disclosure, a plurality of ohmic contact structures are arranged in sequence from short to long along the center of the device to the edge of the device, the resistance of the ohmic structure in the center of the device is increased by reducing the length, and the resistance of the ohmic structure at the edge of the device is reduced by increasing the length. The length of the ohmic structure is adjusted from short to long according to the distance from the center of the device, so that when the electrostatic current flows through the ohmic contact structure in a direction perpendicular to the gate width direction, the large current is introduced as much as possible into the ohmic contact structure farther from the center of the device, thereby reducing the electrothermal temperature of the ohmic contact structure in the center of the device and avoiding burning of the ohmic contact structure.

[0050] Figure 4A and Figure 4B It is a schematic diagram of the thermal effect of the ohmic contact structure provided by the embodiment of the present disclosure.

[0051] Figure 4A This is a schematic diagram of the temperature distribution of the slot-type ohmic contact structure in the related art. When a large current flows through, the ohmic contact structure located in the center of the device produces a thermal effect, and the temperature rises sharply until it burns out, because the heat dissipation environment in the center of the device is worse than that at the edge of the device.

[0052] Figure 4B : is a schematic diagram of the temperature distribution of the ohmic contact structure provided by the embodiment of the present disclosure. When a large current flows through, since the ohmic contact structure at the center of the device is short in length, small in area, and large in resistance, and the ohmic contact structure at the edge of the device is long in length, large in area, and small in resistance, the large current is introduced into the ohmic contact structure far away from the center of the device, and the current, electrothermal effect, and temperature of the ohmic structure located at the center of the device are reduced. Furthermore, by gradually adjusting the length of the ohmic contact structure, the heat balance of all ohmic contact structures is achieved, and the ohmic contact structure is prevented from being burned at a certain point, and the ESD function can be better realized.

[0053] Figure 5 Schematic diagram of the ohmic contact structure in the second embodiment of the present disclosure.

[0054] refer to Figure 5, the first contact structure 11, the second contact structure 12, and the third contact structure 13, which are centrally aligned in the gate width direction, are connected to the same metal area. In terms of the setting position, the first contact structure 11, the second contact structure 12, and the third contact structure 13 are simultaneously set at the source and the drain of the transistor, and the first contact structure 11 respectively located at the source and the drain of the transistor is flush in the channel direction, the second contact structure 12 respectively located at the source and the drain of the transistor is flush in the channel direction, and the third contact structure 13 respectively located at the source and the drain of the transistor is flush in the channel direction, each contact structure is close to the gate, and the first contact structure 11, the second contact structure 12, and the third contact structure 13 located at the drain are at a distance M1 from the gate in the channel direction, and the first contact structure 11, the second contact structure 12, and the third contact structure 13 located at the source are at a distance M2 from the gate in the channel direction, and M1 is greater than M2, that is, the first contact structure, the second contact structure, and the third contact structure respectively located at the source and the drain of the transistor are asymmetrically distributed relative to the gate of the transistor.

[0055] The reason why M1 is greater than M2 is to provide enough heat dissipation space for the drain and improve the heat dissipation capacity of the drain.

[0056] In other embodiments, the first contact structure 11, the second contact structure 12, and the third contact structure 13 respectively located at the source and the drain of the transistor may also be symmetrically distributed relative to the gate of the transistor, that is, M1=M2, which is not particularly limited in the present disclosure.

[0057] Figure 6 Schematic diagram of the ohmic contact structure in the third embodiment of the present disclosure. Figure 6 In other embodiments of the present disclosure, the first contact structure 11, the second contact structure 12, and the third contact structure 13 may also be provided only at the drain of the transistor or only at the source of the transistor. In the case where each contact structure is provided only at one side of the transistor gate, it is preferred to provide only at the drain of the transistor to better achieve the ESD effect.

[0058] In terms of monomer size, the first contact structure 11, the second contact structure 12, and the third contact structure 13 located on the same side of the transistor gate have the same width in the channel direction. In one embodiment, the first length L1 is 1 micron, the second length L2 is 1.5 to 3 microns, and the third length L3 is 2 to 5 microns. When determining the specific values ​​of the second length L2 and the third length L3, it is still necessary to keep the third length L3 greater than the second length L2. Those skilled in the art can set the length of each contact structure according to actual process standards and requirements, and the present disclosure does not make any special restrictions on this.

[0059] Figure 7 Schematic diagram of the ohmic contact structure in the fourth embodiment of the present disclosure.

[0060] refer to Figure 7 In one embodiment of the present disclosure, the first contact structure 11, the second contact structure 12, and the third contact structure 13 located at the source of the transistor have the same first width W1 in the channel direction, and the first contact structure 11, the second contact structure 12, and the third contact structure 13 located at the drain of the transistor have the same second width W2 in the channel direction, and the second width W2 is greater than the first width W1. Figure 7 In the illustrated embodiment, the widths of the metal structures of the source and drain in the channel direction may also be equal.

[0061] Figure 8 Schematic diagram of the ohmic contact structure in the fifth embodiment of the present disclosure.

[0062] refer to Figure 8 In another embodiment of the present disclosure, the first contact structure 11, the second contact structure 12, and the third contact structure 13 located at the source of the transistor are all electrically connected to the first metal structure 81, and the first contact structure 11, the second contact structure 12, and the third contact structure 13 located at the drain of the transistor are all electrically connected to the second metal structure 82, and the width of the first metal structure 81 is smaller than the width of the second metal structure 82. Figure 8 In the embodiment shown, the widths of the contact structures at the source and drain in the channel direction may be the same or may be different. Figure 7 As shown, the second width W2 of each contact structure located at the drain is greater than the first width W1 of each contact structure located at the source.

[0063] In terms of quantity, it is easy to understand that the number of contact structures is proportional to the width of the device. When the device size is large, it can be as follows Fig. 9 As shown, the number of the first contact structure 11, the second contact structure 12, and the third contact structure 13 is increased; or as Fig.10 As shown, a fourth contact structure 14 having a length longer than the third contact structure 13 is added, and so on.

[0064] To summarize, the ohmic contact structure provided in the embodiment of the present disclosure can increase the resistance of the ohmic structure in the center of the device and reduce the resistance of the ohmic structure at the edge of the device by arranging multiple ohmic contact structures in sequence from short to long along the center of the device to the edge of the device, thereby directing a large current to the edge of the device when an electrostatic discharge current flows through, reducing the heat generated by the large current flowing through the center of the device, and preventing the ohmic contact structure located in the center of the device from being burned by the heat generated by the large current.

[0065] Fig.11 is a schematic diagram of a semiconductor device provided in one embodiment of the present disclosure.

[0066] refer to Fig.11 , the semiconductor device 1100 comprises:

[0067] Gate 111;

[0068] The source electrode 112 is located at one side of the gate electrode 111 and has a first groove array 1121. The first groove array has at least three grooves, and the shapes and areas of the grooves are not completely the same.

[0069] The drain 113 , located at the other side of the gate 111 , has a second groove array 1131 . The second groove array has at least three grooves, and the shapes and areas of the grooves are not completely the same.

[0070] The first groove array 1121 is located in the first doping region 1122 , the second groove array 1131 is located in the second doping region 1132 , and the concentration of the second doping region 1132 is greater than or equal to the concentration of the first doping region 1122 .

[0071] Fig.12 yes Fig.11 A top view of the semiconductor device shown.

[0072] refer to Fig.12 In the semiconductor device 1100, the grooves in the second groove array 1131 can be aligned along the center of the gate width, and the area of ​​each groove increases from the edge to the center of the semiconductor device 1100. The groove area can be increased as follows: Fig.12 As shown in the figure, the multiple grooves are all rectangular and have the same width along the channel direction. The length of each groove along the gate width direction decreases sequentially from the edge to the center of the semiconductor device 1100. Other methods may also be used (such as setting the groove to be circular and increasing the number of grooves). The present disclosure does not specifically limit the shape of the groove.

[0073] refer to Fig.12 In another embodiment, the shape and area of ​​each groove of the first groove array 1121 can be the same, for example, groove 11, groove 12, and groove 13 are rectangles with the same shape and area. According to the size of the current flowing through, the shape and area of ​​grooves 12 and 13 can be set to be the same as groove 11, or the shape and area of ​​grooves 11 and 13 can be set to be the same as groove 12, and the shape and area of ​​grooves 11 and 12 can also be set to be the same as groove 13. The rectangular shape of the above grooves 11, 12, and 13 can be rectangular, elliptical, circular, or other shapes, which are not limited here. The specific areas of the above grooves 11, 12, and 13 are not specifically limited here, considering the different manufacturing processes and the different sizes of the current flowing through.

[0074] In addition, continue to refer to Fig.12, the number of grooves in the second groove array 1131 and the first groove array 1121 can be set to be equal, and the nth groove in the second groove array 1131 is aligned with the nth groove in the first groove array 1121 along the channel direction, where n is the ordinal number of the grooves calculated from the edge of the semiconductor device. It can be understood that the number of grooves in the first groove array 1121 and the second groove array 1131 can also be set to be unequal.

[0075] exist Fig.12 In the illustrated embodiment, the number of grooves in the first groove array 1121 and the second groove array 1131 is 5, and the grooves in the first groove array 1121 and the second groove array 1131 are symmetrically distributed along the center line of the semiconductor device in the gate width direction. In other embodiments of the present disclosure, the number of grooves in each groove array can be greater, and the present disclosure does not specifically limit this.

[0076] Fig.11 or Fig.12 The semiconductor device shown can be used to build Figure 3 The ohmic contact structure shown.

[0077] Fig.13 It is a schematic diagram of the connection between semiconductor devices and ohmic structures.

[0078] refer to Fig.13 When used as the bottom layer of the ohmic contact structure 100, the grooves in the first groove array and the second groove array are filled with a conductive medium 1123 or 1133 including metal silicide, metal oxide and metal, and the conductive medium 1123 of the first groove array is electrically connected to the first metal structure 131 (through the ohmic contact structure), and the conductive medium 1133 of the second groove array is electrically connected to the second metal structure 132 (through the ohmic contact structure). The shapes and arrangements of the first metal structure 131, the second metal structure 132, and the grooves are as follows: Figure 3 to Figure 12 As shown in any item, the description is as above, and the present disclosure will not be repeated here.

[0079] To summarize, the semiconductor device provided by the embodiment of the present disclosure has a contact structure located at the center of the device that has a smaller area and a larger resistance than the contact structure located at the edge of the device. Therefore, when ESD current is generated, the ESD current can be distributed in a state where the edge is greater than the center, thereby reducing the electrothermal effect in the center of the semiconductor device, avoiding excessive ESD current from burning the contact structure in the center of the semiconductor device, and having excellent ESD performance.

[0080] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. An ohmic contact structure, characterized in that: include: A first contact structure is arranged along the gate width direction of the transistor, is located at the center of the upper surface of the active region in the gate width direction, and has a first length; A second contact structure is arranged along the gate width direction, is located on both sides of the first contact structure along the gate width direction, is centrally aligned with the first contact structure in the gate width direction, and has a second length greater than the first length; The third contact structure is arranged along the gate width direction, located on a side of the second contact structure away from the first contact structure along the gate width direction, aligned with the center of the first contact structure in the gate width direction, and has a third length greater than the second length.

2. The ohmic contact structure according to claim 1, characterized in that: The first length is 1 micrometer, the second length is 1.5 to 3 micrometers, and the third length is 2 to 5 micrometers.

3. The ohmic contact structure according to claim 1, wherein: The first contact structure, the second contact structure, and the third contact structure have the same width in the channel direction.

4. The ohmic contact structure according to claim 3, characterized in that: The first contact structure, the second contact structure, and the third contact structure are all disposed at the source of the transistor or at the drain of the transistor.

5. The ohmic contact structure according to claim 4, characterized in that: The first contact structure, the second contact structure, and the third contact structure, which are all disposed at the source of the transistor or at the drain of the transistor, are all electrically connected to the same metal structure.

6. The ohmic contact structure according to claim 3, characterized in that: The first contact structure, the second contact structure and the third contact structure are all arranged at the source and the drain of the transistor.

7. The ohmic contact structure according to claim 6, characterized in that: The first contact structure, the second contact structure, and the third contact structure, which are respectively located at the source and the drain of the transistor, are axially symmetrically distributed with respect to the gate of the transistor.

8. The ohmic contact structure according to claim 6, characterized in that: The first contact structure, the second contact structure, and the third contact structure, which are respectively located at the source and drain of the transistor, are asymmetrically distributed relative to the gate of the transistor, and the two first contact structures, which are respectively located at the source and drain of the transistor, are flush in the channel direction, the two second contact structures, which are respectively located at the source and drain of the transistor, are flush in the channel direction, and the two third contact structures, which are respectively located at the source and drain of the transistor, are flush in the channel direction.

9. The ohmic contact structure according to claim 6, characterized in that: The first contact structure, the second contact structure, and the third contact structure located at the source of the transistor have the same first width in the channel direction, and the first contact structure, the second contact structure, and the third contact structure located at the drain of the transistor have the same second width in the channel direction, and the second width is greater than the first width.

10. The ohmic contact structure according to claim 6, characterized in that: The first contact structure, the second contact structure and the third contact structure located at the source of the transistor are all electrically connected to the first metal structure, and the first contact structure, the second contact structure and the third contact structure located at the drain of the transistor are all electrically connected to the second metal structure.

11. The ohmic contact structure according to claim 10, characterized in that: In the channel direction, the width of the second metal structure is greater than the width of the first metal structure.

12. A semiconductor device, characterized in that: include: Gate; A source electrode, located at one side of the gate electrode, having a first groove array, wherein the first groove array has at least three grooves, and the shapes and areas of the grooves are not completely the same; A drain electrode, located at the other side of the gate, having a second groove array, wherein the second groove array has at least three grooves, and the shapes and areas of the grooves are not completely the same; The grooves in the second groove array are aligned along the center of the gate width direction, and the area of ​​each groove in the second groove array decreases sequentially from the edge of the semiconductor device to the center of the semiconductor device; The grooves are filled with a conductive medium, the conductive medium of the first groove array is electrically connected to a first metal structure, and the conductive medium of the second groove array is electrically connected to a second metal structure.

13. The semiconductor device according to claim 12, wherein: Also includes: a first doped region, wherein the first groove array is located in the first doped region; The second doping region, the second groove array is located in the second doping region, and the concentration of the second doping region is greater than or equal to the concentration of the first doping region.

14. The semiconductor device according to claim 12, wherein: The conductive medium includes metal silicide, metal oxide and metal.

15. The semiconductor device according to claim 12, wherein: The multiple grooves in the second groove array are all rectangular and have the same width along the channel direction. From the edge of the semiconductor device to the center of the semiconductor device, the length of each groove in the second groove array along the gate width direction decreases sequentially.

16. The semiconductor device according to claim 12, wherein: The second groove array and the first groove array have the same number of grooves, and the nth groove in the second groove array is aligned with the nth groove in the first groove array along the channel direction, and n is the ordinal number of the groove calculated from the edge of the semiconductor device.

17. The semiconductor device according to claim 12, wherein: The number of grooves in the first groove array and the second groove array is 5, and the grooves in the first groove array and the second groove array are symmetrically distributed along the center line of the semiconductor device in the gate width direction.

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