Instruction processing device and instruction processing method

Abstract

An instruction processing device and an instruction processing method are disclosed. The instruction processing device includes: an instruction boundary prediction unit, which is used to obtain an instruction packet of the variable-length instruction set and add instruction prediction information to each instruction meta-field in the instruction packet; an instruction pipeline structure, wherein the instruction fetch unit of the instruction pipeline structure includes an instruction boundary determination unit, and the instruction boundary determination unit is used to determine one or more instructions according to the instruction prediction information. Compared with the prior art, the advantage of the embodiment of the present invention is that before entering the instruction pipeline structure, the instruction prediction information is added to each instruction meta-field, so that the instruction fetch unit can determine the instruction boundary information according to the instruction prediction information, thereby determining the instruction boundary information more quickly, avoiding spending more logical length to determine the instruction boundary information.

Description

Technical Field

[0001] The present invention relates to the field of processor manufacturing, and more specifically, to an instruction processing device and an instruction processing method. Background Art

[0002] Improving processor architecture is a very difficult task. Researchers put a lot of effort into this, hoping to make progress in even the smallest aspects. In the design of high-performance processors, reducing pipeline stages has become a consensus for improving processor architecture.

[0003] In the pipeline structure, the main task of the instruction fetch stage is to obtain a fixed-length instruction packet from the instruction cache or external bus according to the instruction packet address. After obtaining the instruction packet, the position of the valid instruction in the instruction packet is determined according to the value of the instruction PC. Then, all the instruction meta-fields in the valid instruction are decoded one by one to determine whether each instruction meta-field is an instruction header. Then, according to the value of the PC and the instruction header information of each instruction meta-field, the boundary of each instruction is confirmed from front to back, and the instruction packet is split to obtain the correct instruction.

[0004] At the instruction fetch level, the following two functions are usually included:

[0005] 1) Encapsulate the instruction information and store it in the instruction cache;

[0006] 2) It is usually necessary to obtain partial decoding information of the instruction faster, for example, whether the instruction is a branch instruction, or a function return instruction, etc. This information can be used to start changing the execution flow of the program, such as using branch prediction information to jump, and using the function return address predicted by the function return predictor to start fetching a new instruction stream.

[0007] In the traditional method, the instruction boundary information is decoded after the instruction packet is obtained, which is not conducive to the implementation of the above two functions in the instruction fetch stage at the same time. For high-performance processors, since the timing requirements are not met, additional pipeline stages will be added, which will greatly reduce the performance of the processor. For example, for branch instructions, it takes one cycle later to obtain the information on whether to jump. Summary of the invention

[0008] In view of this, the present invention proposes an instruction processing device and an instruction processing method to solve the above problems.

[0009] To achieve this object, according to a first aspect of the present invention, the present invention provides an instruction processing device for processing instructions under a variable-length instruction set, comprising:

[0010] An instruction boundary prediction unit, used for acquiring an instruction packet of the variable-length instruction set and adding instruction prediction information to each instruction element field in the instruction packet;

[0011] An instruction pipeline structure, wherein an instruction fetch unit of the instruction pipeline structure comprises an instruction boundary determination unit, and the instruction boundary determination unit is used to determine one or more instructions according to the instruction prediction information.

[0012] In some embodiments, the instruction boundary prediction unit obtains instruction prediction information of each instruction metafield by the following steps:

[0013] Determining all possible settings of a first instruction element field in the instruction packet under the variable-length instruction set;

[0014] The instruction prediction information of the current instruction metafield is determined based on the instruction prediction information and decoding information of the previous instruction metafield.

[0015] In some embodiments, instruction prediction information of the current instruction metafield is determined based on instruction prediction information and decoding information of the previous x instruction metafields, where the value of x is related to the maximum instruction encoding length in the variable-length instruction set and the length of the instruction metafield.

[0016] In some embodiments, the instruction boundary determination unit determines the instruction meta-field corresponding to the program pointer, and obtains instruction prediction information of the instruction meta-field corresponding to the program pointer based on this. If the instruction prediction information of the instruction meta-field corresponding to the program pointer includes an entry representing an instruction header, the entry is used as the instruction boundary information, and one or more instructions are obtained based on this.

[0017] In some embodiments, if the instruction prediction information of the instruction metafield corresponding to the program pointer does not include an entry indicating an instruction header, the instruction boundary calculation unit is called to recalculate the instruction boundary information.

[0018] In some embodiments, the apparatus further comprises an instruction cache for caching instruction packets to which instruction prediction information is added.

[0019] In some embodiments, the device is a processor core.

[0020] In some embodiments, the device is a processor.

[0021] In a second aspect, an embodiment of the present invention provides an instruction processing method, including:

[0022] Obtaining an instruction packet of a variable-length instruction set, and adding instruction prediction information to each instruction element field in the instruction packet; and

[0023] At the instruction fetch stage of the instruction pipeline, one or more instructions are determined based on the instruction prediction information.

[0024] In some embodiments, instruction prediction information of each instruction metafield is obtained by the following steps:

[0025] Determining all possible settings of a first instruction element field in the instruction packet under the variable-length instruction set;

[0026] The instruction prediction information of the current instruction metafield is determined based on the instruction prediction information and decoding information of the previous instruction metafield.

[0027] In some embodiments, instruction prediction information of the current instruction metafield is determined based on instruction prediction information and decoding information of the previous x instruction metafields, where the value of x is related to the maximum instruction encoding length in the variable-length instruction set and the length of the instruction metafield.

[0028] In some embodiments, determining one or more instructions according to the instruction prediction information includes:

[0029] Determine the instruction meta-field corresponding to the program pointer, and obtain instruction prediction information of the instruction meta-field corresponding to the program pointer accordingly;

[0030] If the instruction prediction information of the instruction meta-field corresponding to the program pointer includes an entry representing an instruction header, the entry is used as the instruction boundary information, and one or more instructions are obtained accordingly.

[0031] In some embodiments, the instruction processing method further comprises: if the instruction prediction information of the instruction meta-field corresponding to the program pointer does not include an entry representing an instruction header, recalculating instruction boundary information.

[0032] In some embodiments, the further step includes: caching instruction packets to which instruction prediction information is added.

[0033] In a third aspect, an embodiment of the present invention provides a computer system, including: a memory;

[0034] a processor coupled to the memory, the processor comprising:

[0035] An instruction boundary prediction unit, used for acquiring an instruction packet of the variable-length instruction set and adding instruction prediction information to each instruction element field in the instruction packet;

[0036] An instruction pipeline structure, wherein an instruction fetch unit of the instruction pipeline structure comprises an instruction boundary determination unit, and the instruction boundary determination unit is used to determine one or more instructions according to the instruction prediction information.

[0037] In a fourth aspect, an embodiment of the present invention provides a system on chip, comprising an instruction processing device as described in any one of the above.

[0038] Compared with the prior art, the advantages of the embodiments of the present invention are: before entering the instruction pipeline structure, instruction prediction information is added to each instruction meta-field, so that the instruction fetch unit can determine the instruction boundary information based on the instruction prediction information, thereby determining the instruction boundary information more quickly, avoiding spending too much time to determine the instruction boundary information, and further avoiding the problem of needing to add additional pipeline stages due to insufficient time to pre-decode the current instruction (such as a branch instruction) in the current instruction fetch cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and other objects, features and advantages of the present invention will become more apparent through the description of the embodiments of the present invention with reference to the following drawings, in which:

[0040] Figure 1 is a schematic diagram of the structure of a computer system for implementing an embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of the structure of a system on a chip for implementing an embodiment of the present invention;

[0042] Figure 3 is a schematic diagram of the structure of a processor core for implementing an embodiment of the present invention;

[0043] Figure 4 yes Figure 3 Schematic diagram of the input and output of the instruction prediction unit in;

[0044] Figure 5a and Figure 5b Schematic diagrams of prediction logic for 16 / 32 bit variable length instruction sets are shown respectively;

[0045] Figure 5c A schematic diagram showing prediction logic applicable to any variable-length instruction set is shown;

[0046] Figure 6 A schematic diagram showing the confirmation logic of the instruction confirmation unit is shown;

[0047] Figure 7 Shows Figure 3 More details of the front end unit 301 are shown;

[0048] Figure 8 yes Figure 7 An embodiment variation of the invention is described below. DETAILED DESCRIPTION

[0049] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0050] The following terms are used in this article.

[0051] Variable-length instruction set: the instruction encoding length of the instructions in the instruction set is variable. For example, the instruction set includes both instructions encoded in 16 bits and instructions encoded in 32 bits.

[0052] An instruction packet is a fixed-length binary segment that the processor obtains from the instruction cache or external bus.

[0053] Instruction prediction information is used to indicate whether an instruction meta-field is an instruction header, instruction tail, or any of the segments in the middle of an instruction.

[0054] The instruction header information is used to indicate whether an instruction meta-field in the instruction packet is an instruction header. If the instruction header information of all instruction meta-fields in the instruction packet is determined, the instruction boundary information is also determined.

[0055] Instruction boundary information, in variable-length coded instruction sets, instructions are not aligned according to addresses in memory, so it is necessary to obtain the boundary of each instruction, that is, the location of the instruction header of an instruction on a block of continuous addresses. In this article, the instruction header information and instruction boundary information can be information that is compared and analyzed to confirm the instruction prediction information, or it can be information obtained by the instruction boundary calculation unit. This information can basically be considered as the real instruction boundary information unless the calculation or prediction is wrong.

[0056] Instruction meta fields are fields extracted from the instruction packet according to the greatest common divisor of the lengths of the instruction codes in the variable-length instruction set. For example, if an instruction packet contains two instruction codes, the instruction code lengths are 8 bits and 16 bits respectively, then instruction meta fields are extracted from the instruction packet according to 8 bits.

[0057] Instruction cache, the first level of cache, is used to store individual instructions.

[0058] Program PC, program pointer.

[0059] Instruction pipeline, the instruction pipeline is to improve the efficiency of the processor in executing instructions by dividing the operation of an instruction into multiple small steps, each step is completed by a special circuit. The current mainstream instruction pipeline technologies include three-level, four-level, five-level, seven-level and super instruction pipelines, etc. For example, the five-level instruction pipeline in the textbook example includes the instruction fetch level, decoding level, execution level, memory access level and write-back level. In this article, the instruction fetch level, decoding level, execution level, memory access level and write-back level are also called instruction fetch unit, decoding unit, execution unit, memory access unit and retirement unit. The combination of software and hardware that implements the instruction pipeline is called the instruction pipeline structure.

[0060] Figure 1 is a schematic diagram of the structure of a computer system for implementing the present invention. Figure 1 , system 100 is an example of a "central" system architecture. System 100 can be built based on various processor models currently on the market and is powered by WINDOWS TM Operating system version, UNIX operating system, Linux operating system, etc. Operating system drivers. In addition, the system 100 is generally implemented in a PC, a desktop, a notebook, or a server.

[0061] like Figure 1 As shown, system 100 includes processor 102. Processor 102 has data processing capabilities known in the art. It can be a processor of complex instruction set (CISC) architecture, reduced instruction set (RISC) architecture, very long instruction set (VLIW) architecture, or a processor that implements a combination of the above instruction sets, or any processor device built for a specific purpose.

[0062] The processor 102 is coupled to the system bus 101, which can transmit data signals between the processor 102 and other components. The processor 102 also includes a processor core 1021 improved according to the technical solution provided by the embodiment of the present invention, and its specific details will be provided below.

[0063] The system 100 also includes a memory 104 and a graphics card 105. The memory 104 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or other memory devices. The memory 104 may store instruction information and / or data information represented by data signals. The graphics card 105 includes a display driver for controlling the correct display of display signals on a display screen.

[0064] The graphics card 105 and the memory 104 are coupled to the system bus 101 via the memory controller hub 103. The processor 102 can communicate with the memory controller hub 103 via the system bus 101. The memory controller hub 103 provides a high-bandwidth memory access path 421 to the memory 104 for storing and reading instruction information and data information. At the same time, the memory controller hub 103 and the graphics card 105 transmit display signals based on the graphics card signal input and output interface 420. The graphics card signal input and output interface 420 is, for example, an interface type such as DVI, HDMI, etc.

[0065] The memory controller hub 103 not only transmits digital signals between the processor 102 , the memory 103 and the graphics card 105 , but also bridges digital signals between the system bus 101 and the memory 104 and the input / output control hub 106 .

[0066] The system 100 further includes an input / output control center 106, which is coupled to the memory controller center 103 via a dedicated hub interface bus 422, and some I / O devices are connected to the input / output control center 106 via a local I / 0 bus. The local I / 0 bus is used to couple peripheral devices to the input / output control center 106, and then to the memory controller center 103 and the system bus 101. The peripheral devices include, but are not limited to, the following devices: a hard disk 107, an optical drive 108, a sound card 109, a serial expansion port 110, an audio controller 111, a keyboard 112, a mouse 113, a GPIO interface 114, a flash memory 115, and a network card 116.

[0067] Of course, different computer systems have different structure diagrams according to different motherboards, operating systems and instruction set architectures. For example, many computer systems currently integrate the memory controller center 103 into the processor 102, so that the input / output control center 106 becomes a control center coupled to the processor 103.

[0068] Figure 2 2 is a schematic diagram of a system on chip 200 for implementing the present invention. The system 200 as a system on chip can be produced and sold as an independent device, or combined with other components to form a new device for production and sale.

[0069] System 200 can be manufactured using various processor models currently on the market and can be powered by WINDOWS TM, UNIX, Linux and Android, RTOS and other operating systems. System 200 can be implemented in computer devices, handheld devices and embedded products. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs) and handheld PCs. Embedded products can include network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can execute one or more instructions.

[0070] refer to Figure 2 As shown, the system 200 includes a processor 202 , a static random access memory 205 , an LCD controller 204 , a flash memory 206 , and an AHB / APB bridge 207 coupled via an AHB (Advanced High performance Bus, system bus) bus 201 .

[0071] The processor 202 may be a complex instruction set (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction set (VLIW) microprocessor, a microprocessor implementing a combination of the above instruction sets, or any other processor device. The processor 202 also includes a processor core 221 improved according to the technical solution provided in an embodiment of the present invention, and its specific details will be provided below.

[0072] The static random access memory 205 and the flash memory 206 are used to store instruction information and / or data information represented by digital signals. For example, the static random access memory 205 can be used as a running space for various applications, creating heaps, stacks, storing intermediate data, etc. for various applications, and the flash memory 206 can store executable codes of various applications and executable codes of the operating system.

[0073] The AHB bus 201 is used to transmit digital signals between high-performance modules of the system 200 , such as transmitting digital signals between the processor 202 and the static random access memory 205 , the processor 202 and the LCD controller 204 , the processor 202 and the flash memory 206 , and the processor 202 and the AHB / APB bridge 207 .

[0074] The AHB / APB bridge 407 is used to bridge data transmission between the AHB bus and the APB bus, and realizes the conversion from the AHB protocol to the APB protocol by latching the address, data and control signals from the AHB bus and providing secondary decoding to generate the selection signal of the APB peripheral device.

[0075] The system 200 may also include various interfaces coupled to the APB bus. The various interfaces include, but are not limited to, the following interface types: Secure Digital High Capacity (SDHC), I2C bus, Serial Peripheral Interface (SPI), Universal Asynchronous Receiver / Transmitter (UART), Universal Serial Bus (USB), General-purpose input / output (GPIO), and Bluetooth UART. Peripheral devices coupled to the interface are, for example, USB devices, memory cards, message transceivers, Bluetooth devices, etc.

[0076] It should be pointed out that Figure 1 and Figure 2 The system shown is only used to illustrate the application scenario of the embodiment of the present invention, and is not intended to limit the embodiment of the present invention. In theory, the processor or processor core improved according to the embodiment of the present invention can be applied to a system with any processor architecture.

[0077] Figure 3 1 is a schematic diagram of the structure of a processor core according to an embodiment of the present invention. In the figure, arrows represent the coupling relationship between two or more units and the data transmission direction between the two.

[0078] like Figure 3 As shown, the processor core 300 includes a front end unit 301 , an engine unit 302 , and a memory unit 303 coupled to the system 300 .

[0079] The front end unit 301 includes a coupled instruction boundary prediction unit 3011, an instruction cache unit 3012, an instruction TLB 3013, an AND / OR gate 3014, an instruction fetch unit 3015, and a decoding unit 3016. The instruction cache unit 3012 can be further coupled to a level 2 (L2) cache unit 3033 in the memory unit 303 to facilitate the transfer of instruction data.

[0080] Instruction packet PCK1 comes from processor core 300 or other components in the processor, or is provided by a bus. Instruction boundary prediction unit 3011 obtains and parses instruction packet PCK1, adds instruction prediction information to each instruction element field in instruction packet PCK1, and obtains instruction packet PCK2 (including PCK1 and instruction prediction information). Instruction boundary prediction unit 3011 can store instruction packet PCK2 in instruction cache 3012, or directly send instruction packet PCK2 to instruction fetch unit 3015 for processing. For illustration only, Figure 1 An AND-OR gate 3014 is used to indicate that the information input to the instruction fetch unit 3015 can come directly from the output of the instruction boundary prediction unit 3011 or from the instruction cache 3012. The instruction fetch unit 3015 can include an instruction boundary confirmation unit 30151. The instruction fetch unit 3015 obtains the physical address from the instruction TLB unit 3013 according to the program PC and obtains the instruction packet from the instruction cache 3012 accordingly, then calls the instruction boundary confirmation unit to determine the instruction boundary information according to the prediction information, and obtains multiple instructions from the instruction packet according to the instruction boundary information, and then pre-decodes each instruction to obtain pre-decoding information, such as whether the instruction is a branch instruction, the jump direction and target address of the branch instruction, etc.

[0081] The decoding unit 3016 can decode the instruction according to the instruction set architecture, determine what operation the instruction is, and determine how the instruction pipeline processes the instruction. The instruction set architecture is determined by the manufacturer of the processor. When the program is compiled into an executable form, the compiler only uses the instructions defined in the instruction set architecture to organize the executable code. If the compiler uses an undefined instruction, the decoding unit 3016 cannot understand the meaning that the instruction is trying to express, causing the instruction decoding to fail.

[0082] The decoding unit 3016 may be further coupled to a scheduler unit 3021 in the engine unit 302. The engine unit 302 may include a coupled scheduler unit 3021, a retirement unit 3022, a register file unit 3023, and an execution module 3024. The scheduler unit 3021 may be coupled to the register file unit 3023. The scheduler unit 3021 may schedule multiple instructions in the instruction pipeline, such as adjusting the execution order of instructions in the instruction pipeline (e.g., out-of-order execution, etc.), or routing an instruction to multiple execution units at the same time. In an optional embodiment, the decoding unit 3016 and the scheduler unit 3021 may also be combined into one unit.

[0083] The register file unit 3023 represents one or more physical register files, and different physical register files store one or more different data types (e.g., scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc.), status (such as the instruction PC of the next instruction), etc. In an optional embodiment, the register file unit 3023 can be overwritten by the retirement unit 3022 to implement various modes of register renaming and out-of-order execution. Examples of registers in the physical register file include but may not be limited to dedicated physical registers, dynamically allocated physical registers using register renaming, and a combination of dedicated physical registers and dynamically allocated physical registers, etc.

[0084] The retirement unit 3022 and the physical register file unit 3023 may be coupled to an execution module 3024. The execution module 3024 may include one or more execution units 30241 and one or more memory access units 30242. Each execution unit 30241 may perform a corresponding operation (e.g., shift, addition, subtraction, multiplication) on a type of data. The memory access unit 30242 may be coupled to a memory unit 303, which may include a data TLB unit 3031 coupled to a data cache unit 3032, wherein the data cache unit is coupled to a level 2 (L2) cache unit 3033. The L2 cache unit 3033 may also be coupled to one or more other levels of cache (not shown), and ultimately coupled to a main memory (a memory coupled via a system bus). Although Figure 3 Instruction cache unit 3012, data cache unit 3032, and L2 cache unit 3033 are shown, but in other embodiments, in different combinations, one or more caches or cache units may be inside the core, outside the core, or partially inside the core and partially outside the core; and although the embodiment shown in the processor may also include separate instruction and data cache units and a shared L2 cache unit, other embodiments may have a single internal cache for both instructions and data. In some embodiments, the system may include a combination of internal caches and external caches that may be external to the core and / or processor. In other embodiments, all caches may be external to the core and / or processor.

[0085] It should be pointed out that there are differences in the processing speed of instructions among the instruction fetch unit 3015, the decoding unit 3016, the scheduler unit 3021, and the execution module 3024. It is generally necessary to set an instruction cache between the two, or to adjust the speed difference by setting different numbers of units, for example, one instruction fetch unit corresponds to multiple execution modules 3024.

[0086] In addition, although the instruction fetch unit, decoding unit, scheduler unit, execution unit, memory access unit and retirement unit are used to implement the instruction pipeline structure in the figure (the instruction boundary prediction unit is not a component of the instruction pipeline structure), the present invention is not limited to this. Those skilled in the art may use other instruction pipelines to implement this embodiment, such as using the standard five-stage pipeline structure shown in the textbook to implement this embodiment, or using a super instruction pipeline structure to implement this embodiment.

[0087] Compared with the prior art, the advantages of the embodiments of the present invention are: before entering the instruction pipeline structure, the instruction prediction information is added to each instruction meta-field, so that the instruction fetch unit can determine the instruction boundary information according to the instruction prediction information, thereby determining the instruction boundary information more quickly, avoiding spending more logical length to determine the instruction boundary information, and further avoiding the problem of adding additional pipeline stages due to insufficient time to pre-decode instructions (such as branch instructions) in the current instruction fetch cycle. To illustrate with an example. If the instruction fetch unit cannot promptly determine that the current instruction is a branch instruction in the current instruction fetch cycle, it cannot promptly obtain the instruction packet at the jump target address, so it may be necessary to add an empty beat in the instruction pipeline to wait for the instruction packet to be obtained from the jump target address.

[0088] In the following embodiments, various aspects of the instruction boundary prediction unit and the instruction boundary determination unit will be described in further detail.

[0089] Figure 4 yes Figure 3 Schematic diagram of the input and output of the instruction prediction unit in . Figure 4 As shown, the instruction prediction unit 3011 obtains the instruction packet PCK1 including the instruction meta-fields H1-Hn, and outputs the instruction packet PCK2 including the added prediction information. As shown in the figure, the prediction information of the instruction meta-field H1 is shown as e0 to en, and the prediction information of the instruction meta-fields H2-Hn is shown as inf2-infn. The reason for this is that it is generally necessary to infer the prediction information of the current instruction meta-field based on the prediction information of the previous instruction meta-field, but as the first instruction meta-field, the instruction meta-field H1 has no other instruction meta-fields before, so here e0 to en represent various possible assumptions, for example, e0 represents that the instruction meta-field H1 is an instruction header, e1 represents that the instruction meta-field H1 is not an instruction header, and so on. Afterwards, the prediction information inf2 of the instruction meta-field H2 can be obtained according to various assumptions e0-en, and then the prediction information of the instruction meta-field H3 can be obtained according to various assumptions e0-en and the prediction information inf2. And so on.

[0090] based on Figure 4As shown, in one embodiment, the prediction information solving logic is set as follows: the instruction prediction information of the current instruction meta-field is determined based on the instruction prediction information and decoding information of the previous x instruction meta-fields. Where x = A / B-1, where A represents the maximum instruction encoding length in the variable-length instruction set, and B represents the length of the instruction meta-field. Below, two examples are used to illustrate how this method works.

[0091] ■16 / 32bit variable length instruction set prediction logic

[0092] The instruction encoding length of the instruction set is 16 bits and 32 bits, so the instruction metafield length is 16 bits, and the value of X is 1. According to the above formula, the instruction prediction information of the next instruction metafield can be obtained based on the instruction prediction information and decoding information of the previous instruction metafield. For 16 / 32bit mixed instructions, for each instruction metafield, there are only two hypothetical situations: the instruction metafield is an instruction header and it is not an instruction header. Figure 5a and Figure 5b Schematic diagrams of starting logic solving based on two assumptions: the instruction element field H1 is not an instruction header and is an instruction header.

[0093] refer to Figure 5a As shown, the logic solution starts from the instruction metafield H1 is not the instruction header. If H1 is not the instruction header, then H2 must be the instruction header. The instruction metafield H2 is determined by decoding to be either a single metafield length (16bit) or a double metafield length (32bit). When the instruction metafield H2 is a single metafield, the instruction metafield H3 can only be the instruction header. When the instruction metafield H2 is a double metafield, H3 must not be the instruction header. The instruction metafield H3 is determined by decoding to be either a single metafield length (16bit) or a double metafield length. When the instruction metafield H3 is a single metafield, the instruction metafield H4 can only be the instruction header. When the instruction metafield H3 is a double metafield and the instruction metafield H3 is not the instruction header, the instruction metafield H4 is not the instruction header. By analogy, the instruction prediction information of the instruction metafields H4-Hn can be obtained.

[0094] refer to Figure 5bAs shown, the logic solution is started from the instruction metafield H1 being the instruction header. The instruction metafield H1 is determined through decoding to be either a single metafield length (16 bits) or a double metafield length (32 bits). When the instruction metafield H1 is a single metafield, the instruction metafield H2 can only be the instruction header. When the instruction metafield H1 is a double metafield, the instruction metafield H2 is not the instruction header. The instruction metafield H2 is determined through decoding to be either a single metafield length (16 bits) or a double metafield length. When the instruction metafield H2 is the instruction header of the single metafield, the instruction metafield H3 is the instruction header. When the instruction metafield H2 is a single metafield and is not the instruction header, the instruction metafield H3 can only be the instruction header. By analogy, prediction information can be given to the instruction metafields H4-n.

[0095] ■16 / 24 / 32 mixed prediction logic

[0096] The instruction encoding length of the instruction set is 16 bits, 24 bits, and 32 bits, so the instruction metafield length is 8 bits, and the value of X is 3. Then the instruction prediction information and decoding information of the first three metafields are used to obtain the instruction header information of the current instruction metafield. As shown in the following table, by checking the decoding information of the instruction metafields H1-H4, it is possible to obtain information on whether the instruction metafield H5 is an instruction header.

[0097]

[0098] From the above table, for the instruction element field H4, there are the following situations:

[0099] If the instruction metafield H1 is the instruction header of a 32-bit instruction and the instruction metafield H4 is not the instruction header, then the instruction metafield 5 is the instruction header;

[0100] If the instruction metafield H2 is the instruction header of a 32-bit instruction and the instruction metafield H4 is not the instruction header, then the instruction metafield 5 is not the instruction header;

[0101] If the instruction metafield H3 is the instruction header of a 32-bit instruction and the instruction metafield H4 is not the instruction header, then the instruction metafield 5 is not the instruction header;

[0102] If the instruction element field H2 is the instruction header of the 24-bit instruction and the instruction element field H4 is not the instruction header, then the instruction element field 5 is the instruction header;

[0103] If the instruction element field H3 is the instruction header of the 24-bit instruction and the instruction element field H4 is not the instruction header, then the instruction element field 5 is not the instruction header;

[0104] If the instruction element field H3 is the instruction header of the 16-bit instruction and the instruction element field H4 is not the instruction header, then the instruction element field 5 is the instruction header;

[0105] When the instruction metafield H4 is the instruction header of a 32-bit instruction, the instruction metafield 5 is not the instruction header;

[0106] When the instruction metafield H4 is the instruction header of a 24-bit instruction, the instruction metafield 5 is not the instruction header;

[0107] When the instruction element field H4 is the instruction header of a 26-bit instruction, the instruction element field 5 is not the instruction header.

[0108] Through the above logic, it is determined whether the instruction element field 5 is an instruction header.

[0109] For the mixed 16 / 24 / 32 encoding, there are seven hypothetical situations for the first instruction meta-field of the instruction packet. That is, assuming that the first instruction meta-field of the instruction packet is as follows, the instruction header prediction information that needs to be expanded for each meta-field needs to be solved according to the above logic:

[0110] Ex significance e0 It is not the instruction header, but the second meta field of the 32-bit instruction. e1 It is not the instruction header, but the third element field of the 32-bit instruction. e2 It is not the instruction header, but the fourth element field of the 32-bit instruction. e3 It is not the instruction header, but the second meta field of the 24-bit instruction. e4 It is not the instruction header, but the third element field of the 24-bit instruction. e5 It is not the instruction header, but the second meta field of the 16-bit instruction. e6 Instruction Header

[0111] In the above embodiment, by checking whether the current instruction meta-field is an instruction header, and combining the decoding information of the current field, it is determined whether the next field is an instruction header. For example, if the current field is an instruction header and the decoding information shows that it is a 32-bit instruction, then the next meta-field is not an instruction header. If the current field is not an instruction header, the next meta-field must be an instruction header.

[0112] ■General solution logic

[0113] This method is applicable to the instruction header prediction information of different instruction packet lengths and different instruction encoding lengths. The solution process is as follows:

[0114] For ex from e0 to en: #Assuming that H1 is the header, middle segments, and tail of the instruction encoding,

[0115] # Solve the information of the next segment in sequence

[0116] For Hx from H2 to Hn

[0117] Combine the ex(e0-en) and decoding information of the first x instruction metafields to get ex(e0-en) of Hx+1. Among them, H1_e[x] is the prediction information corresponding to each instruction code length under the traversal assumption (e0-en). Let L0 be the minimum encoding length in the instruction set, LN be the maximum encoding length in the instruction set, and LE be the length of the instruction metafield. Then use the following code to solve H1_e[x].

[0118]

[0119] Figure 5cThe following is a schematic diagram of the general solution logic. Figure 5c As shown, under the assumption that the condition is e0, the instruction header information is judged according to the decoding information of the instruction meta-field H1 to obtain the instruction prediction information H1-e0 of H1, and then the instruction header information is judged according to H1-e0 and the decoding information of the instruction meta-field H2 to obtain the instruction prediction information H2-e0 of H2, and so on. Through a limited number of exhaustive logics, the prediction information of each instruction meta-field can be obtained.

[0120] go through Figure 5c After calculating the prediction information of each instruction, the solution logic stores the instruction together with the instruction prediction information into the instruction cache. The instruction fetch unit obtains an instruction packet from the instruction cache or off-chip according to the aligned address (when the instruction cache is off-chip). The instruction packet contains an instruction and the above-mentioned instruction prediction information. The instruction boundary information can be quickly obtained through the instruction boundary confirmation unit 30151.

[0121] Figure 6 The schematic diagram of the confirmation logic of the instruction confirmation unit 30151 is shown. As shown in the reference figure, the instruction boundary confirmation unit 30151 confirms the valid instruction meta-field from the instruction packet according to the program pointer (PC), wherein the starting position of the valid instruction meta-field in the instruction packet is indicated by the program PC. For example, if the instruction packet is 256 bits, 64 bytes, the value of the lower 6 bits of the PC indicates the start of the valid meta-field. If the value of the lower 6 bits of the program PC is 8, the valid meta-field starts from the 8th byte. The instruction meta-field start_ex marked as the instruction header is selected from the instruction meta-field. If the instruction prediction information e0-en of the corresponding instruction meta-field is found according to start_ex, the entry with a value of 1 in the prediction information e0-en is used as the instruction boundary information (hx_head) (x is fetched as 0...n). If the instruction prediction information corresponding to start_ex does not contain an entry of 1, it means that the instruction prediction is wrong and the instruction boundary information needs to be recalculated. The above logic can be implemented by an AND or OR gate, which greatly reduces the logic length.

[0122] In principle, if there is no data information in the instruction segment of the program, that is, the instruction segment is full of instruction information, then the above method can definitely directly obtain the correct instruction boundary information. However, if the instruction segment of the program contains data, then the above method may not be able to obtain the correct instruction boundary information, and the correct instruction boundary will need to be recalculated based on the actual position of the program PC in the instruction packet. For details, see Figure 7 shown.

[0123] Figure 7 Shows Figure 3 More details of the front end unit 301 are shown. Figure 7 As shown, the instruction boundary confirmation unit 30151 receives the program PC and the instruction packet PCK2 with added prediction information, determines the instruction meta field corresponding to the program PC in the instruction packet PCK2, the instruction meta field should be the instruction header of an instruction, finds the entry representing the instruction header in the instruction prediction information corresponding to the instruction meta field, the entry and the instruction prediction information corresponding to the entry are the instruction boundary information, and one or more instructions can be obtained accordingly. The instruction fetch unit 3015 can then pre-decode the instruction to determine whether the instruction is a branch instruction. If an instruction is a branch instruction, the branch jump prediction unit 3017 can be retrieved according to the program PC of the instruction to obtain the target jump address, and the jump behavior 701 is executed according to the target jump address to obtain the instruction packet at the target jump address, and the instruction is stored in the instruction cache 3018 for the decoding unit 3016 to read and decode from it.

[0124] When the instruction boundary confirmation unit 30151 determines the instruction meta-field corresponding to the program PC in the instruction packet PCK2, the instruction meta-field should be the instruction header of an instruction, but there is another possibility: the entry representing the instruction header cannot be found in the instruction prediction information corresponding to the instruction meta-field, indicating a prediction error. At this time, the instruction boundary calculation unit 30152 needs to be called to recalculate the instruction boundary information.

[0125] The instruction boundary prediction method provided by the embodiment of the present invention shortens the logical length of confirming the instruction boundary information, and at the same time, the logical length from confirming the boundary information to executing the jump behavior is also shortened. This method is particularly suitable for deep instruction pipelines and can significantly improve the execution efficiency of the instruction pipeline. The instruction boundary prediction method provided by the present invention is not affected by the order in which the processor views the instruction stream.

[0126] Figure 8 yes Figure 7 A variation of the embodiment based on the invention. Figure 8 , the instruction packet PCK11 that has passed through the instruction boundary prediction unit 3011 and the instruction packet PCK12 that has not passed through the instruction boundary prediction unit 3011 are shown. The processing flow of PCK11 is as follows: Figure 7 As shown, no further description is given here. Instruction PCK12 is directly stored in the instruction cache 3012. When the instruction fetch unit 3015 obtains an instruction packet from the instruction cache 3012, it is detected by the detection unit 3019. The detection unit 3019 distinguishes instruction packets PCK21 and PCK12 by detecting whether the instruction packet contains instruction prediction information. The instruction packet PCK12 is calculated by the instruction boundary calculation unit 30152 to obtain multiple instructions from the instruction packet PCK12.

[0127] exist Figure 8 In the embodiment, two hardware logics for processing instructions of variable-length instruction sets are integrated to be suitable for different application scenarios and take into account the characteristics of the two hardware logics. Specifically, adding instruction prediction information to each instruction in the instruction packet can help the instruction unit to parse the instruction faster, but it will take up more storage space of the instruction cache. If the two are integrated in the same instruction fetch unit, one of the hardware logics can be used according to actual needs.

[0128] The present invention can be implemented in hardware or dedicated circuits, software, logic or any combination thereof. For example. A processing device for implementing the present invention is added outside the instruction fetch unit, and the processing device is implemented by hardware logic or software firmware. The processing device implements taking out instruction packets from the cache, adding instruction prediction information to each instruction and then calling back to the instruction cache. At the same time, the hardware logic of the instruction fetch unit is modified so that the instruction fetch unit preferentially uses the instruction prediction information to obtain instruction boundary information. The technical solution of the embodiment of the present invention is implemented in this way. Of course, the present invention is not limited to this. The apparatus and method described in the text can also be reconstructed with hardware, software, software, dedicated circuits or logic, general hardware or controllers or other computing devices, or some combination thereof. If involved, the circuit design of the present invention can be implemented in various components such as integrated circuit modules.

[0129] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An instruction processing device for processing instructions of a variable-length instruction set, comprising: An instruction boundary prediction unit, used for acquiring an instruction packet of the variable-length instruction set and adding instruction prediction information to each instruction element field in the instruction packet; An instruction pipeline structure, wherein an instruction fetch unit of the instruction pipeline structure includes an instruction boundary determination unit, wherein the instruction boundary determination unit is used to determine one or more instructions according to the instruction prediction information, The instruction boundary prediction unit obtains instruction prediction information of each instruction meta-field through the following steps: Determining all possible settings of a first instruction element field in the instruction packet under the variable-length instruction set; The instruction prediction information of the current instruction metafield is determined based on the instruction prediction information and decoding information of the previous instruction metafield.

2. The instruction processing device according to claim 1 determines the instruction prediction information of the current instruction meta-field based on the instruction prediction information and decoding information of the first x instruction meta-fields, wherein the value of x is related to the maximum instruction encoding length in the variable-length instruction set and the length of the instruction meta-field.

3. According to the instruction processing device according to claim 1, the instruction boundary determination unit determines the instruction meta-field corresponding to the program pointer, and obtains the instruction prediction information of the instruction meta-field corresponding to the program pointer accordingly; if the instruction prediction information of the instruction meta-field corresponding to the program pointer contains an entry representing an instruction header, the entry is used as the instruction boundary information, and one or more instructions are obtained accordingly. 4 . The instruction processing apparatus according to claim 3 , wherein if the instruction prediction information of the instruction meta-field corresponding to the program pointer does not include an entry indicating an instruction header, an instruction boundary calculation unit is called to recalculate the instruction boundary information. 5 . The instruction processing device according to claim 1 , further comprising an instruction cache for caching instruction packets to which instruction prediction information is added. 6 . The instruction processing device according to claim 1 , wherein the instruction processing device is a processor core.

7. The instruction processing device according to any one of claims 1 to 5, wherein the instruction processing device is a processor.

8. A method for processing an instruction, comprising: Obtaining an instruction packet of a variable-length instruction set, and adding instruction prediction information to each instruction element field in the instruction packet; as well as At the instruction fetch stage of the instruction pipeline, one or more instructions are determined according to the instruction prediction information, wherein the instruction prediction information of each instruction meta-field is obtained by the following steps: Determining all possible settings of a first instruction element field in the instruction packet under the variable-length instruction set; The instruction prediction information of the current instruction metafield is determined based on the instruction prediction information and decoding information of the previous instruction metafield.

9. The instruction processing method according to claim 8 determines the instruction prediction information of the current instruction meta-field based on the instruction prediction information and decoding information of the first x instruction meta-fields, wherein the value of x is related to the maximum instruction encoding length in the variable-length instruction set and the length of the instruction meta-field.

10. The instruction processing method according to claim 9, wherein determining one or more instructions according to the instruction prediction information comprises: Determine the instruction meta-field corresponding to the program pointer, and obtain instruction prediction information of the instruction meta-field corresponding to the program pointer accordingly; If the instruction prediction information of the instruction meta-field corresponding to the program pointer includes an entry representing an instruction header, the entry is used as the instruction boundary information, and one or more instructions are obtained accordingly.

11. The instruction processing method according to claim 10, further comprising: If the instruction prediction information of the instruction metafield corresponding to the program pointer does not include an entry indicating an instruction header, the instruction boundary information is recalculated.

12. The instruction processing method according to claim 9, further comprising: The cache adds instruction prediction information to the instruction packet.

13. A computer system comprising: Memory; a processor coupled to the memory, the processor comprising: An instruction boundary prediction unit, used for acquiring an instruction packet of a variable-length instruction set and adding instruction prediction information to each instruction element field in the instruction packet; An instruction pipeline structure, wherein an instruction fetch unit of the instruction pipeline structure includes an instruction boundary determination unit, wherein the instruction boundary determination unit is used to determine one or more instructions according to the instruction prediction information, The instruction boundary prediction unit obtains instruction prediction information of each instruction meta-field through the following steps: Determining all possible settings of a first instruction element field in the instruction packet under the variable-length instruction set; The instruction prediction information of the current instruction metafield is determined based on the instruction prediction information and decoding information of the previous instruction metafield.

14. A system on chip, comprising the instruction processing device according to any one of claims 1 to 5.

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