Wafer-level chip packaging structure and packaging method

Abstract

The present invention provides a wafer-level packaging structure and packaging method, the packaging method comprising: providing a supporting substrate, forming a temporary bonding layer and a patch film; fixing a chip to be packaged on the patch film; preparing a conductive column; using a packaging layer to package the chip to be packaged to prepare a rewiring layer; preparing a metal bump; peeling off the supporting substrate based on the temporary bonding layer. The present invention adopts a method of first performing patching and then preparing a rewiring layer. In fan-out wafer-level packaging, it is beneficial to shorten the process, reduce the operation cycle, improve the product yield, and reduce the product cost. It realizes effective six-sided packaging of wafer-level chips, better packaging chips, and improves product reliability. The metal bumps are formed by solder paste printing or ball planting, which reduces the complexity of the process.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a wafer-level chip packaging structure and a packaging method. Background Art

[0002] As integrated circuits become more powerful, with higher performance and integration, and new types of integrated circuits emerge, packaging technology plays an increasingly important role in integrated circuit products, accounting for an increasing proportion of the value of the entire electronic system. At the same time, as the feature size of integrated circuits reaches the nanometer level, transistors develop towards higher density and higher clock frequency, and packaging also develops towards higher density.

[0003] Due to the advantages of miniaturization, low cost and high integration, as well as better performance and higher energy efficiency, fan-out wafer-level packaging (FOWLP) technology has become an important packaging method for electronic devices such as high-demand mobile / wireless networks, and is one of the most promising packaging technologies at present.

[0004] However, in the existing fan-out packaging, it is difficult to achieve simple and effective comprehensive packaging for the wafer-level packaging structure, and the packaging process is long and the preparation cycle is long, which affects the operating efficiency. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a wafer-level chip packaging structure and packaging method, which are used to solve the problems in the prior art that it is difficult to achieve simple and effective comprehensive packaging and the process cycle is long.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a wafer-level chip packaging method, which comprises the following steps:

[0007] Providing a supporting substrate, and forming a temporary bonding layer on the supporting substrate;

[0008] Providing a chip to be packaged and a die bonding film, forming the die bonding film on the temporary bonding layer, wherein the chip to be packaged has a first surface and a second surface opposite to each other, fixing the chip to be packaged on the die bonding film, and making the first surface of the chip to be packaged contact with the die bonding film;

[0009] Preparing a conductive column on the second surface of the chip to be packaged, wherein the conductive column is electrically connected to the chip to be packaged;

[0010] The chip to be packaged is packaged with a packaging layer, the top surface of the conductive pillar is exposed on the packaging layer, and the packaging layer and the chip mounting film cover the chip to be packaged;

[0011] Preparing a rewiring layer on the packaging layer, wherein the rewiring layer is electrically connected to the conductive pillar;

[0012] Preparing a metal bump on a side of the rewiring layer away from the packaging layer, so as to electrically lead out the chip to be packaged through the rewiring layer and the conductive pillar; and

[0013] The die attach film and the supporting substrate are peeled off based on the temporary bonding layer.

[0014] Optionally, after forming the temporary bonding layer, the method further includes forming an adhesion protection layer on the temporary bonding layer, and the die attach film is formed on the surface of the adhesion protection layer.

[0015] Optionally, the adhesion protection layer includes a polyimide layer.

[0016] Optionally, the step of preparing the rewiring layer includes: forming a dielectric layer and a metal stack structure on the upper surface of the packaging layer, the metal stack structure is electrically connected to the conductive column to electrically lead out the chip to be packaged, wherein the metal stack structure is located in the dielectric layer, the metal stack structure includes a plurality of layers of metal wire layers and metal plugs arranged at intervals, and the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers.

[0017] Optionally, the metal bump includes one of tin solder, silver solder and gold-tin alloy solder.

[0018] Optionally, the temporary bonding layer includes a light-to-heat conversion layer, wherein the light-to-heat conversion layer is irradiated with a laser to separate the light-to-heat conversion layer from the chip film and the supporting substrate, thereby peeling off the chip film and the supporting substrate.

[0019] Optionally, the method for forming the metal bump comprises the following steps:

[0020] Preparing a patterned surface layer on the rewiring layer, wherein the patterned surface layer exposes a pad area on the rewiring layer where the metal bump is to be formed;

[0021] The metal bump is formed on the pad area based on the patterned surface layer, and the formation of the metal bump includes any one of solder paste printing and ball planting.

[0022] Optionally, there is a reserved space between the edge of the chip film and the edge of the supporting substrate, the size of the chip film is consistent with the chip to be packaged, and the packaging layer is formed on the chip to be packaged and extends to the reserved space.

[0023] A wafer-level chip packaging structure, wherein the packaging structure is preferably a structure obtained by packaging using the packaging method of the present invention, and the packaging structure comprises:

[0024] A chip to be packaged, wherein the chip to be packaged has a first surface and a second surface opposite to each other;

[0025] A die-attachment film is located on the first surface of the chip to be packaged, and the first surface is in contact with the die-attachment film;

[0026] A conductive column, formed on the second surface of the chip to be packaged and electrically connected to the chip to be packaged;

[0027] A packaging layer is formed on the second surface of the chip to be packaged and extends to the side of the chip to be packaged, and the top surface of the conductive column is exposed in the packaging layer, and the packaging layer and the die-mounting film cover the chip to be packaged;

[0028] a rewiring layer formed on the packaging layer, the rewiring layer being electrically connected to the conductive pillar; and

[0029] A metal bump is formed on a side of the rewiring layer away from the packaging layer, and the metal bump electrically leads the chip to be packaged through the rewiring layer and the conductive column.

[0030] Optionally, an adhesive protection layer is formed on the surface of the die attach film away from the chip to be packaged, and the adhesive protection layer and the packaging layer cover the die attach film and the chip to be packaged.

[0031] Optionally, the adhesion protection layer includes a polyimide layer.

[0032] Optionally, the metal bump includes one of tin solder, silver solder and gold-tin alloy solder.

[0033] Optionally, the packaging structure also includes a patterned surface layer, which is formed on a layer of the rewiring layer away from the packaging layer, and the patterned surface layer exposes a pad area on the rewiring layer where the metal bump is formed, and the metal bump is formed on the pad area via the patterned surface layer.

[0034] Optionally, there is a reserved space between the edge of the chip film and the edge of the supporting substrate, the size of the chip film is consistent with the chip to be packaged, and the packaging layer is formed on the chip to be packaged and extends to the reserved space.

[0035] As described above, the wafer-level chip packaging structure and packaging method of the present invention adopts a method of first performing patching (fixing the chip to be packaged) and then preparing the rewiring layer. In fan-out wafer-level packaging, it is beneficial to shorten the process, reduce the operation cycle, improve product yield, and reduce product costs. It has fewer processes, faster packaging speed, and higher output efficiency. The present invention also realizes effective six-sided packaging of wafer-level chips, better packaging chips, and improved product reliability. Metal bumps are formed by solder paste printing or ball planting to reduce the complexity of the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Shown is a process flow chart of the wafer-level chip packaging method of the present invention.

[0037] Figure 2 It shows a schematic structural diagram of providing a supporting substrate to form a temporary bonding layer in the wafer-level chip packaging method of the present invention.

[0038] Figure 3 It shows a schematic diagram of the structure of forming a die bonding film in the wafer-level chip packaging method of the present invention.

[0039] Figure 4 Shown is a schematic diagram of the structure of fixing the chip to be packaged in the wafer-level chip packaging method of the present invention.

[0040] Figure 5 It is a schematic structural diagram of forming conductive pillars in the wafer-level chip packaging method of the present invention.

[0041] Figure 6 It is a schematic diagram showing the structure of forming a packaging material layer in the wafer-level chip packaging method of the present invention.

[0042] Figure 7 It is a schematic diagram showing the structure of forming a packaging layer in the wafer-level chip packaging method of the present invention.

[0043] Figure 8 It is a schematic structural diagram of forming a rewiring layer in the wafer-level chip packaging method of the present invention.

[0044] Fig. 9 It is a schematic structural diagram of forming a patterned surface layer in the wafer-level chip packaging method of the present invention.

[0045] Fig.10 Shown is a schematic structural diagram of metal bumps formed in the wafer-level chip packaging method of the present invention.

[0046] Fig.11 It is a schematic diagram of the structure after the supporting substrate is separated in the wafer-level chip packaging method of the present invention.

[0047] Component number description

[0048] 100 Support substrate

[0049] 101 Temporary bonding layer

[0050] 102 Adhesion protective layer

[0051] 103 patch film

[0052] 104 Chips to be packaged

[0053] 105 Electrode area

[0054] 106 Conductive Column

[0055] 107 Packaging material layer

[0056] 108 Encapsulation Layer

[0057] 109 Rewiring Layer

[0058] 110 Graphical surface layer

[0059] 111 Pad area

[0060] 112 metal bumps

[0061] Steps S1 to S7 DETAILED DESCRIPTION

[0062] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0063] See also Figure 1-Figure 11 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0064] Embodiment 1:

[0065] like Figure 1 As shown, the present invention provides a wafer-level chip packaging method, the packaging method comprising the following steps:

[0066] Providing a supporting substrate, and forming a temporary bonding layer on the supporting substrate;

[0067] Providing a chip to be packaged and a die bonding film, forming the die bonding film on the temporary bonding layer, wherein the chip to be packaged has a first surface and a second surface opposite to each other, fixing the chip to be packaged on the die bonding film, and making the first surface of the chip to be packaged contact with the die bonding film;

[0068] Preparing a conductive column on the second surface of the chip to be packaged, wherein the conductive column is electrically connected to the chip to be packaged;

[0069] The chip to be packaged is packaged with a packaging layer, the top surface of the conductive pillar is exposed on the packaging layer, and the packaging layer and the chip mounting film cover the chip to be packaged;

[0070] Preparing a rewiring layer on the packaging layer, wherein the rewiring layer is electrically connected to the conductive pillar;

[0071] Preparing a metal bump on a side of the rewiring layer away from the packaging layer, so as to electrically lead out the chip to be packaged through the rewiring layer and the conductive pillar; and

[0072] The die attach film and the supporting substrate are peeled off based on the temporary bonding layer.

[0073] The wafer-level chip packaging method of the present invention will be described in detail below with reference to the accompanying drawings.

[0074] like Figure 1 S1 and Figure 2 As shown, a supporting substrate 100 is provided, and a temporary bonding layer 101 is formed on the supporting substrate.

[0075] As an example, the support substrate 100 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate. In one example, the light transmittance of the support substrate 100 is not less than 50%, so as to facilitate the subsequent separation of the support substrate based on the temporary bonding layer. In this embodiment, the support substrate 100 is selected as a glass substrate, which has a low cost, is easy to form a temporary bonding layer 101 on its surface, and can reduce the difficulty of the subsequent peeling process.

[0076] As an example, the temporary bonding layer 101 includes a light-to-heat conversion layer (LTHC), which is formed on the support substrate 100 by a spin coating process and then cured by a curing process. The light-to-heat conversion layer (LTHC) has stable performance and a relatively smooth surface, which is conducive to obtaining a flat surface in the subsequent peeling process, and the peeling difficulty is relatively low.

[0077] like Figure 1 S2 and Figure 3-4As shown, a chip to be packaged 104 and a die bonding film 103 are provided, and the die bonding film 103 is formed on the temporary bonding layer 101. The chip to be packaged has a first surface and a second surface relative to each other. The chip to be packaged 104 is fixed on the die bonding film 103, and the first surface of the chip to be packaged 104 is in contact with the die bonding film 103.

[0078] As an example, after forming the temporary bonding layer 101 , the method further includes the steps of: forming an adhesion protection layer 102 on the temporary bonding layer 101 , and forming the die attach film 103 on the surface of the adhesion protection layer 102 .

[0079] As an example, the adhesion protection layer 102 includes a polyimide layer.

[0080] Specifically, a die film 103 is provided in the present invention, and the die film 103 and the subsequently formed packaging layer 108 package the chip to be packaged 104, thereby realizing six-sided packaging of the chip. In one example, the die film 103 can be first formed on the temporary bonding layer 101, and then the chip to be packaged is formed on the die film, or the die film 103 can be first formed on the surface of the chip to be packaged, and then the two are formed on the temporary bonding layer. In one example, the die film 103 includes a DAF (die-attach film) film, which can include an epoxy resin film layer. In wafer-level packaging, the present invention sets a die film 103 on the surface of the wafer, so that the chip wafer-level six-sided packaging can be realized based on the die film 103, and the back of the chip can also be protected. In one example, the thickness of the patch film 103 (such as the DAF film) is between 10-40 microns, and can be 15 microns, 20 microns, 30 microns, 32 microns, 35 microns, etc. In one example, 32-40 microns is selected to facilitate six-sided packaging of the chip 104 to be packaged.

[0081] Specifically, in one example, the step of forming an adhesion protection layer 102 between the temporary bonding layer 101 and the chip film 103 is also included, wherein, optionally, the material of the adhesion protection layer 102 may be PI (polyimide), and the adhesion protection layer 102 may realize the adhesion of the chip 104 to be packaged, so that the chip 104 to be packaged can be better formed on the supporting substrate 100, and it is also convenient for the subsequent manufacturing process. At the same time, the adhesion protection layer 102 may also play the role of protecting the intermediate layer when the temporary bonding layer 101 is subsequently peeled off, such as protecting the chip film 103 from damage during separation.

[0082] As an example, there is a reserved space between the edge of the patch film 103 and the edge of the supporting substrate 100, the size of the patch film 103 is consistent with the chip to be packaged 104, and the packaging layer 108 is formed on the chip to be packaged 104 and extends to the reserved space.

[0083] Specifically, in this step, the chip to be packaged 104 is formed on the die bonding film 103 (die bonding), wherein the chip to be packaged 104 has a first surface and a second surface relative to each other, the first surface can be the back side of the chip, and the second surface can be the front side of the chip to be packaged 104. In one example, the chip to be packaged 104 also has an electrode region 105, and the electrode region 105 is arranged at the second surface to achieve electrical connection of the chip to be packaged 104. In this example, the chip to be packaged 104 is a wafer-level chip, and a plurality of chips can also be formed on the wafer for packaging.

[0084] Specifically, in one example, there is a reserved space between the edge of the patch film 103 and the edge of the supporting substrate 100, such as Figure 4 As shown, that is, after the patch film 103 is set on the supporting substrate 100 or the adhesive protective layer 102, it is exposed to the lower material layer contacted by the patch film 103, and the exposed part constitutes the reserved space. In an optional example, the center of the patch film 103 coincides with the center of the lower material layer, and each is symmetrical about the center, thereby forming a uniform and symmetrical reserved space. Optionally, when the first surface of the chip 104 to be packaged is in contact with the patch film 103, the two just completely overlap. Of course, it is also possible that the first surface does not completely occupy the surface of the patch film 103, and the area of ​​the patch film 103 is larger than the area of ​​the first surface. In this example, the chip 104 to be packaged, that is, the size and shape of the back of the wafer to be packaged is consistent with the patch film 103, which can be beneficial to improve the sealing effect and the stability of the six-sided package.

[0085] like Figure 1 S3 and Figure 5 As shown, a conductive pillar 106 is prepared on the second surface of the chip 104 to be packaged, and the conductive pillar 106 is electrically connected to the chip 104 to be packaged.

[0086] Specifically, a conductive column 106 is also prepared on the chip to be packaged 104, such as a conductive copper column. In one example, the conductive column 106 is prepared on the electrode area 105 to achieve electrical connection of the chip to be packaged 104. The preparation process of the conductive column 106 can adopt the preparation process of the conductive connection column commonly used in the art, such as the copper column preparation process.

[0087] like Figure 1 S4 and Figure 6-7 As shown, the chip to be packaged is packaged with a packaging layer 108 , the top surface of the conductive pillar 106 is exposed on the packaging layer 108 , and the packaging layer 108 and the die attach film 103 cover the chip to be packaged 104 .

[0088] Specifically, the method of encapsulating the chip 104 to be encapsulated by the encapsulation layer 108 includes one of compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating, and the material of the encapsulation layer 108 includes one of polyimide, silica gel and epoxy resin. The encapsulation material layer 107 may be formed on the structure to be encapsulated first, and then the step of thinning the material layer of the encapsulation layer 108 is included to expose the conductive pillar 106 on the encapsulation layer 108.

[0089] Specifically, in one example, the packaging layer 108 after packaging is in an inverted U-shaped structure on the chip to be packaged 104, preferably a symmetrical structure. Optionally, when the chip film 103 is the same size as the chip to be packaged 104, one surface of the packaging layer 108 is in contact with the supporting base 100 or the adhesion protective layer 102 (when present), and the side of the chip film 103 and the chip to be packaged 104 are packaged together at the same time, which can help improve the stability of the packaging structure and improve the packaging effect.

[0090] like Figure 1 S5 and Figure 8 As shown, a rewiring layer 109 is prepared on the packaging layer 108 , and the rewiring layer 109 is electrically connected to the conductive pillars 106 .

[0091] As an example, the steps of preparing the rewiring layer 109 include: forming a dielectric layer and a metal stack structure on the upper surface of the packaging layer 108, the metal stack structure is electrically connected to the conductive column 106 to electrically lead out the chip to be packaged 104, wherein the metal stack structure is located in the dielectric layer, the metal stack structure includes a plurality of layers of metal wire layers and metal plugs arranged at intervals, and the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers.

[0092] Specifically, in this step, a rewiring layer 109 is prepared on the packaging layer 108, and the rewiring layer 109 is electrically connected to the conductive pillars 106 to achieve electrical connection with the chip to be packaged 104. In the present invention, the die is first mounted and then the rewiring layer 109 is packaged. That is to say, the present invention first mounts the die (first mounts the chip to be packaged 104), and then prepares the rewiring layer 109 (RDL). This type of fan-out packaging (Fan-out wafer level package) can be beneficial in shortening the process, reducing the operation cycle (cycle time), improving the product yield (throughput), and reducing the product cost (cost) in the fan-out packaging field.

[0093] In addition, the rewiring layer 109 may include several dielectric layers and several metal wire layers arranged according to graphic requirements, and two adjacent metal wire layers are connected by metal plugs. The material of the dielectric layer may be one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass, and fluorine-containing glass. In this embodiment, the material of the dielectric layer may be PI (polyimide) to further reduce the process difficulty and process cost. The material of the metal wire layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. In this embodiment, the material of the metal wire layer is copper, and the metal plug material is copper.

[0094] like Figure 1 S6 and Figure 9-10 As shown, a metal bump 112 is prepared on a side of the rewiring layer 109 away from the packaging layer 108 , so as to electrically lead out the chip 104 to be packaged through the rewiring layer 109 and the conductive pillars 106 .

[0095] As an example, the metal bump 112 includes one of tin solder, silver solder and gold-tin alloy solder.

[0096] As an example, the steps of forming the metal bump 112 include:

[0097] Preparing a patterned surface layer 110 on the rewiring layer 109, wherein the patterned surface layer 110 exposes a pad area 111 on the rewiring layer 109 where the metal bump 112 is to be formed; and

[0098] The metal bump 112 is formed on the pad area 111 based on the patterned surface layer 110 , and the metal bump 112 is formed by any one of solder paste printing and ball planting.

[0099] Specifically, a metal bump 112 is prepared on the other side of the rewiring layer 109, and the metal bump 112 is electrically connected to the metal wire layer in the rewiring layer 109 by solder paste printing reflow soldering or ball planting. This method is simple and has simple process complexity. In addition, in one example, a patterned surface layer 110 is formed on the rewiring layer 109 before forming the metal bump 112. In one example, the material of the patterned surface layer 110 may be PI, wherein a layer of PI material layer may be first formed on the rewiring layer 109 and then patterned so that the material layer reveals the metal area on the rewiring layer 109 where a solder pad needs to be prepared, i.e., the solder pad area, while other areas are covered to form the patterned surface layer 110, thereby further protecting the packaging structure and improving the reliability of the packaging. In an optional example, the upper surface of the patterned surface layer 110 is higher than the upper surface of the rewiring layer 109, which is beneficial to the subsequent preparation and implementation of the metal bump 112, improving the reliability of the metal bump 112, and improving the electrical stability of the overall packaging structure.

[0100] like Figure 1 S7 and Fig.11 As shown, the die attach film 103 and the supporting substrate are peeled off based on the temporary bonding layer 101 .

[0101] As an example, the temporary bonding layer 101 includes a light-to-heat conversion layer, wherein the light-to-heat conversion layer is irradiated with a laser to separate the light-to-heat conversion layer from the chip film 103 and the supporting substrate 100 , thereby peeling off the chip film 103 and the supporting substrate 100 .

[0102] Specifically, the temporary bonding layer 101 is a light-to-heat conversion layer, and the light-to-heat conversion layer is irradiated with a laser to separate the light-to-heat conversion layer from the packaging layer 108, the chip to be packaged 104, and the supporting substrate 100. Alternatively, in one example, the adhesive protective layer 102 is separated from the supporting substrate 100, and then the chip to be packaged 104 and the supporting substrate 100 are peeled off, thereby obtaining a packaging structure. In addition, the supporting substrate 100 of the present invention, such as a glass substrate (glass wafer), can be reused as a temporary carrier in the process, which is conducive to reducing the cost of the product.

[0103] Embodiment 2:

[0104] like Fig.11 As shown, and refer to Figure 1-10 The present invention further provides a wafer-level chip packaging structure, wherein the packaging structure is preferably obtained by packaging using the packaging method of the present invention, and the packaging structure comprises:

[0105] A chip to be packaged 104, wherein the chip to be packaged 104 has a first surface and a second surface opposite to each other;

[0106] A die attach film 103 is located on the first surface of the chip to be packaged 104, and the first surface is in contact with the die attach film 103;

[0107] A conductive column 106 is formed on the second surface of the chip to be packaged 104 and is electrically connected to the chip to be packaged 104;

[0108] The packaging layer 108 is formed on the second surface of the chip to be packaged 104 and extends to the side of the chip to be packaged 104, and the top surface of the conductive pillar 106 is exposed in the packaging layer 108, and the packaging layer 108 and the die-attachment film 103 cover the chip to be packaged 104;

[0109] a rewiring layer 109 formed on the packaging layer 108, wherein the rewiring layer 109 is electrically connected to the conductive pillar 106; and

[0110] The metal bump 112 is formed on a side of the rewiring layer 109 away from the packaging layer 108 . The metal bump 112 is used to electrically lead out the chip 104 to be packaged through the rewiring layer 109 and the conductive pillar 106 .

[0111] Specifically, in the present invention, a die-attach film 103 is provided, and the die-attach film 103 and the subsequently formed encapsulation layer 108 encapsulate the chip 104 to be encapsulated, thereby realizing the six-sided encapsulation of the chip. In one example, the die-attach film 103 includes a DAF (die-attach film) film layer, and a resin material die-attach film 103 can be used, including an epoxy resin film. In wafer-level encapsulation, the present invention sets a die-attach film 103 on the surface of the wafer, so that the six-sided encapsulation of the chip wafer level can be realized based on the die-attach film 103, and the back of the chip can also be protected. In one example, the thickness of the die-attach film 103 (such as the DAF film) is between 10-40 microns, and can be 15 microns, 20 microns, 30 microns, 32 microns, 35 microns, etc. In one example, 32-40 microns are selected to facilitate the six-sided encapsulation of the chip 104 to be encapsulated.

[0112] As an example, an adhesive protection layer 102 is formed on the surface of the die attach film 103 away from the chip to be packaged 104 , and the adhesive protection layer 102 and the packaging layer 108 cover the die attach film 103 and the chip to be packaged 104 .

[0113] As an example, the adhesion protection layer 102 includes a polyimide layer.

[0114] Specifically, in one example, an adhesion protection layer 102 is formed between the temporary bonding layer 101 and the chip film 103, wherein, optionally, the material of the adhesion protection layer 102 may be PI (polyimide), and the adhesion protection layer 102 may enable the adhesion of the chip 104 to be packaged, so that the chip 104 to be packaged can be better formed on the supporting substrate 100, and it is also convenient for the subsequent manufacturing process. At the same time, the adhesion protection layer 102 may also play the role of protecting the intermediate layer when the temporary bonding layer 101 is subsequently peeled off, such as protecting the chip film 103 from damage during separation.

[0115] As an example, the packaging structure also includes a patterned surface layer 110, which is formed on a layer of the rewiring layer 109 away from the packaging layer 108, and the patterned surface layer 110 exposes a pad area 111 on the rewiring layer 109 where the metal bump 112 is formed, and the metal bump 112 is formed on the pad area 111 via the patterned surface layer 110.

[0116] As an example, the metal bump 112 includes one of tin solder, silver solder and gold-tin alloy solder.

[0117] Specifically, the conductive pillar 106 may be a conductive copper pillar, and the conductive pillar 106 is prepared on the electrode region 105 to achieve electrical connection of the chip 104 to be packaged. The material of the packaging layer 108 includes one of polyimide, silica gel and epoxy resin. The packaging material layer 107 may be formed on the structure to be packaged first. Specifically, in one example, the packaging layer 108 after packaging is in an inverted U-shaped structure on the chip 104 to be packaged, preferably a symmetrical structure. Optionally, when the chip film 103 is the same size as the chip 104 to be packaged, one surface of the packaging layer 108 is in contact with the supporting substrate 100 or the adhesive protective layer 102 (when present), and the chip film 103 and the side of the chip 104 to be packaged are packaged together at the same time, which can help improve the stability of the packaging structure and improve the packaging effect.

[0118] Specifically, in one example, the rewiring layer 109 includes a dielectric layer and a metal stacking structure, the metal stacking structure is electrically connected to the conductive pillar 106 to electrically lead out the chip to be packaged 104, wherein the metal stacking structure is located in the dielectric layer, and the metal stacking structure includes a plurality of metal wire layers and metal plugs arranged at intervals, and the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers. Further, the conductive pillar 106 is electrically connected to the metal layer. The rewiring layer 109 may include a plurality of dielectric layers and a plurality of metal wire layers arranged according to graphic requirements, and two adjacent metal wire layers are connected by metal plugs. The material of the dielectric layer may be one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass, and fluorine-containing glass. In this embodiment, the material of the dielectric layer may be PI (polyimide) to further reduce the process difficulty and process cost. The material of the metal wire layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. In this embodiment, the material of the metal wire layer is copper, and the material of the metal plug is copper.

[0119] In addition, in one example, the packaging structure also includes forming a patterned surface layer 110, and the material of the patterned surface layer 110 can be PI, wherein a layer of PI material layer can be first formed on the rewiring layer 109, and then patterned so that the material layer reveals the metal area on the rewiring layer 109 where the solder pad needs to be prepared, that is, the solder pad area, and covers other areas to form the patterned surface layer 110, which further protects the packaging structure and improves the reliability of the package. In an optional example, the upper surface of the patterned surface layer 110 is higher than the upper surface of the rewiring layer 109, which is beneficial to the subsequent preparation and implementation of the metal bump 112, improves the reliability of the metal bump 112, and improves the electrical stability of the overall packaging structure.

[0120] As an example, there is a reserved space between the edge of the patch film 103 and the edge of the supporting substrate 100, the size of the patch film 103 is consistent with the chip to be packaged 104, and the packaging layer 108 is formed on the chip to be packaged 104 and extends to the reserved space.

[0121] Specifically, the chip to be packaged 104 has a first surface and a second surface relative to each other, the first surface may be the back side of the chip, and the second surface may be the front side of the chip to be packaged 104. In one example, the chip to be packaged 104 further has an electrode region 105, and the electrode region 105 is disposed at the second surface to achieve electrical connection of the chip to be packaged 104. In this example, the chip to be packaged 104 is a wafer-level chip, and a plurality of chips may be formed on the wafer for packaging.

[0122] Specifically, in one example, there is a reserved space between the edge of the patch film 103 and the edge of the supporting substrate 100, such as Figure 4 As shown, that is, after the patch film 103 is set on the supporting substrate 100 or the adhesive protective layer 102, it is exposed to the lower material layer contacted by the patch film 103, and the exposed part constitutes the reserved space. In an optional example, the center of the patch film 103 coincides with the center of the lower material layer, and each is symmetrical about the center, thereby forming a uniform and symmetrical reserved space. Optionally, when the first surface of the chip 104 to be packaged is in contact with the patch film 103, the two just completely overlap. Of course, it is also possible that the first surface does not completely occupy the surface of the patch film 103, and the area of ​​the patch film 103 is larger than the area of ​​the first surface. In this example, the chip 104 to be packaged, that is, the size and shape of the back of the wafer to be packaged is consistent with the patch film 103, which can be beneficial to improve the sealing effect and the stability of the six-sided package.

[0123] In summary, the present invention provides a wafer-level packaging structure and a packaging method, the packaging method comprising: providing a supporting substrate and forming a temporary bonding layer on the supporting substrate; forming a die bonding film on the temporary bonding layer; providing a chip to be packaged, the chip to be packaged having a first surface and a second surface relative to each other, fixing the chip to be packaged on the die bonding film, and making the first surface of the chip to be packaged contact the die bonding film; preparing a conductive column on the second surface of the chip to be packaged, the conductive column being electrically connected to the chip to be packaged; using a packaging layer to package the chip to be packaged, the top surface of the conductive column being exposed to the packaging layer, the packaging layer and the die bonding film covering the chip to be packaged; preparing a rewiring layer on the packaging layer, the rewiring layer being electrically connected to the conductive column; preparing a metal bump on a side of the rewiring layer away from the packaging layer, so as to realize the electrical lead-out of the chip to be packaged through the rewiring layer and the conductive column; and peeling off the die bonding film and the supporting substrate based on the temporary bonding layer. Through the above scheme, the present invention adopts the method of first performing patching and then preparing the rewiring layer, which is beneficial to shortening the process, reducing the operation cycle, improving the product yield, and reducing the product cost in the fan-out wafer-level packaging, realizing effective six-sided packaging of wafer-level chips, better packaging chips, improving product reliability, and using solder paste printing or ball planting to form metal bumps to reduce the complexity of the process. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0124] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A wafer-level chip packaging method, characterized in that: The packaging method comprises the following steps: Providing a supporting substrate, and forming a temporary bonding layer on the supporting substrate; Providing a chip to be packaged and a die bonding film, forming the die bonding film on the temporary bonding layer, wherein the chip to be packaged has a first surface and a second surface opposite to each other, the chip to be packaged is fixed on the die bonding film, and the first surface of the chip to be packaged is in contact with the die bonding film; Preparing a conductive column on the second surface of the chip to be packaged, wherein the conductive column is electrically connected to the chip to be packaged; The chip to be packaged is packaged with a packaging layer, the top surface of the conductive pillar is exposed on the packaging layer, and the packaging layer and the chip mounting film cover the chip to be packaged; A rewiring layer is prepared on the packaging layer, wherein the rewiring layer is electrically connected to the conductive pillars, and the chip to be packaged is firstly mounted, and then the rewiring layer is prepared; Preparing a metal bump on a side of the rewiring layer away from the packaging layer, so as to electrically lead out the chip to be packaged through the rewiring layer and the conductive pillar; and peeling off the die attach film and the supporting substrate based on the temporary bonding layer; After forming the temporary bonding layer, the method further includes forming an adhesion protection layer on the temporary bonding layer, and forming the die attach film on the surface of the adhesion protection layer.

2. The wafer-level chip packaging method according to claim 1, characterized in that: The adhesion protection layer includes a polyimide layer.

3. The wafer-level chip packaging method according to claim 1, characterized in that: The step of preparing the rewiring layer includes: forming a dielectric layer and a metal stack structure on the upper surface of the packaging layer, the metal stack structure is electrically connected to the conductive column to electrically lead out the chip to be packaged, wherein the metal stack structure is located in the dielectric layer, the metal stack structure includes a plurality of layers of metal wire layers and metal plugs arranged at intervals, and the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers.

4. The wafer-level chip packaging method according to claim 1, characterized in that: The metal bump includes one of tin solder, silver solder and gold-tin alloy solder.

5. The wafer-level chip packaging method according to claim 1, characterized in that: The temporary bonding layer includes a light-to-heat conversion layer, wherein the light-to-heat conversion layer is irradiated with laser to separate the light-to-heat conversion layer from the die attach film and the supporting substrate, thereby peeling off the die attach film and the supporting substrate.

6. The wafer-level chip packaging method according to claim 1, characterized in that: The steps of forming the metal bumps include: Preparing a patterned surface layer on the rewiring layer, wherein the patterned surface layer exposes a pad area on the rewiring layer where the metal bump is to be formed; and The metal bump is formed on the pad area based on the patterned surface layer, and the formation of the metal bump includes any one of solder paste printing and ball planting.

7. The wafer-level chip packaging method according to any one of claims 1 to 6, characterized in that: There is a reserved space between the edge of the chip patch film and the edge of the supporting substrate. The size of the chip patch film is consistent with the chip to be packaged. The packaging layer is formed on the chip to be packaged and extends to the reserved space.

8. A wafer-level chip packaging structure, characterized in that: The packaging structure comprises: A chip to be packaged, wherein the chip to be packaged has a first surface and a second surface opposite to each other; A die-attachment film is located on the first surface of the chip to be packaged, and the first surface is in contact with the die-attachment film; An adhesive protection layer is formed on the surface of the die-attachment film away from the chip to be packaged; A conductive column, formed on the second surface of the chip to be packaged and electrically connected to the chip to be packaged; A packaging layer is formed on the second surface of the chip to be packaged and extends to the side of the chip to be packaged, and the top surface of the conductive column is exposed in the packaging layer, and the packaging layer and the die-mounting film cover the chip to be packaged; A rewiring layer is formed on the packaging layer, the rewiring layer is electrically connected to the conductive pillars, and the chip to be packaged is firstly mounted, and then the rewiring layer is prepared; and A metal bump is formed on a side of the rewiring layer away from the packaging layer, and the metal bump electrically leads the chip to be packaged through the rewiring layer and the conductive column.

9. The wafer-level chip packaging structure according to claim 8, characterized in that: The adhesive protection layer and the packaging layer cover the die attach film and the chip to be packaged.

10. The wafer-level chip packaging structure according to claim 9, characterized in that: The adhesion protection layer includes a polyimide layer.

11. The wafer-level chip packaging structure according to claim 8, characterized in that: The metal bump includes one of tin solder, silver solder and gold-tin alloy solder.

12. The wafer-level chip packaging structure according to claim 8, characterized in that: The packaging structure also includes a patterned surface layer, which is formed on a layer of the rewiring layer away from the packaging layer, and the patterned surface layer exposes the pad area of ​​the metal bump formed on the rewiring layer, and the metal bump is formed on the pad area through the patterned surface layer.

13. The wafer-level chip packaging structure according to any one of claims 8 to 12, characterized in that: There is a reserved space between the edge of the patch film and the edge of the supporting substrate. The size of the patch film is consistent with the chip to be packaged. The packaging layer is formed on the chip to be packaged and extends to the reserved space.

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