Heat dissipation structure and preparation method thereof, chip packaging structure and chip packaging method

Abstract

The present invention provides a heat dissipation structure and a preparation method thereof, a chip packaging structure and a chip packaging method, wherein the heat dissipation structure comprises: a first plate layer and a second plate layer arranged opposite to each other; the first plate layer has a first microchannel, a coolant inlet and a coolant outlet, the first microchannel faces the second plate layer, the coolant inlet and the coolant outlet face away from the second plate layer, and the coolant inlet and the coolant outlet are connected to the first microchannel; the second plate layer comprises a first area and a second area adjacent to each other, the distance from the surface of the second area facing away from the first plate layer to the first plate layer is smaller than the distance from the surface of the first area facing away from the first plate layer to the first plate layer, the first area and the second area are provided with a second microchannel, and the second microchannel is connected to the first microchannel. The heat dissipation structure can meet the heat dissipation requirements of a multi-chip integrated structure with chips of different thicknesses, and when the heat dissipation structure is used for heat dissipation, the coolant delivery channel is simple.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a heat dissipation structure and a preparation method thereof, a chip packaging structure and a chip packaging method. Background Art

[0002] Nowadays, electronic devices are rapidly developing towards high integration, high assembly density and high operating speed. As the core of electronic devices, electronic chips have been increasing in integration, packaging density and working clock frequency, while their volume is shrinking. Therefore, the heat generated per unit area of ​​electronic chips is increasing, especially for high-power electronic devices. The increasing heat generated per unit area of ​​electronic chips can easily cause a sharp increase in the junction temperature, and the high junction temperature will have an adverse effect on the performance of electronic chips and electronic devices. According to statistics, 55% of electronic equipment failures are caused by excessively high junction temperatures, and studies have shown that for every 10°C increase in the junction temperature of a single electronic chip, the reliability of the electronic device will decrease by 50%. It can be seen that the heat dissipation problem of chips has become a key factor in the normal operation of electronic devices.

[0003] Microfluidics is a better heat dissipation technology. The microfluidic structure is a plate layer with a channel with two openings at both ends. The purpose of heat dissipation of the device is achieved by mounting the microfluidic structure on the surface of the chip and allowing the coolant to flow in from one opening, absorbing the heat near the device and then flowing out from the other opening. Microfluidic heat dissipation is an effective heat dissipation method because of its advantages such as high surface area / volume ratio, low thermal resistance, and low flow rate. Usually, the microfluidic channel used to transport the heat dissipation coolant is set above the main working area of ​​the electronic chip to meet the needs of small electronic equipment.

[0004] However, when the multi-chip integrated structure includes chips of different thicknesses, it is impossible to meet the heat dissipation requirement of the multi-chip integrated structure by mounting the above-mentioned micro-channel structure. Summary of the invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the defect that the existing microchannel structure cannot meet the heat dissipation requirements of a multi-chip integrated structure with chips of different thicknesses, thereby providing a heat dissipation structure and its preparation method, a chip packaging structure and a chip packaging method.

[0006] The present invention provides a heat dissipation structure, comprising:

[0007] A first plate layer and a second plate layer arranged opposite to each other;

[0008] The first plate layer has a first microchannel, and the first microchannel faces the second plate layer;

[0009] The second plate layer includes an adjacent first zone and a second zone, an arrangement direction from the first zone to the second zone is parallel to an extension surface of the second plate layer, a distance from a surface of the second zone facing away from the first plate layer to the first plate layer is smaller than a distance from a surface of the first zone facing away from the first plate layer to the first plate layer, and a second microfluidic channel is arranged in the first zone and the second zone, and the second microfluidic channel is connected to the first microfluidic channel.

[0010] Optionally, the surface of the first board layer facing the second board layer is planar, the surface of the second board layer facing the first board layer is planar, and the surface of the first board layer facing the second board layer is parallel to the surface of the second board layer facing the first board layer.

[0011] Optionally, a depth of the second microfluidic channel located in the first zone is greater than a depth of the second microfluidic channel located in the second zone.

[0012] Optionally, a difference between a depth of the second microchannel located in the first zone and a depth of the second microchannel located in the second zone is 50 μm-700 μm.

[0013] Optionally, the heat dissipation structure also includes: a coolant inlet and a coolant outlet located in the first plate layer, the coolant inlet and the coolant outlet are located on the side of the first plate layer facing away from the second plate layer, and the coolant inlet and the coolant outlet are connected to the first microchannel.

[0014] Optionally, the orthographic projection of the coolant inlet on the second plate layer is located in the first zone, and the orthographic projection of the coolant outlet on the second plate layer is located in the second zone; or, the orthographic projection of the coolant outlet on the second plate layer is located in the first zone, and the orthographic projection of the coolant inlet on the second plate layer is located in the second zone.

[0015] Optionally, the heat dissipation structure also includes: a connector located between the first board layer and the second board layer, the connector including a connected first bonding layer and a second bonding layer; the surface of the first bonding layer facing away from the second bonding layer is connected to the first board layer; and the surface of the second bonding layer facing away from the first bonding layer is connected to the second board layer.

[0016] Optionally, the first bonding layer is disposed around a port of the first microfluidic channel; and the second bonding layer is disposed around a port of the second microfluidic channel.

[0017] Optionally, the shape of the orthographic projection of the second microfluidic channel on the first plate layer is a serpentine, and the shape of the orthographic projection of the first microfluidic channel on the second plate layer is a serpentine; or, the shape of the orthographic projection of the second microfluidic channel on the first plate layer is a half-circle shape, and the shape of the orthographic projection of the first microfluidic channel on the second plate layer is a half-circle shape; or, the shape of the orthographic projection of the second microfluidic channel on the first plate layer is a grid shape, and the shape of the orthographic projection of the first microfluidic channel on the second plate layer is a grid shape.

[0018] The present invention also provides a chip packaging structure, comprising:

[0019] The above heat dissipation structure;

[0020] A first chip, wherein the back side of the first chip is arranged on a side of the first region away from the first board layer;

[0021] A second chip, wherein the back side of the second chip is arranged on a side of the second region away from the first board layer, and the thickness of the second chip is greater than that of the first chip.

[0022] Optionally, the chip packaging structure further includes: an encapsulation layer, the encapsulation layer is arranged on a side of the second board layer away from the first board layer, the encapsulation layer wraps the first chip and the second chip and exposes the front side of the first chip and the front side of the second chip;

[0023] A rewiring structure is provided on a surface of the encapsulation layer facing away from the second board layer, the front side of the first chip is connected to the rewiring structure, and the front side of the second chip is connected to the rewiring structure.

[0024] The present invention also provides a method for preparing a heat dissipation structure, comprising the following steps:

[0025] Providing a first board layer and a second board layer, wherein the second board layer comprises a first area and a second area adjacent to each other, and an arrangement direction from the first area to the second area is parallel to an extension surface of the second board layer;

[0026] Disposing a first microfluidic channel in a partial thickness of the first plate layer;

[0027] forming a second microfluidic channel in the first and second regions of the partial thickness;

[0028] The first plate layer and the second plate layer are arranged opposite to each other and bonded together, and the second microfluidic channel is connected to the first microfluidic channel;

[0029] The surface of the second region of the second board layer which is away from the first board layer is thinned so that the thickness of the second region is smaller than the thickness of the first region.

[0030] Optionally, the method for preparing the heat dissipation structure further includes:

[0031] A coolant inlet and a coolant outlet are arranged in the first plate layer of partial thickness, and the coolant inlet and the coolant outlet are connected to the first microchannel; after the first plate layer and the second plate layer are arranged opposite to each other and bonded together, the coolant inlet and the coolant outlet are located on the side of the first plate layer facing away from the second plate layer.

[0032] Optionally, the method for preparing the heat dissipation structure also includes: setting a first bonding layer on one side surface of the first board layer; after forming the first microchannel, the first bonding layer is set around the port of the first microchannel; setting a second bonding layer on one side surface of the first area and the second area, and after forming the second microchannel, the second bonding layer is set around the port of the second microchannel; bonding the first board layer and the second board layer together includes: bonding the first bonding layer to the second bonding layer.

[0033] The present invention also provides a chip packaging method, comprising the following steps:

[0034] Providing the above heat dissipation structure of a first chip and a second chip, wherein the thickness of the second chip is greater than the thickness of the first chip;

[0035] Disposing the back side of the first chip on a surface of the first region facing away from the first board layer;

[0036] The back side of the second chip is arranged on a surface of the second region facing away from the first board layer.

[0037] Optionally, the chip packaging method also includes: forming an encapsulation layer on the side surface of the second board layer facing away from the first board layer, the encapsulation layer wraps the first chip and the second chip and exposes the front side of the first chip and the front side of the second chip; forming a rewiring structure on the side surface of the encapsulation layer facing away from the second board layer, the front side of the first chip and the front side of the second chip, the front side of the first chip is connected to the rewiring structure, and the front side of the second chip is connected to the rewiring structure.

[0038] The technical solution of the present invention has the following advantages:

[0039] 1. The heat dissipation structure provided by the present invention comprises a first plate layer and a second plate layer arranged opposite to each other; the first plate layer has a first microchannel, the first microchannel faces the second plate layer, the second plate layer comprises a first area and a second area adjacent to each other, the arrangement direction from the first area to the second area is parallel to the extension surface of the second plate layer, the first area and the second area are provided with a second microchannel, the second microchannel is connected with the first microchannel to form a microchannel structure; the distance from the surface of the second area facing away from the first plate layer to the first plate layer is smaller than the distance from the surface of the first area facing away from the first plate layer to the first plate layer, so that the first area is suitable for connecting chips with smaller thickness, and the second area is suitable for connecting chips with larger thickness; during the heat dissipation process, the coolant flows in the microchannel structure and absorbs the heat generated by chips of different thicknesses, so that chips of different thicknesses can effectively dissipate heat, that is, the heat dissipation structure can meet the heat dissipation requirements of a multi-chip integrated structure with chips of different thicknesses.

[0040] 2. In the heat dissipation structure provided by the present invention, the depth of the second microchannel located in the first zone is greater than the depth of the second microchannel located in the second zone, and the distance between the coolant flowing in the second microchannel in the first zone and the first chip is smaller, thereby improving the heat dissipation effect of the first zone, that is, improving the heat dissipation effect of the heat dissipation structure, and avoiding the adverse effect of heat accumulation in the multi-chip packaging structure on chip performance.

[0041] 3. The heat dissipation structure provided by the present invention further includes a coolant inlet and a coolant outlet located in the first plate layer, the coolant inlet and the coolant outlet are located on the side of the first plate layer facing away from the second plate layer, and the coolant inlet and the coolant outlet are connected to the first microchannel. The coolant enters the microchannel structure from the coolant inlet, and flows out from the coolant outlet after absorbing the heat generated by chips of different thicknesses, that is, the above heat dissipation structure only needs to be provided with one set of coolant inlet and coolant outlet to meet the use requirements, making the coolant delivery structure simpler.

[0042] 4. In the heat dissipation structure provided by the present invention, the orthographic projection of the coolant inlet on the second plate layer is located in the first zone, and the orthographic projection of the coolant outlet on the second plate layer is located in the second zone; or, the orthographic projection of the coolant outlet on the second plate layer is located in the first zone, and the orthographic projection of the coolant inlet on the second plate layer is located in the second zone. The above arrangement is beneficial to the circulation effect of the coolant in the first zone and the second zone, thereby facilitating the heat dissipation efficiency of the first chip and the second chip.

[0043] 5. The heat dissipation structure provided by the present invention further includes a connector located between the first plate layer and the second plate layer, the connector includes a first bonding layer and a second bonding layer connected; the surface of the first bonding layer facing away from the second bonding layer is connected to the first plate layer; the surface of the second bonding layer facing away from the first bonding layer is connected to the second plate layer. The connection between the first plate layer and the second plate layer is achieved through the connector, so that the first microchannel is connected to the second microchannel to form a microchannel structure, which can be used for heat dissipation in a multi-chip packaging structure.

[0044] 6. In the heat dissipation structure provided by the present invention, the first bonding layer is arranged around the port of the first microchannel; the second bonding layer is arranged around the port of the second microchannel to seal the microchannel structure so that the microchannel structure forms a sealing area to prevent the coolant from losing from the connecting piece.

[0045] 7. The chip packaging structure provided by the present invention includes a heat dissipation structure, a first chip and a second chip. The back side of the first chip is arranged on the side of the first area away from the first board layer, and the back side of the second chip is arranged on the side of the second area away from the first board layer. The thickness of the second chip is greater than the thickness of the first chip, which can meet the heat dissipation requirements of a multi-chip integrated structure with chips of different thicknesses.

[0046] 8. The preparation method of the heat dissipation structure provided by the present invention is achieved by setting a first microchannel in the first board layer of partial thickness, and forming a second microchannel in the first zone and the second zone of partial thickness; then the first board layer and the second board layer are arranged relative to each other and bonded together, and the second microchannel is connected to the first microchannel; finally, the surface of the second zone of the second board layer away from the first board layer is thinned to make the thickness of the first zone greater than the thickness of the second zone. The prepared heat dissipation structure is suitable for heat dissipation of a multi-chip integrated structure with chips of different thicknesses, and the preparation method is simple.

[0047] 9. The chip packaging method provided by the present invention can meet the heat dissipation requirements of a multi-chip integrated structure with chips of different thicknesses by setting the back side of the first chip on the side surface of the first area away from the first board layer, and setting the back side of the second chip on the side surface of the second area away from the first board layer, and the packaging method is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 It is a structural schematic diagram of a chip packaging structure;

[0050] Figure 2 is a schematic structural diagram of a heat dissipation structure in an embodiment of the present invention;

[0051] Figure 3 is a cross-sectional view of the first type of first board layer in an embodiment of the present invention;

[0052] Figure 4 is a cross-sectional view of the second first board layer in an embodiment of the present invention;

[0053] Figure 5 is a cross-sectional view of the third first board layer in an embodiment of the present invention;

[0054] Figure 6 is a schematic structural diagram of a chip packaging structure in an embodiment of the present invention;

[0055] Figure 7 is a process flow chart of a method for preparing a heat dissipation structure in an embodiment of the present invention;

[0056] Figure 8-Figure 15 A schematic diagram of the structure during the preparation of the heat dissipation structure in an embodiment of the present invention;

[0057] Fig.16 is a process flow chart of a chip packaging method in an embodiment of the present invention;

[0058] Figure 17-Figure 21 It is a structural schematic diagram of a chip packaging method in an embodiment of the present invention. DETAILED DESCRIPTION

[0059] See also Figure 1A chip packaging structure includes a heat dissipation structure and a chip 4'. The heat dissipation structure includes a first plate layer 1' and a second plate layer 2', the surfaces of the first plate layer 1' and the second plate layer 2' are both planes; the first plate layer 1' has a first microchannel 11', a coolant inlet 12' and a coolant outlet 13', the first microchannel 11' faces the second plate layer 2', the coolant inlet 12' and the coolant outlet 13' are away from the second plate layer 2', and the coolant inlet 12' and the coolant outlet 13' are connected to the first microchannel 11'; the second plate layer 2' is provided with a second microchannel 23', and the second microchannel 23' is connected to the first microchannel 11'; the second plate layer 2 is mounted on the back of the chip 4' on the side away from the first plate layer 1.

[0060] However, the above chip packaging structure is only applicable to a multi-chip integrated structure or a single chip with chips of a single thickness; when the multi-chip packaging structure has chips of different thicknesses, the heat dissipation structure in the chip packaging structure cannot be simultaneously mounted on the surfaces of chips with different thicknesses, thereby making it impossible for each chip to dissipate heat at the same time, that is, the above chip packaging structure cannot meet the heat dissipation requirements of a multi-chip integrated structure with chips of different thicknesses.

[0061] The present invention provides a heat dissipation structure, comprising a first plate layer and a second plate layer arranged opposite to each other; the first plate layer has a first microchannel, and the first microchannel faces the second plate layer; the second plate layer comprises a first area and a second area adjacent to each other, the arrangement direction from the first area to the second area is parallel to the extension surface of the second plate layer, the distance from the surface of the second area facing away from the first plate layer to the first plate layer is smaller than the distance from the surface of the first area facing away from the first plate layer to the first plate layer, the first area and the second area are provided with a second microchannel, and the second microchannel is connected to the first microchannel. The heat dissipation structure can meet the heat dissipation requirements of a multi-chip integrated structure with chips of different thicknesses.

[0062] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limitations on the present invention.

[0064] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0065] See also Figure 2 The present embodiment provides a heat dissipation structure, comprising a first board layer 1 and a second board layer 2 arranged opposite to each other; the first board layer 1 has a first microchannel 11, and the first microchannel 11 faces the second board layer 2; the second board layer 2 includes adjacent first areas 21 and second areas 22, and the arrangement direction from the first areas 21 to the second areas 22 is parallel to the extension surface of the second board layer 2, and the distance from the surface of the second area 22 facing away from the first board layer 1 to the first board layer 1 is smaller than the distance from the surface of the first area 21 facing away from the first board layer 1 to the first board layer 1, and second microchannels 23 are arranged in the first areas 21 and the second areas 22, and the second microchannels 23 are connected to the first microchannel 11.

[0066] In the above-mentioned heat dissipation structure, the second microchannel 23 is connected to the first microchannel 11 to form a microchannel structure; the distance from the surface of the second area 22 facing away from the first board layer 1 to the first board layer 1 is smaller than the distance from the surface of the first area 21 facing away from the first board layer 1 to the first board layer 1, so that the first area 21 is suitable for connecting chips with smaller thickness, and the second area 22 is suitable for connecting chips with larger thickness; during the heat dissipation process, the coolant flows in the microchannel structure and absorbs the heat generated by chips of different thicknesses, so that chips of different thicknesses can effectively dissipate heat, that is, the heat dissipation structure can meet the heat dissipation requirements of a multi-chip integrated structure with chips of different thicknesses.

[0067] It should be understood that the number of the first area 21 in the second board layer 2 includes but is not limited to 1, and the number of the second area 22 in the second board layer 2 includes but is not limited to 1. The first board layer 1 and the second board layer 2 are made of metal, ceramic or silicon wafer.

[0068] See also Figure 2In this embodiment, the surface of the first board layer 1 facing the second board layer 2 is flat, the surface of the second board layer 2 facing the first board layer 1 is flat, the surface of the first board layer 1 facing the second board layer 2 is parallel to the surface of the second board layer 2 facing the first board layer 1, and the surface of the second board layer away from the first board layer is discontinuous in the first area and the second area. The surface of the first board layer 1 facing the second board layer 2 is flat, and the surface of the second board layer 2 facing the first board layer 1 is flat, which reduces the difficulty of manufacturing the heat dissipation structure.

[0069] It should be understood that the surface of the first board layer 1 facing away from the second board layer 2 includes but is not limited to being a plane. Preferably, in order to reduce the difficulty of preparing the heat dissipation structure, the surface of the first board layer 1 facing away from the second board layer 2 is a plane.

[0070] See also Figure 2 In this embodiment, the depth of the second microchannel 23 located in the first area 21 is greater than the depth of the second microchannel 23 located in the second area 22. Since the distance from the surface of the second area in the second plate layer facing away from the first plate layer to the first plate layer is less than the distance from the surface of the first area facing away from the first plate layer to the first plate layer, when the depth of the second microchannel located in the first area is the same as the depth of the second microchannel located in the second area, the distance between the coolant flowing in the second microchannel in the first area and the chip arranged in the first area is greater than the distance between the coolant flowing in the second microchannel in the first area and the back of the chip arranged in the second area, so that the chip arranged in the first area cannot effectively dissipate heat, thereby causing heat accumulation in the multi-chip packaging structure, so that the performance of the chip arranged in the second area and the chip in the second area are both adversely affected; by making the depth of the second microchannel located in the first area greater than the depth of the second microchannel located in the second area, the heat dissipation effect of the first area is improved, that is, the heat dissipation effect of the heat dissipation structure is improved, and the adverse effect of heat accumulation in the multi-chip packaging structure on chip performance is avoided.

[0071] It should be understood that the difference between the depth of the second microchannel 23 located in the first area 21 and the depth of the second microchannel 23 located in the second area 22 is adapted to the difference between the distance from the surface of the first area 21 facing away from the first plate layer 1 to the first plate layer 1 and the distance from the surface of the second area 22 facing away from the first plate layer 1 to the first plate layer 1, that is, adapted to the thickness difference of the different chips. Specifically, the difference between the depth of the second microchannel 23 located in the first area 21 and the depth of the second microchannel 23 located in the second area 22 can be 50μm-700μm.

[0072] In this embodiment, the heat dissipation structure further includes: a coolant inlet 12 and a coolant outlet 13 located in the first plate layer 1, the coolant inlet 12 and the coolant outlet 13 are located on the side of the first plate layer 1 facing away from the second plate layer 2, and the coolant inlet 12 and the coolant outlet 13 are connected to the first microchannel 11. The coolant enters the microchannel structure through the coolant inlet 12, and flows out through the coolant outlet 13 after absorbing the heat generated by chips of different thicknesses, that is, the heat dissipation structure only needs to be provided with one set of coolant inlet 12 and coolant outlet 13, so that the coolant delivery structure is simpler.

[0073] Furthermore, the coolant inlet 12 and the coolant outlet 13 may both be located in the first area 21 or in the second area 22 in the orthographic projection of the second plate layer 2, or one of them may be located in the first area 21 and the other in the second area 22. Figure 2 , the orthographic projection of the coolant inlet 12 on the second plate layer 2 is located in the first area 21, and the orthographic projection of the coolant outlet 13 on the second plate layer 2 is located in the second area 22; or, the orthographic projection of the coolant outlet 13 on the second plate layer 2 is located in the first area 21, and the orthographic projection of the coolant inlet 12 on the second plate layer 2 is located in the second area 22. The above arrangement can make the coolant flow more fully in the microchannel structure located in the first area 21 and the microchannel structure located in the second area 22, thereby facilitating the heat dissipation efficiency of the first chip 4 and the second chip 5. Figure 2 In this embodiment, the heat dissipation structure further includes a connector 3 located between the first board layer 1 and the second board layer 2, and the connector 3 includes a first bonding layer 31 and a second bonding layer 32 connected; the surface of the first bonding layer 31 facing away from the second bonding layer 32 is connected to the first board layer 1; the surface of the second bonding layer 32 facing away from the first bonding layer 31 is connected to the second board layer 2. The connection between the first board layer 1 and the second board layer 2 is achieved by the connector 3, so that the first microchannel 11 is connected to the second microchannel 23 to form a microchannel structure, which can be used for heat dissipation in a multi-chip packaging structure. Specifically, the material of the connector 3 includes but is not limited to solder.

[0074] Furthermore, the first bonding layer 31 is arranged around the port of the first microchannel 11; the second bonding layer 32 is arranged around the port of the second microchannel 23 to seal the microchannel structure so that the microchannel structure forms a sealing area to prevent the coolant from losing from the connector 3.

[0075] In this embodiment, the orthographic projection of the second microchannel 23 on the first plate layer 1 is in the shape of a serpentine, and the orthographic projection of the first microchannel 11 on the second plate layer 2 is in the shape of a serpentine, so that the shape of the microchannel structure is serpentine. The cross-sectional view of the first plate layer 1 is as shown in FIG. Figure 3 As shown; or, the shape of the orthographic projection of the second microchannel 23 on the first plate layer 1 is a half-circle shape, and the shape of the orthographic projection of the first microchannel 11 on the second plate layer 2 is a half-circle shape, so that the shape of the microchannel structure is a half-circle shape, and the cross-sectional view of the first plate layer 1 is as shown Figure 4 Alternatively, the orthographic projection of the second microchannel 23 on the first plate layer 1 is in the shape of a grid, and the orthographic projection of the first microchannel 11 on the second plate layer 2 is in the shape of a grid, so that the shape of the microchannel structure is in the shape of a grid, and the cross-sectional view of the first plate layer 1 is as shown Figure 5 It should be understood that the orthographic projection of the second microchannel 23 on the first plate layer 1 and the orthographic projection of the first microchannel 11 on the second plate layer 2 have the same shape, and include but are not limited to the above-mentioned figures.

[0076] See also Figure 6 This embodiment also provides a chip packaging structure, including:

[0077] The heat dissipation structure provided in this embodiment;

[0078] A first chip 4, wherein the back side of the first chip 4 is arranged on a side of the first region 21 away from the first board layer 1;

[0079] The second chip 5 , the back side of the second chip 5 is arranged on the side of the second area 22 away from the first board layer 1 , and the thickness of the second chip 5 is greater than the thickness of the first chip 4 .

[0080] The chip packaging structure can meet the heat dissipation requirements of a multi-chip integrated structure with chips of different thicknesses.

[0081] It should be understood that the number of the above-mentioned first chips 4 includes but is not limited to 1, and the number of the above-mentioned second chips 5 includes but is not limited to 1; as an optional embodiment, the first chip 4 is a single chip, and the second chip 5 is a three-dimensional stacked chip; or, the first chip 4 and the second chip 5 are both single chips; or, the first chip 4 and the second chip 5 are both three-dimensional stacked chips.

[0082] In this embodiment, see Figure 6The chip packaging structure further includes: an encapsulation layer 6, which is arranged on the side of the second board layer 2 away from the first board layer 1, and the encapsulation layer 6 wraps the first chip 4 and the second chip 5 and exposes the front of the first chip 4 and the front of the second chip 5; a rewiring structure 7, which is arranged on the surface of the encapsulation layer 6 on the side away from the second board layer 2, and the front of the first chip 4 is connected to the rewiring structure 7, and the front of the second chip 5 is connected to the rewiring structure 7. The chip packaging structure wraps the first chip 4 and the second chip 5 through the encapsulation layer 6, thereby improving the strength and stability of the chip packaging structure, and plays a role in fixing and supporting the rewiring structure 7, avoiding the adverse effect of the bending of the rewiring structure 7 on the device performance.

[0083] Furthermore, the front surface of the second chip 5 is flush with the front surface of the first chip 4 , so that the surface of the encapsulation layer 6 facing away from the first board layer 1 is a plane, and the preparation process is simple.

[0084] In this embodiment, see Figure 6 The chip packaging structure further includes: an adhesive layer 8, the adhesive layer 8 is located between the back surface of the first chip 4 and the side surface of the first area 21 away from the first board layer 1 and between the back surface of the second chip 5 and the side surface of the second area 22 away from the first board layer 1; solder balls 9, the solder balls 9 are arranged on the side surface of the rewiring structure 7 away from the first chip 4. By arranging the rewiring structure 7 and the solder balls 9, the first chip 4 and the second chip 5 can pass voltage or current and then work.

[0085] Furthermore, the material of the adhesive layer 8 can be silicone adhesive sealant, which has high heat resistance and thermal conductivity. When the heat generation per unit area of ​​the first chip 4 and the second chip 5 is high, the use of silicone adhesive sealant can improve the firmness of the bonding.

[0086] See also Figure 7 This embodiment also provides a method for preparing a heat dissipation structure, comprising the following steps:

[0087] S1. Provide a first board layer 1 and a second board layer 2, wherein the second board layer 2 includes a first area 21 and a second area 22 adjacent to each other, and an arrangement direction from the first area 21 to the second area 22 is parallel to an extension surface of the second board layer 2;

[0088] S2, setting a first microchannel 11 in a partial thickness of the first plate layer 1;

[0089] S3, forming a second microchannel 23 in the first area 21 and the second area 22 of the partial thickness;

[0090] S4, arranging the first plate layer 1 and the second plate layer 2 opposite to each other and bonding them together, and making the second microchannel 23 communicate with the first microchannel 11;

[0091] S5. Thinning the surface of the second region 22 of the second board layer 2 which is away from the first board layer 1 , so that the thickness of the second region 22 is smaller than the thickness of the first region 21 .

[0092] Figures 8 to 15 Schematic diagram of the preparation process of the heat dissipation structure of this embodiment.

[0093] See also Figure 8 , providing a first board layer 1. Specifically, the first board layer 1 has a plane; the material of the first board layer 1 is metal, ceramic or silicon wafer.

[0094] See also Fig. 9 , a first bonding layer 31 is disposed on one side surface of the first board layer 1. Specifically, solder is coated on one side surface of the first board layer 1 to form the first bonding layer 31.

[0095] See also Fig.10 , a first microchannel 11 is arranged in a partial thickness of the first plate layer 1. Specifically, an area on the side of the first plate layer 1 where the first bonding layer 31 is arranged but where the first bonding layer 31 is not arranged is etched, so that the first bonding layer 31 surrounds the port of the first microchannel 11.

[0096] It is important to understand that Figure 9-10 As shown, the first bonding layer 31 is firstly arranged on one side surface of the first board layer 1, and then the first microchannel is arranged; or the first microchannel 11 can be firstly arranged in a partial thickness of the first board layer 1, and then the first bonding layer 31 is arranged at the port of the first microchannel 11.

[0097] See also Fig.10 A coolant inlet 12 and a coolant outlet 13 are provided in the first plate layer 1 of a partial thickness, and the coolant inlet 12 and the coolant outlet 13 are connected to the first microchannel 11. Specifically, a surface of the first plate layer 1 on which the first bonding layer 31 is not provided is etched so that the coolant inlet 12 and the coolant outlet 13 are connected to the first microchannel 11.

[0098] It should be understood that the first microchannel 11 may be formed first and then the coolant inlet 12 and the coolant outlet 13 are formed, or the coolant inlet 12 and the coolant outlet 13 may be formed first and then the first microchannel 11 is formed.

[0099] See also Fig.11, providing a second board layer 2. Specifically, the second board layer 2 includes a first area 21 and a second area 22 adjacent to each other, and the arrangement direction from the first area 21 to the second area 22 is parallel to the extension surface of the second board layer 2; the material of the second board layer 2 is metal, ceramic or silicon wafer.

[0100] See also Fig.12 A second bonding layer 32 is disposed on one side surface of the first area 21 and the second area 22. Specifically, solder is coated on one side surface of the second board layer 2 to form the second bonding layer 32.

[0101] See also Fig.13 , forming the second microchannel 23 in the first area 21 and the second area 22 of the partial thickness. Specifically, etching is performed on the area on the side of the second plate layer 2 where the second bonding layer 32 is provided but the second bonding layer 32 is not provided, so that the second bonding layer 32 surrounds the port of the second microchannel 23.

[0102] It is important to understand that Figure 12-13 As shown, a second bonding layer 32 is firstly provided on one side surface of the first area 21 and the second area 22, and then a second microchannel 23 is formed in the partial thickness of the first area 21 and the second area 22; alternatively, a second microchannel 23 is firstly formed in the partial thickness of the first area 21 and the second area 22, and then a second bonding layer 32 is provided at the port of the second microchannel 23.

[0103] See also Fig.14 The first plate layer 1 and the second plate layer 2 prepared in the above steps are arranged opposite to each other and bonded together, and the second microchannel 23 is connected to the first microchannel 11. Specifically, the first bonding layer 31 and the second bonding layer 32 are bonded.

[0104] See also Fig.15 , the second area 22 of the second board layer 2 is thinned on one side away from the first board layer 1, so that the thickness of the first area 21 is greater than the thickness of the second area 22. Specifically, the thinning method is at least one of a mechanical thinning process, a chemical mechanical polishing process, and a chemical etching process.

[0105] It should be understood that before forming the second bonding layer 32, a partial area of ​​the surface of one side of the second board layer 2 can be thinned, and then the second bonding layer 32 can be formed on the opposite side surface of the second board layer 2; or, after forming the second bonding layer 32 and before forming the second microchannel 23, the surface of one side of the second board layer 2 where the second bonding layer 32 is not set can be thinned.

[0106] like Fig.16 As shown, this embodiment also provides a method for preparing a chip packaging structure, comprising the following steps:

[0107] S6. Provide a first chip 4, a second chip 5 and the heat dissipation structure described in this embodiment, wherein the thickness of the second chip 5 is greater than the thickness of the first chip 4;

[0108] S7. Dispose the back side of the first chip 4 on a side surface of the first area 21 away from the first board layer 1 ; and dispose the back side of the second chip 5 on a side surface of the second area 22 away from the first board layer 1 .

[0109] Figures 17 to 21 It is a structural schematic diagram of the preparation process of the chip packaging structure of this embodiment.

[0110] See also Fig.17 , the back side of the first chip 4 is arranged on a side surface of the first area 21 away from the first board layer 1 ; the back side of the second chip 5 is arranged on a side surface of the second area 22 away from the first board layer 1 .

[0111] Specifically, a first adhesive layer 81 is set on the side surface of the first area 21 away from the first board layer 1, and the back side of the first chip 4 is set on the first adhesive layer 81. After the first adhesive layer 81 is cured, the back side of the first chip 4 is fixed to the side surface of the first area 21 away from the first board layer 1; a second adhesive layer 82 is set on the side surface of the second area 22 away from the first board layer 1, and the back side of the second chip 5 is set on the second adhesive layer 82. After the second adhesive layer 82 is cured, the back side of the second chip 5 is fixed to the side surface of the second area 22 away from the first board layer 1.

[0112] Furthermore, the front surface of the second chip 5 is flush with the front surface of the first chip 4 .

[0113] See also Fig.18 An encapsulation layer 6 is formed on a surface of the second board layer 2 that is away from the first board layer 1 , and the encapsulation layer 6 wraps the first chip 4 and the second chip 5 .

[0114] See also Fig.19 , the encapsulation layer 6 is thinned to expose the front surface of the first chip 4 and the front surface of the second chip 5. Specifically, the thinning method is at least one of chemical mechanical polishing, mechanical etching, and chemical etching.

[0115] See also Fig. 20A rewiring structure 7 is formed on the surface of the encapsulation layer 6 facing away from the second board layer, the front surface of the first chip 4 and the front surface of the second chip 5. The front surface of the first chip 4 is connected to the rewiring structure 7, and the front surface of the second chip 5 is connected to the rewiring structure 7.

[0116] See also Fig.21 A solder ball 9 is arranged on a surface of the redistribution structure 7 which is away from the first chip 4 .

[0117] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A heat dissipation structure, comprising a first plate layer and a second plate layer arranged opposite to each other; the first plate layer has a first microchannel, and the first microchannel faces the second plate layer; the second plate layer comprises a first area and a second area adjacent to each other, the arrangement direction from the first area to the second area is parallel to the extension surface of the second plate layer, the distance from the surface of the second area facing away from the first plate layer to the first plate layer is smaller than the distance from the surface of the first area facing away from the first plate layer to the first plate layer, the first area and the second area are provided with a second microchannel, and the second microchannel is connected to the first microchannel; A first chip, wherein the back side of the first chip is arranged on a side of the first region away from the first board layer; A second chip, wherein the back side of the second chip is arranged on a side of the second region away from the first board layer, and the thickness of the second chip is greater than that of the first chip.

2. The chip packaging structure according to claim 1, characterized in that: The surface of the first board layer facing the second board layer is planar, the surface of the second board layer facing the first board layer is planar, and the surface of the first board layer facing the second board layer is parallel to the surface of the second board layer facing the first board layer.

3. The chip packaging structure according to claim 1, characterized in that: The depth of the second micro-channel located in the first region is greater than the depth of the second micro-channel located in the second region.

4. The chip packaging structure according to claim 3, characterized in that: A difference between a depth of the second microchannel located in the first region and a depth of the second microchannel located in the second region is 50 μm-700 μm.

5. The chip packaging structure according to claim 1, characterized in that: Also includes: A coolant inlet and a coolant outlet are located in the first plate layer, the coolant inlet and the coolant outlet are located on a side of the first plate layer facing away from the second plate layer, and the coolant inlet and the coolant outlet are communicated with the first microchannel.

6. The chip packaging structure according to claim 5, characterized in that: The orthographic projection of the coolant inlet on the second plate layer is located in the first area, and the orthographic projection of the coolant outlet on the second plate layer is located in the second area; Alternatively, the orthographic projection of the cooling liquid outlet on the second plate layer is located in the first area, and the orthographic projection of the cooling liquid inlet on the second plate layer is located in the second area.

7. The chip packaging structure according to claim 1, characterized in that: Also includes: A connector located between the first board layer and the second board layer, the connector comprising a first bonding layer and a second bonding layer connected thereto; The surface of the first bonding layer facing away from the second bonding layer is connected to the first board layer; The surface of the second bonding layer facing away from the first bonding layer is connected to the second board layer.

8. The chip packaging structure according to claim 7, characterized in that: The first bonding layer is disposed around the port of the first microfluidic channel; the second bonding layer is disposed around the port of the second microfluidic channel.

9. The chip packaging structure according to claim 1, characterized in that: The orthographic projection of the second microchannel on the first plate layer is in the shape of a serpentine, and the orthographic projection of the first microchannel on the second plate layer is in the shape of a serpentine; or, the orthographic projection of the second microchannel on the first plate layer is in the shape of a half-circle, and the orthographic projection of the first microchannel on the second plate layer is in the shape of a half-circle; Alternatively, the orthographic projection of the second microchannel on the first plate layer is in a grid shape, and the orthographic projection of the first microchannel on the second plate layer is in a grid shape.

10. The chip packaging structure according to claim 1, characterized in that: Also includes: An encapsulation layer, the encapsulation layer is arranged on a side of the second board layer away from the first board layer, the encapsulation layer wraps the first chip and the second chip and exposes the front side of the first chip and the front side of the second chip; A rewiring structure is provided on a surface of the encapsulation layer facing away from the second board layer, the front side of the first chip is connected to the rewiring structure, and the front side of the second chip is connected to the rewiring structure.

11. A chip packaging method, characterized in that: The following steps are involved: Provide a first chip, a second chip, and the heat dissipation structure according to any one of claims 1 to 9, wherein the thickness of the second chip is greater than the thickness of the first chip; Disposing the back side of the first chip on a surface of the first region facing away from the first board layer; The back side of the second chip is arranged on a surface of the second region facing away from the first board layer.

12. The chip packaging method according to claim 11, characterized in that: Providing the heat dissipation structure comprises the following steps: Providing a first board layer and a second board layer, wherein the second board layer comprises a first area and a second area adjacent to each other, and an arrangement direction from the first area to the second area is parallel to an extension surface of the second board layer; Disposing a first microfluidic channel in a partial thickness of the first plate layer; forming a second microfluidic channel in the first and second regions of the partial thickness; The first plate layer and the second plate layer are arranged opposite to each other and bonded together, and the second microfluidic channel is connected to the first microfluidic channel; The surface of the second region of the second board layer which is away from the first board layer is thinned so that the thickness of the second region is smaller than the thickness of the first region.

13. The chip packaging method according to claim 12, characterized in that: Providing the heat dissipation structure also includes: A coolant inlet and a coolant outlet are arranged in the first plate layer of partial thickness, and the coolant inlet and the coolant outlet are connected to the first microchannel; after the first plate layer and the second plate layer are arranged opposite to each other and bonded together, the coolant inlet and the coolant outlet are located on the side of the first plate layer facing away from the second plate layer.

14. The chip packaging method according to claim 12, characterized in that: Providing the heat dissipation structure further includes: arranging a first bonding layer on one side surface of the first plate layer; after forming the first microchannel, the first bonding layer is arranged around the port of the first microchannel; arranging a second bonding layer on one side surface of the first area and the second area, and after forming the second microchannel, the second bonding layer is arranged around the port of the second microchannel; Bonding the first board layer and the second board layer together includes: bonding the first bonding layer to the second bonding layer.

15. The chip packaging method according to claim 11, characterized in that: Also includes: An encapsulation layer is formed on a surface of the second board layer facing away from the first board layer, wherein the encapsulation layer wraps the first chip and the second chip and exposes the front side of the first chip and the front side of the second chip; A rewiring structure is formed on the surface of the encapsulation layer facing away from the second board layer, the front side of the first chip and the front side of the second chip, the front side of the first chip is connected to the rewiring structure, and the front side of the second chip is connected to the rewiring structure.

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