Thin Film Transistor Array

Abstract

The present invention provides a thin film transistor array with low power consumption. The thin film transistor array includes: column wiring, row wiring, capacitor wiring; and a plurality of pixels, the plurality of pixels are arranged in a matrix along a first direction and a second direction, and have thin film transistors, etc., the plurality of pixels form an effective area of ​​M columns and N rows, the source electrode of the thin film transistor is connected to the column wiring, the gate electrode is connected to the row wiring, the drain electrode is connected to the pixel electrode, the capacitor electrode is connected to the capacitor wiring, the row wiring is the length of M pixels arranged along the second direction, the column wiring is the length of N / 2 pixels arranged along the first direction, and the capacitor wiring is the length of N pixels arranged along the first direction.

Description

Technical Field

[0001] The present invention relates to a thin film transistor array. The thin film transistor array of the present invention can be used in a display device. In addition, the thin film transistor array of the present invention is suitable for low power consumption applications. Background Art

[0002] Based on transistor and integrated circuit technology that uses the semiconductor itself as a substrate, amorphous silicon (a-Si) and polycrystalline silicon (poly-Si) thin film transistor (TFT) arrays are manufactured on glass substrates and applied to liquid crystal displays, etc. TFT plays the role of a switch. When the TFT is turned on by the selection voltage provided to the row wiring (gate wiring), the signal voltage provided to the column wiring (source wiring) is written to the pixel electrode connected to the drain electrode. The written voltage is maintained in a storage capacitor provided between the drain electrode or the pixel electrode and the capacitor electrode. (In the case of a TFT array, the role of the source and drain changes according to the polarity of the written voltage, so the name is not determined during the operation. Therefore, for convenience, one side is called the source and the other side is called the drain, and they are collectively referred to as such. In the present invention, the side connected to the wiring is called the source, and the side connected to the pixel electrode is called the drain.)

[0003] TFT arrays have developed technology as liquid crystal display devices that use liquid crystal as a display medium. In recent years, electronic paper display devices that combine thin film transistor arrays and electrophoretic media have been developed, and are expected to be display devices with lower power consumption than liquid crystals. This is because general liquid crystal display devices can only display during driving, and they need to continue to be driven in order to maintain the display. In contrast, electrophoretic electronic paper also maintains the display after the drive ends, so it does not need to be driven.

[0004] Furthermore, a technology combining electronic paper and RFID as an individual identification technology to form a display unit of a container is disclosed (Patent Document 1). By displaying the content data stored in the RFID on the display unit, the data can be confirmed even by visual observation.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2003-233786 Summary of the invention

[0008] Problems that the invention will solve

[0009] Among such display devices, there are types that use the power of a built-in battery for rewriting, and types that convert the radio waves of a reader / writer that rewrites the RFID into electricity and use the electricity to rewrite. In each type, reducing the amount of power consumed during rewriting becomes a problem. In a display device with a built-in battery, if the power consumption is large, the battery needs to be replaced frequently. In a display device that uses the power of RF waves, if the power consumption is large, rewriting can only be performed at a close distance where the radio waves are strong.

[0010] The present invention has been made in view of the state of the prior art, and an object of the present invention is to provide a thin film transistor array with reduced power consumption.

[0011] Means for solving problems

[0012] One mode of the present invention for solving the above-mentioned problems is a thin film transistor array, comprising: an insulating substrate; a plurality of column wirings extending along a first direction on the insulating substrate, a plurality of row wirings extending along a second direction orthogonal to the first direction, and a plurality of capacitor wirings extending along the first direction; and a plurality of pixels arranged in a matrix along the first direction and the second direction, having thin film transistors, pixel electrodes, and capacitor electrodes, the plurality of pixels forming a rectangular effective area (an area that can be used for display) composed of a matrix structure of M columns and N rows (M and N are natural numbers), with N pixels arranged along the first direction and M pixels arranged along the second direction, the thin film transistor having a gate electrode, a source electrode, and a drain electrode, the source electrode being connected to the column wiring, the gate electrode being connected to the row wiring, the drain electrode being connected to the pixel electrode, and the capacitor electrode being connected to the capacitor wiring, the row wiring being a length spanning M pixels arranged along the second direction in the effective area, the column wiring being a length spanning N / 2 pixels arranged along the first direction in the effective area, and the capacitor wiring being a length different from the column wiring and spanning N pixels arranged along the first direction in the effective area.

[0013] Effects of the Invention

[0014] According to the present invention, a thin film transistor array with low power consumption can be provided. That is, by using the present invention in a display device, the power consumption of the display device during rewriting can be reduced, and the battery replacement frequency of a battery-built-in display device can be reduced. In addition, the rewritable distance of a display device of the type that performs power conversion by RF radio waves can be extended. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A It is a plan view showing an example of a thin film transistor array according to the first embodiment of the present invention.

[0016] Figure 1BIt is a plan view showing an example of a thin film transistor array according to the first embodiment of the present invention.

[0017] Figure 2A It is a plan view showing an example of a thin film transistor array according to a second embodiment of the present invention.

[0018] Figure 2B It is a plan view showing an example of a thin film transistor array according to a second embodiment of the present invention.

[0019] Figure 3A It is a plan view showing an example of a thin film transistor array according to a third embodiment of the present invention.

[0020] Figure 3B It is a plan view showing an example of a thin film transistor array according to a third embodiment of the present invention.

[0021] Figure 4A It is a cross-sectional view showing an example of electrostatic capacitance between electrodes.

[0022] Figure 4B It is a cross-sectional view showing an example of electrostatic capacitance between electrodes.

[0023] Figure 4C It is a cross-sectional view showing an example of electrostatic capacitance between electrodes.

[0024] Figure 4D It is a cross-sectional view showing an example of electrostatic capacitance between electrodes.

[0025] Figure 5A It is a plan view showing an example of power supply to the thin film transistor array according to the first embodiment.

[0026] Figure 5B It is a plan view showing an example of power supply to the thin film transistor array according to the first embodiment.

[0027] Figure 5C It is a plan view showing an example of power supply to the thin film transistor array according to the first embodiment.

[0028] Figure 5D It is a plan view showing an example of power supply to the thin film transistor array according to the first embodiment.

[0029] Figure 6 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0030] Figure 7 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0031] Figure 8The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0032] Fig. 9 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0033] Fig.10 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0034] Fig.11 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0035] Fig.12 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0036] Fig.13 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0037] Fig.14 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0038] Fig.15 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0039] Fig.16 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0040] Fig.17 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0041] Fig.18 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0042] Fig.19 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0043] Fig. 20 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0044] Fig.21 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0045] Fig. 22The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0046] Fig.23 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0047] Fig.24 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0048] Fig.25 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0049] Fig.26 The diagrams are a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the first embodiment.

[0050] Fig.27A It is a plan view showing an example of power supply to the thin film transistor array according to the second embodiment.

[0051] Fig.27B It is a plan view showing an example of power supply to the thin film transistor array according to the second embodiment.

[0052] Fig.27C It is a plan view showing an example of power supply to the thin film transistor array according to the second embodiment.

[0053] Fig.27D It is a plan view showing an example of power supply to the thin film transistor array according to the second embodiment.

[0054] Fig.28 The diagram is a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the second embodiment.

[0055] Fig.29 The diagram is a plan view and a cross-sectional view showing the manufacturing process of the thin film transistor array according to the second embodiment.

[0056] Fig. 30A It is a plan view showing an example of power supply to the thin film transistor array according to the third embodiment.

[0057] Fig. 30B It is a plan view showing an example of power supply to the thin film transistor array according to the third embodiment.

[0058] Fig. 30C It is a plan view showing an example of power supply to the thin film transistor array according to the third embodiment.

[0059] Fig.30D It is a plan view showing an example of power supply to the thin film transistor array according to the third embodiment.

[0060] Fig.31 The diagrams are a plan view and a cross-sectional view showing a manufacturing process of a thin film transistor array according to the third embodiment.

[0061] Fig.32 The diagrams are a plan view and a cross-sectional view showing a manufacturing process of a thin film transistor array according to the third embodiment.

[0062] Fig.33 The diagram shows the voltage waveform, current waveform, and calculation of the electric power in the column wiring.

[0063] Fig.34 The diagram shows the voltage waveform, current waveform, and calculation of the electric power in the row wiring.

[0064] Fig.35 It is a diagram showing the voltage waveform, current waveform, and calculation of the electric power amount in the pixel TFT.

[0065] Fig.36 FIG. 1 is a plan view showing an example of a conventional thin film transistor array.

[0066] Fig.37 It means to Fig.36 A top view of an example of a power supply for a thin film transistor.

[0067] Fig.38 FIG. 1 is a plan view showing an example of a conventional thin film transistor array.

[0068] Fig.39 It means to Fig.38 A top view of an example of a power supply for a thin film transistor. DETAILED DESCRIPTION

[0069] The following is a detailed description of the embodiments of the present invention using the accompanying drawings. In addition, in the following drawings, the scale is not accurately drawn for the sake of easy understanding of the description. In addition, the same reference numerals are marked for the same or corresponding structures between the embodiments, and the description is omitted.

[0070] (Basic Configuration of First to Third Embodiments)

[0071] The basic structures of the thin film transistor arrays according to the first to third embodiments of the present invention are shown in FIG. Figure 1A , Figure 2A ,or Figure 3A In. Figure 1A , Figure 2A , Figure 3AAs shown, the thin film transistor array includes an insulating substrate 1 (not shown), a plurality of column wirings 4L extending along the longitudinal direction (first direction) of the figure on the insulating substrate 1, a plurality of row wirings 2L extending along the transverse direction (second direction) of the figure orthogonal to the longitudinal direction, a plurality of capacitor wirings 8L extending along the longitudinal direction, and a plurality of pixels arranged in a matrix along the longitudinal and transverse directions (the positions where the pixels are arranged are represented by squares. The pixels themselves are not shown). The plurality of pixels form a rectangular effective area, and the rectangular effective area is composed of a matrix structure of M columns and N rows (M and N are natural numbers) with N pixels arranged along the longitudinal direction and M pixels arranged along the transverse direction.

[0072] Although in Figure 1A , Figure 2A , Figure 3A It is not described in the figure, but the pixel has a thin film transistor, a pixel electrode 10, and a capacitor electrode 8. The thin film transistor has a gate electrode 2, a source electrode 4, and a drain electrode 5. There is a semiconductor pattern 6 between the source electrode 4 and the drain electrode 5. The semiconductor pattern 6 overlaps with the gate electrode 2 via the gate insulating film 3. The capacitor electrode 8 has an electrostatic capacitance with the pixel electrode 10. The source electrode 4 is connected to the column wiring 4L, the gate electrode 2 is connected to the row wiring 2L, the drain electrode 5 is connected to the pixel electrode 10, and the capacitor electrode 8 is connected to the capacitor wiring 8L. Although described in detail later, these electrodes and wirings are stacked via multiple insulating films.

[0073] Figure 1A , Figure 2A , Figure 3A FIG. 2 shows the planar arrangement and length of the row wiring 2L, column wiring 4L, and capacitor wiring 8L. The row wiring 2L is the length of M pixels arranged in the horizontal direction in the effective area. The column wiring 4L is the length of N / 2 pixels arranged in the vertical direction in the effective area. The capacitor wiring 8L is the length of N pixels arranged in the vertical direction in the effective area. The positions of the row wiring 2L, column wiring 4L, and capacitor wiring 8L in the stacking direction are arbitrary. That is, although Figure 1A , Figure 2A , Figure 3A It is described that the column wiring 4L and the capacitor wiring 8L are located above the row wiring 2L, but this is not necessarily the case. In addition, the upper half and the lower half of the display surface are also referred to as the upper region and the lower region below. In addition, the row wiring 2L and the column wiring 4L formed in the upper region and the lower region are also referred to as the upper region row wiring 2L, the lower region row wiring 2L, the upper region column wiring 4L, and the lower region column wiring 4L.

[0074] like Figure 1AAs shown, in the thin film transistor array of the first embodiment, one column wiring 4L is configured for each column consisting of N / 2 pixels arranged in the vertical direction. Thus, M column wirings 4L are provided in each of the two regions, and 2M are provided in total in the entire effective area. In addition, one row wiring 2L is configured for each row consisting of M pixels arranged in the horizontal direction. Thus, N / 2 row wirings 2L are provided in each of the two regions, and N are provided in total in the entire effective area. In addition, one capacitor wiring 8L is configured for each column consisting of N pixels arranged in the vertical direction. Thus, M capacitor wirings 8L are provided in the entire effective area.

[0075] like Figure 2A As shown, in the thin film transistor array of the second embodiment, one column wiring 4L is configured for each column consisting of N / 2 pixels arranged in the vertical direction. Thus, M column wirings 4L are provided in each of the two regions, and 2M are provided in total in the entire effective area. In addition, one row wiring 2L is configured for each row consisting of M pixels arranged in the horizontal direction. Thus, N / 2 row wirings 2L are provided in each of the two regions, and N are provided in total in the entire effective area. In addition, one capacitor wiring 8L is configured for each column consisting of N pixels arranged in the vertical direction. Thus, M / 2 are provided in the entire effective area.

[0076] like Figure 3A As shown, in the thin film transistor array of the third embodiment, two column wirings 4L are arranged for each column consisting of N / 2 pixels arranged in the vertical direction. Thus, 2M column wirings 4L are provided in two regions, respectively, and 4M are provided in total in the entire effective area. In addition, one row wiring 2L is arranged for each row consisting of M pixels arranged in the horizontal direction. Thus, N / 4 row wirings 2L are provided in two regions, respectively, and N / 2 are provided in total in the entire effective area. In addition, one capacitor wiring 8L is arranged for each column consisting of N pixels arranged in the vertical direction. Thus, M are provided in the entire effective area.

[0077] The basic structure of a conventional thin film transistor array is shown in Fig.36 and Fig.38 middle. Fig.36 The thin film transistor array has a column wiring 4L extending in the longitudinal direction, a row wiring 2L extending in the transverse direction, and a capacitor wiring 8L extending in the transverse direction. The row wiring 2L is long enough to reach (span) all pixels arranged in the transverse direction of the effective area, the column wiring 4L is long enough to reach all pixels arranged in the longitudinal direction of the effective area, and the capacitor wiring 8L is long enough to reach all pixels arranged in the transverse direction of the effective area. Fig.36 The supply lines of the thin film transistor array are shown in Fig.37 The gate power supply line 11 is connected to the left end of the row wiring 2L, the source power supply line 12 is connected to the lower end of the column wiring 4L, and the capacitor power supply line 13 is connected to the right end of the capacitor wiring 8L.

[0078] Fig.38 The thin film transistor array has a column wiring 4L extending in the longitudinal direction, a row wiring 2L extending in the transverse direction, and a capacitor wiring 8L extending in the longitudinal direction. The row wiring 2L is the length that reaches all pixels arranged in the transverse direction of the effective area, the column wiring 4L is the length that reaches all pixels arranged in the longitudinal direction of the effective area, and the capacitor wiring 8L is the length that reaches all pixels arranged in the longitudinal direction of the effective area. Fig.38 The supply lines of the thin film transistor array are shown in Fig.39 The gate power supply line 11 is connected to the left end of the row wiring 2L, the source power supply line 12 is connected to the lower end of the column wiring 4L, and the capacitor power supply line 13 is connected to the upper end of the capacitor wiring 8L.

[0079] Thus, the row wiring 2L and the column wiring 4L necessarily have an intersection, and the capacitor wiring 8L has an intersection with at least the row wiring 2L or the column wiring 4L. The intersection has an electrostatic capacitance that depends on the overlapping area of ​​the wirings, the thickness of the insulating film, and the dielectric constant. The capacitance between the row wiring and the column wiring is Cgsl, the capacitance between the row wiring and the capacitor wiring is Cgc, and the capacitance between the column wiring and the capacitor wiring is Csc.

[0080] In addition, by covering most of the row wiring 2L and the column wiring 4L with the pixel electrode 10, it is possible to prevent the potential of the row wiring 2L and the column wiring 4L from directly affecting the display, but the electrostatic capacitance between the row wiring 2L, the column wiring 4L and the pixel electrode 10 cannot be ignored. The capacitance between the row wiring and the pixel electrode is denoted as Cgp, and the capacitance between the column wiring and the pixel electrode is denoted as Csp.

[0081] In addition, the TFT has a semiconductor pattern 6 between the source electrode 4 and the drain electrode 5, and the semiconductor pattern 6 overlaps with the gate electrode 2 via the gate insulating film 3. A portion of the source electrode 4 and the drain electrode 5 also overlaps with the gate electrode 2, so in principle there is a gate electrode-source electrode capacitance Cgs and a gate electrode-drain electrode capacitance Cgd. Furthermore, the capacitor electrode 8 has an electrostatic capacitance Cs between the pixel electrode 10.

[0082] Figure 4A It is a cross-sectional view showing an example of a thin film transistor constituting a thin film transistor array according to the first to third embodiments of the present invention. Figure 4AThe TFT has, in sequence, on an insulating substrate 1: a first conductive layer having a gate electrode 2 and a row wiring 2L, a gate insulating film 3, a second conductive layer having a source electrode 4, a column wiring 4L and a drain electrode 5, an interlayer insulating film 7, a third conductive layer having a capacitor electrode 8 and a capacitor wiring 8L, a capacitor insulating film 9, and a fourth conductive layer having a pixel electrode 10.

[0083] Figure 4A The area where the electrostatic capacitance between each wiring and electrode (row wiring · column wiring capacitance Cgsl, row wiring · capacitor wiring capacitance Cgc, column wiring · capacitor wiring capacitance Csc, row wiring · pixel electrode capacitance Cgp, column wiring · pixel electrode capacitance Csp, gate electrode · source electrode capacitance Cgs, gate electrode · drain electrode capacitance Cgd, storage capacitance Cs) is generated is schematically shown. (Since the overlapping part of Cgsl and Cgc is not included in the cross section, they are marked with arrows.) When the TFT is turned on (when calculating the gate feed-through voltage), in order to calculate Cgs, the overlapping area of ​​the gate electrode 2 · source electrode 4 is added with about half of the area of ​​the channel portion 6C, and in order to calculate Cgd, the overlapping area of ​​the gate electrode 2 · drain electrode 5 is added with about half of the area of ​​the channel portion 6C. When the TFT is turned off (when calculating parasitic capacitance), Cgs is related only to the overlapping area of ​​the gate electrode 2 and the source electrode 4, and Cgd is related only to the overlapping area of ​​the gate electrode 2 and the drain electrode 5. Cs is composed of the pixel electrode 10 / capacitor insulating film 9 / capacitor electrode 8.

[0084] Figure 4B It is a cross-sectional view showing an example of a thin film transistor constituting a thin film transistor array according to the first to third embodiments of the present invention. Figure 4B The TFT has, in sequence, on an insulating substrate 1: a first conductive layer having a source electrode 4, a column wiring 4L, and a drain electrode 5, a gate insulating film 3, a second conductive layer having a gate electrode 2 and a row wiring 2L, an interlayer insulating film 7, a third conductive layer having a capacitor electrode 8 and a capacitor wiring 8L, a capacitor insulating film 9, and a fourth conductive layer having a pixel electrode 10.

[0085] Figure 4BThe area where the electrostatic capacitance between each wiring and electrode (row wiring · column wiring capacitance Cgsl, row wiring · capacitor wiring capacitance Cgc, column wiring · capacitor wiring capacitance Csc, row wiring · pixel electrode capacitance Cgp, column wiring · pixel electrode capacitance Csp, gate electrode · source electrode capacitance Cgs, gate electrode · drain electrode capacitance Cgd, storage capacitance Cs) is generated is schematically shown. (Since the overlapping part of Cgsl and Cgc is not included in the cross section, they are marked with arrows.) When the TFT is turned on (when calculating the gate feed-through voltage), in order to calculate Cgs, the overlapping area of ​​the gate electrode 2 · source electrode 4 is added with about half of the area of ​​the channel portion 6C, and in order to calculate Cgd, the overlapping area of ​​the gate electrode 2 · drain electrode 5 is added with about half of the area of ​​the channel portion 6C. When the TFT is turned off (when calculating parasitic capacitance), Cgs is related only to the overlapping area of ​​the gate electrode 2 and the source electrode 4, and Cgd is related only to the overlapping area of ​​the gate electrode 2 and the drain electrode 5. Cs is composed of the pixel electrode 10 / capacitor insulating film 9 / capacitor electrode 8.

[0086] Figure 4C It is a cross-sectional view showing an example of a thin film transistor constituting a thin film transistor array according to the first to third embodiments of the present invention. Figure 4C The TFT has, in sequence, on an insulating substrate 1: a first conductive layer having a gate electrode 2, a row wiring 2L, and a drain sub-electrode 5S, a gate insulating film 3, a second conductive layer having a source electrode 4, a column wiring 4L, a drain electrode 5, a capacitor electrode 8, and a capacitor wiring 8L, an interlayer insulating film 7, and a third conductive layer having a pixel electrode 10.

[0087] Figure 4CThe area where the electrostatic capacitance between each wiring and electrode (row wiring · column wiring capacitance Cgsl, row wiring · capacitor wiring capacitance Cgc, row wiring · pixel electrode capacitance Cgp, column wiring · pixel electrode capacitance Csp, gate electrode · source electrode capacitance Cgs, gate electrode · drain electrode capacitance Cgd, storage capacitance Cs) is generated is schematically shown. (Cgsl and Cgc are marked with arrows because the overlapping part is not included in the cross section. Csc is approximately 0 because it has no overlapping part.) When the TFT is turned on (when calculating the gate feed-through voltage), in order to calculate Cgs, the overlapping area of ​​the gate electrode 2 · source electrode 4 is added with approximately half of the area of ​​the channel portion 6C, and in order to calculate Cgd, the overlapping area of ​​the gate electrode 2 · drain electrode 5 is added with approximately half of the area of ​​the channel portion 6C. When the TFT is turned off (when calculating the parasitic capacitance), Cgs is only related to the overlapping area of ​​the gate electrode 2 and the source electrode 4, and Cgd is only related to the overlapping area of ​​the gate electrode 2 and the drain electrode 5. Cs is mainly composed of the capacitor electrode 8 / gate insulating film 3 / drain sub-electrode 5S, but the pixel electrode 10 / interlayer insulating film 7 / capacitor electrode 8 are also added.

[0088] Figure 4D It is a cross-sectional view showing an example of a thin film transistor constituting a thin film transistor array according to the first to third embodiments of the present invention. Figure 4D The TFT has, in sequence, on an insulating substrate 1: a first conductive layer having a source electrode 4, a column wiring 4L, a drain electrode 5, a capacitor electrode 8, and a capacitor wiring 8L, a gate insulating film 3, a second conductive layer having a gate electrode 2, a row wiring 2L, and a drain sub-electrode 5S, an interlayer insulating film 7, and a third conductive layer having a pixel electrode 10.

[0089] Figure 4DThe area where the electrostatic capacitance between each wiring and electrode (row wiring · column wiring capacitance Cgsl, row wiring · capacitor wiring capacitance Cgc, row wiring · pixel electrode capacitance Cgp, column wiring · pixel electrode capacitance Csp, gate electrode · source electrode capacitance Cgs, gate electrode · drain electrode capacitance Cgd, storage capacitance Cs) is generated is schematically shown. (Cgsl and Cgc are marked with arrows because the overlapping part is not included in the cross section. Csc is approximately 0 because it has no overlapping part.) When the TFT is turned on (when calculating the gate feed-through voltage), in order to calculate Cgs, the overlapping area of ​​the gate electrode 2 · source electrode 4 is added with approximately half of the area of ​​the channel portion 6C, and in order to calculate Cgd, the overlapping area of ​​the gate electrode 2 · drain electrode 5 is added with approximately half of the area of ​​the channel portion 6C. When the TFT is turned off (when calculating parasitic capacitance), Cgs is related only to the overlapping area of ​​the gate electrode 2 and the source electrode 4, and Cgd is related only to the overlapping area of ​​the gate electrode 2 and the drain electrode 5. Cs is composed of the drain sub-electrode 5S / gate insulating film 3 / capacitor electrode 8.

[0090] However, among the above 8 types of electrostatic capacitance, Cgsl and Cgs, Cgp and Cgd are in a parallel relationship, so by including Cgsl in Cgs and Cgp in Cgd, there are 6 types. Cs among the 6 types is designed to be a larger value in order to maintain the potential. On the other hand, Cgs, Cgd, Csp, Csc, and Cgc are relatively small. In addition, Cgs and Cgd cannot be set to 0, and the size is the same as the order of magnitude. Although Csp, Csc or Cgc may be designed to be 0, even if it is larger, it is the same as Cgs and Cgd.

[0091] Among the six types of electrostatic capacitors, those directly connected to the column wiring 4L are Cgs, Csc, and Csp / / Cs, and those directly connected to the row wiring 2L are Cgs, Cgc, and Cgd / / Cs. Here, / / means a series circuit of capacitors, for example, Csp / / Cs=1 / (1 / Csp+1 / Cs).

[0092] exist Fig.36 , Fig.38 In the thin film transistor array, the number of column wirings 4L is M. The number of Cgs, Csc, and Csp connected to one column wiring 4L is N, that is, the electrostatic capacitance C=N(Cgs+Csc+Csp / / Cs).

[0093] The column wiring 4L changes voltage according to the data of each row, so the maximum charge and discharge occurs when the opposite polarity is written for each row. The amount of power consumed in one frame can be calculated as follows: Fig.33Calculate as follows. The voltage waveform of column wiring 4L is V4, the voltages of white writing and black writing are ±Vs, and the column wiring resistance (strictly speaking, the sum of the column wiring resistance and the series resistance (output resistance of the source driver, etc.)) is R. Fig.33 In the equation, the horizontal axis is time t. The voltage of the positive power supply of the source driver is Vp, the current is Ip, the voltage of the negative power supply is Vn, the current is In, the voltage of the GND line is V0=0, and the current is I0. The power consumption of the positive power supply is Pp, the power consumption of the negative power supply is Pn, and the power consumption of the GND line is P0=0. In order to simplify the formula, the integration range of each charging waveform is marked as t=0~∞, but as long as it is sufficiently greater than the time constant CR, for example, even if t=0~3CR covers 95% of the power, which is approximately the same as t=0~∞. The amount of power consumed in 1 frame in 1 column wiring is (2N-1)C(Vs) 2 Therefore, the amount of power consumed in one frame in M ​​source wirings is M×(2N-1)×N(Cgs+Csc+Csp / / Cs)×(Vs) 2 =MN(2N-1)(Cgs+Csc+Csp / / Cs)(Vs) 2 , when N is sufficiently greater than 1, it is considered to be 2MN 2 (Cgs+Csc+Csp / / Cs)(Vs) 2 The case where the amount of power consumed is the smallest is the case where the voltage of the column wiring is not changed, and the amount of power consumed in one frame is zero.

[0094] exist Fig.36 , Fig.38 In the thin film transistor array, the number of row wirings 2L is N. The number of Cgs, Cgc, and Cgd / / Cs connected to one row wiring is M, that is, the electrostatic capacitance C=M(Cgs+Cgc+Cgd / / Cs).

[0095] The row wiring 2L changes the voltage from off to on to off when each row is selected, so the number of charge and discharge times does not depend on the image, and the number of voltage changes is 2 times per frame. If the voltage change amount of the row wiring is ΔVg, the amount of power consumed per frame can be calculated as follows: Fig.34 The voltage waveform of row wiring 2L is V2. Fig.34 This is the case when the TFT is a p-channel. In the case of an n-channel, the voltage is opposite in sign, but the amount of electric power is the same. The positive voltage of the gate is Vp, the negative voltage is Vn, and the row wiring resistance (strictly speaking, the sum of the row wiring resistance and the series resistance (output resistance of the gate driver, etc.)) is R. Fig.34In the equation, the horizontal axis is time t. The voltage of the positive power supply of the gate driver 14 described later is Vp, the current is Ip, the voltage of the negative power supply is Vn, and the current is In. The power consumption of the positive power supply is Pp, and the power consumption of the negative power supply is Pn. In order to simplify the formula, the integral range of each charging waveform is marked as t = 0 ~ ∞, but as long as it is sufficiently greater than the time constant CR, for example, even if t = 0 ~ 3CR covers 95% of the power, which is approximately the same as t = 0 ~ ∞. The amount of power consumed in 1 frame in 1 row wiring is C (ΔVg) 2 Therefore, the amount of power consumed in one frame in N gate wirings is N×M(Cgs+Cgc+Cgd / / Cs)×(ΔVg) 2 =MN(Cgs+Cgc+Cgd / / Cs)(ΔVg) 2 .

[0096] exist Fig.36 , Fig.38 In the thin film transistor array, the number of pixels is MN. When the TFT is turned on, Cs and Cgd are charged, that is, the electrostatic capacitance C = Cs + Cgd. The maximum charge is when the display of all pixels is changed. In this case, if the voltage change of the column wiring is set to Vs, the amount of power consumed in one frame can be calculated as follows: Fig.35 The voltage waveform of the pixel is Vpixel. The TFT resistance (strictly speaking, the sum of the TFT resistance and the series resistance (column wiring resistance, etc.)) is R. Fig.35 In the equation, the horizontal axis is time t. When the drain voltage Vd=Vs is written, the current is Itft and the power consumption is Ptft. In order to simplify the formula, the integral range of the charging waveform is marked as t=0~∞, but as long as it is sufficiently greater than the time constant CR, for example, even if t=0~3CR covers 95% of the power, which is approximately the same as t=0~∞. The power consumed in one frame in a TFT is (Cs+Cgd)(Vs) 2 Among MN, MN(Cs+Cgd)(Vs) 2 The same value is also obtained when Vd=-Vs. The case where the power consumption is the smallest is the case where the potential of all pixels is not changed, and the power consumption is zero.

[0097] Based on the above, the maximum value of the power consumed in the wiring is 2MN per frame as long as N is sufficiently greater than 1. 2 (Cgs+Csc+Csp / / Cs)(Vs) 2 +MN(Cgs+Cgc+Cgd / / Cs)(ΔVg) 2 The power consumption caused by the change in column wiring voltage is equal to 2MN 2The power consumption caused by the row wiring voltage change is proportional to MN. (Cgs+Csc+Csp / / Cs) and (Cgs+Cgc+Cgd / / Cs) are of the same order of magnitude. Usually, the value of N is tens to hundreds, so the maximum power consumption caused by the column wiring voltage change is greater than the power consumption caused by the row wiring voltage change.

[0098] In the case of a TFT array having the same structure of the TFT portion and the storage capacitor portion other than the wiring, Fig.36 Cgs and Fig.38 Cgs, Fig.36 Csp and Fig.38 Csp, Fig.36 Cgd and Fig.38 Cgd, Fig.36 Cs and Fig.38 The Cs of the same. Therefore, the structure with smaller Csc (such as Fig.38 The capacitor wiring 8L is parallel to the column wiring 4L and the capacitor wiring 8L does not overlap the column wiring 4L) compared to the structure with a smaller Cgc (such as Fig.36 In that case, the capacitor wiring 8L is parallel to the row wiring 2L and the capacitor wiring 8L does not overlap with the row wiring 2L, and the maximum power consumption is smaller. In addition, the power consumption caused by the voltage change of the column wiring 4L is proportional to the square of N, so if N is smaller, the power consumption is smaller.

[0099] Therefore, if it is Figure 1A The structure of Fig.38 In comparison, the number of column wirings 4L increases to 2M, but the number of Cgs, Csc, and Csp connected to one column wiring 4L is reduced to N / 2, and the number of voltage changes per frame is also halved. Therefore, the maximum power consumption in the column wiring 4L is halved to (2M)(N / 2)(N-1)(Cgs+Csc+Csp)(Vs) 2 ≈MN 2 (Cgs+Csc+Csp)(Vs) 2 Thus, the power consumption in the column wiring 4L can be greatly reduced. In addition, the power consumption in the row wiring 2L is MN (Cgs + Cgc + Cgd / / Cs) (ΔVg) 2 But unchanged.

[0100] Next, if it is Figure 2AIn the structure of FIG1 , the number of capacitor wirings 8L is halved, and the number of overlaps between row wiring 2L and capacitor wiring 8L is halved. The capacitance between row wiring and capacitor wiring is basically caused by the overlap between wirings, so the number of Cgc connected to one row wiring 2L is M / 2. As a result, the power consumption in the row wiring 2L is reduced to MN (Cgs + Cgc / 2 + Cgd / / Cs) (ΔVg) 2 The maximum value of the power consumption in the column wiring 4L is (2M)(N / 2)(N-1)(Cgs+Csc+Csp)(Vs) which is the same as that in FIG. 1. 2 ≈MN 2 (Cgs+Csc+Csp)(Vs) 2 .

[0101] Moreover, in Figure 3A In the structure of Fig.38 In comparison, the number of column wirings 4L increases to 4M, but the number of Cgs and Csc connected to one column wiring 4L is reduced to N / 4. There are two column wirings 4L overlapping the pixel electrode 10, so the number of Csp is only reduced to N / 2. The number of column wiring voltage changes per frame is also N / 4, so the maximum power consumption in the column wiring 4L is reduced to (4M)(N / 4)(N / 2-1)(Cgs / 4+Csc / 4+Csp / 2)(Vs) 2 ≈MN 2 (Cgs+Csc+2Csp)(Vs) 2 / 2. This can significantly reduce the amount of power consumed in the column wiring 4L. In addition, the amount of power consumed in the row wiring 2L is the same as in FIG. 1: MN(Cgs+Cgc+Cgd / / Cs)(ΔVg) 2 .

[0102] On the other hand, the maximum value of the power consumed by TFT is MN(Cs+Cgd)(Vs) 2 The coefficient of is MN, and the maximum value of the power consumption in the column wiring 4L is MN 2 (Cgs+Csc+2Csp)(Vs) 2 The coefficient of / 2 is MN 2 , therefore, Cs is about the same as NCgs / 2, and if Cgd, Csc, and Csp are small, the amount of power consumed per frame in the TFT is about the same as the amount of power consumed per frame in the column wiring 4L.

[0103] However, in the case of electronic paper, the same image is often written across multiple frames. For example, when a horizontal stripe image is drawn across multiple frames, the power consumption MN of the column wiring 4L is 2 (Cgs+Csc+Csp)(Vs)2 / 2 is necessary in each frame during writing, but the power consumption of TFT is MN (Cs + Cgd) (Vs) 2 This is necessary only in the frame at the beginning of writing, and is not necessary in the frame in which the same voltage is written. Therefore, in the entire writing of several frames or tens of frames, the amount of power consumed in the column wiring 4L is greater.

[0104] According to the above, the wiring structure of TFT is Figure 1A In the case of Fig.38 Compared with other devices, it can reduce the amount of power consumption. Figure 2A , Figure 3A In the case of Figure 1A Further reduce power consumption.

[0105] In addition, the effective area of ​​M columns and N rows is expected to satisfy M ≥ N / 2. This is because, in the case of M < N / 2, as long as Fig.38 In the structure of , the rows and columns are changed to N columns and M rows, then the maximum power consumption in the wiring is ≈ 2NM 2 (Cgs+Csc+Csp / / Cs)(Vs) 2 +MN(Cgs+Cgc+Cgd / / Cs)(ΔVg) 2 , which is less than the maximum value of the power consumption in the wiring structure of FIG1≈MN 2 (Cgs+Csc+Csp / / Cs)(Vs) 2 +MN(Cgs+Cgc+Cgd / / Cs)(ΔVg) 2 That is, the present invention has a greater effect when M≥N / 2.

[0106] It is more desirable that the effective area of ​​M columns and N rows satisfies M ≥ N. This is because, when N / 2 ≤ M < N, if the structure of FIG. 1 is applied by replacing the rows and columns, the maximum power consumption in the column wiring ≈ NM 2 (Cgs+Csc+Csp / / Cs)(Vs) 2 +MN(Cgs+Cgc+Cgd / / Cs)(ΔVg) 2 , which is less than the maximum value of the power consumption in the wiring when the structure of FIG. 1 is applied without changing the rows and columns≈MN 2 (Cgs+Csc+Csp / / Cs)(Vs) 2 +MN(Cgs+Cgc+Cgd / / Cs)(ΔVg) 2 However, N / 2≤M<N may be used according to the relationship between the number of pixels M×N in the effective area and the number of outputs of the driver used.

[0107] exist Figure 1A , Figure 2A , Figure 3A In the structure of FIG. 1 , the length of the column wiring 4L corresponds to (N / 2) pixels, and the length of the capacitor wiring 8L parallel to the column wiring 4L corresponds to N pixels. On the other hand, the length of the capacitor wiring 8L of a conventional panel is as follows: Fig.36 In the case where the row wiring 2L is parallel to the row wiring 2L, the length of the row wiring 2L is the same. Fig.38 In this way, when the column wiring 4L is parallel, the length is the same as that of the column wiring 4L. The present invention has the following advantages: by making the length of the column wiring 4L correspond to the number of pixels (N / 2), the power consumption is suppressed, and by making the length of each capacitor wiring 8L correspond to the number of pixels N, the power supply to each capacitor wiring 8L is completed at least at one place of each capacitor wiring. Alternatively, by supplying power to each capacitor wiring from the top and bottom, there is an advantage that the voltage drop caused by the resistance of the capacitor wiring can be prevented.

[0108] exist Figure 1B , Figure 2B , Figure 3B In the structure, a capacitor connection wiring 8C is also provided in the center of the effective area. With this structure, it is very easy to supply power to the capacitor wiring 8L only by supplying power to the capacitor connection wiring 8C. In addition, the capacitor connection wiring 8C does not overlap with the row wiring 2L, and the capacitor connection wiring 8C does not overlap with the column wiring 4L, thereby preventing Cgc and Csc from increasing.

[0109] In addition, not only Figure 1A , Figure 2A , Figure 3A ,exist Figure 1B , Figure 2B , Figure 3B In the structure, although there is a capacitor connection wiring 8C in the center of the effective area, the pixel pitch P of the N / 2th row and the N / 2+1th row from above the effective area is set to be the same as the pixel pitch P of other rows. That is, the longitudinal spacing between adjacent pixels is made constant. As a result, the observer will not have a sense of incongruity such as the image being separated from top to bottom. In order to align the pixel pitch, the capacitor connection wiring 8C is preferably arranged in a layer lower than the pixel electrode 10. In the case where the capacitor connection wiring 8C overlaps with the pixel electrode 10 of the N / 2th row and the pixel electrode 10 of the N / 2+1th row, in order to offset the electrostatic capacitance caused by the overlap, it is better to reduce the area of ​​the capacitor electrode 8 of the N / 2th row and the N / 2+1th row. As described later, the capacitor connection wiring 8C can also be formed in parallel on multiple conductive layers.

[0110] (Details of the First Embodiment)

[0111] In the thin film transistor array of the first embodiment, power supply can be performed by connecting the gate power supply line 11 to one end of at least a portion of the plurality of row wirings 2L, connecting the first source power supply line 12 to one end of the column wiring 4L formed in one of the two regions on the side opposite to the other of the two regions, connecting the second source power supply line 12 to one end of the column wiring 4L formed in the other of the two regions on the side opposite to the one of the two regions, and connecting the capacitor power supply line 13 to both ends or one end of the capacitor wiring 8L. Furthermore, the other end of the row wiring 2L to which the gate power supply line 11 is connected may be connected to the gate intermediate line 11M, and connected to the row wiring 2L to which the gate power supply line 11 is not connected via the gate intermediate line 11M.

[0112] Specifically, in Figure 1A In the construction shown in , for example Figure 5A In this way, power can be supplied by connecting the gate power supply line 11 to the left or right end of the row wiring 2L, connecting the source power supply line 12 to the upper end of the upper region column wiring 4L, connecting another source power supply line 12 to the lower end of the lower region column wiring 4L, and connecting the capacitor power supply line 13 to the upper and lower ends of the capacitor wiring 8L. The gate power supply line 11 is connected to the output terminal 14O of the gate driver 14, the source power supply line 12 is connected to the output terminal 15O of ​​the source driver 15, and the capacitor power supply line 13 is connected to the common electrode potential or the output terminal 16O or the GND terminal of the capacitor power supply 16. (The common electrode potential refers to the potential applied to the opposing electrode in a display device having a structure in which a display medium is sandwiched between a thin film transistor array and an opposing substrate having an opposing electrode. It is suitable for use in the case where the display medium is a liquid crystal. On the other hand, in the case where the display medium is an electrophoretic particle, it is suitable to use the capacitor power supply potential, the GND potential, or the common electrode potential.)

[0113] exist Figure 5A In the case of , even outside the effective area, the wiring overlaps less, and the power consumption outside the effective area can be suppressed. Figure 5A In FIG. 1 , the only place where the wirings overlap each other outside the effective area is the intersection (2(M-1)) of the source power supply line 12 and the capacitor power supply line 13. Figure 5A The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Figure 5A In the embodiment, there are two gate drivers 14 and two source drivers 15, but the present invention is not limited to this. For example, one gate driver and two source drivers may be used, or two or one gate-source integrated driver may be used.

[0114] Or, in Figure 1A In the structure shown, for example Figure 5BIn this way, the following power supply can be performed: the gate power supply line 11 is connected to one end of the left end or the right end of one of the upper region row wiring 2L or the lower region row wiring 2L, one end of the gate middle line 11M is connected to the other end of the left end or the right end of one of the upper region row wiring 2L or the lower region row wiring 2L, the other end of the gate middle line 11M is connected to the left end or the right end of the other row wiring 2L of the upper region row wiring 2L or the lower region row wiring 2L, the source power supply line 12 is connected to the upper end of the upper region column wiring 4L, the other source power supply line 12 is connected to the lower end of the lower region column wiring 4L, and the capacitor power supply line 13 is connected to the lower end or the upper end of the capacitor wiring 8L. The gate power supply line 11 is connected to the output terminal 14O of the gate driver 14, the source power supply line 12 is connected to the output terminal 15O of ​​the source driver 15, and the capacitor power supply line 13 is connected to the common electrode potential or the output terminal 16O of the capacitor power supply 16 or the GND terminal.

[0115] In this case, outside the effective area, wiring overlaps less frequently, and power consumption outside the effective area can be suppressed. Figure 5B In FIG. 1 , the only place where the wirings overlap with each other outside the effective area is the intersection (M) of the source power supply line 12 and the capacitor power supply line 13. Figure 5B The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Figure 5B In the embodiment, the gate driver 14 is one and the source driver 15 is separated into two, but the present invention is not limited to this. For example, one gate driver and one source driver may be used, or one gate-source integrated driver may be used.

[0116] Figure 6 (a)~ Figure 6 (c) shows that Figure 4A The manufacturing process of a thin film transistor array includes, on an insulating substrate 1, a first conductive layer having a gate electrode 2 and a row wiring 2L, a gate insulating film 3, a second conductive layer having a source electrode 4 and a column wiring 4L and a drain electrode 5, an interlayer insulating film 7, a third conductive layer having a capacitor electrode 8 and a capacitor wiring 8L, a capacitor insulating film 9, and a fourth conductive layer having a pixel electrode 10. The top view above shows the amount of one column of pixels in the N / 2th row, the N / 2+1th row, and the N / 2+2th row from the top of the effective area, and the cross-sectional view below shows the cross-sectional view along the dotted line of the top view.

[0117] Figure 6(a) shows a state in which a gate electrode 2 and a row wiring 2L are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, a source electrode 4 and a column wiring 4L and a drain electrode 5 and a drain connection wiring 5C and a drain pad 5P are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway at the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway at the pixel of the N / 2+1th row. Figure 6 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Figure 6 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0118] Figure 6 (b) shows that Figure 6 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8 and a capacitor wiring 8L on it. Figure 6 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L.

[0119] Figure 6 (c) shows that Figure 6 The state shown in (b) has a structure in which a capacitor insulating film 9 is provided thereon and a pixel electrode 10 is provided thereon. The pixel electrode 10 is electrically connected to the drain pad 5P via an opening of the capacitor insulating film 9 and an opening of the interlayer insulating film 7 .

[0120] Alternatively, in the thin film transistor arrays of the first to third embodiments, when there is a capacitor connection wiring 8C between the upper region and the lower region of the active region, power supply can be performed by connecting the gate power supply line 11 to one end of at least a portion of the plurality of row wirings 2L, connecting the first source power supply line 12 to one end of the column wiring 4L formed in one of the two regions on the side opposite to the other of the two regions, connecting the second source power supply line 12 to one end of the column wiring 4L formed in the other of the two regions on the side opposite to the one of the two regions, and connecting the capacitor power supply line 13 to one end or both ends of the capacitor connection wiring 8C. Furthermore, the other end of the row wiring 2L to which the gate power supply line 11 is connected may be connected to the gate middle line 11M, and connected to the row wiring 2L to which the gate power supply line 11 is not connected via the gate middle line 11M.

[0121] Specifically, in Figure 1B In the construction shown in , for example Figure 5C In this way, power can be supplied by connecting the gate power supply line 11 to the left or right end of the row wiring 2L, connecting the source power supply line 12 to the upper end of the upper region column wiring 4L, connecting another source power supply line 12 to the lower end of the lower region column wiring 4L, and connecting the capacitor power supply line 13 to the left or right end of the capacitor connection wiring 8C. The gate power supply line 11 is connected to the output terminal 14O of the gate driver 14, the source power supply line 12 is connected to the output terminal 15O of ​​the source driver 15, and the capacitor power supply line 13 is connected to the common electrode potential or the output terminal 16O or the GND terminal of the capacitor power supply 16. (The common electrode potential refers to the potential applied to the opposing electrode in a display device having a structure in which a display medium is sandwiched between a thin film transistor array and an opposing substrate having an opposing electrode. It is suitable for use in the case where the display medium is a liquid crystal. On the other hand, in the case where the display medium is an electrophoretic particle, it is suitable to use the capacitor power supply potential, the GND potential, or the common electrode potential.)

[0122] In this case, it is possible to completely eliminate the overlapping portion of the wirings outside the effective area, and to suppress the amount of power consumption outside the effective area. Figure 5C The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Figure 5C In the embodiment, there are two gate drivers 14 and two source drivers 15, but the present invention is not limited to this. For example, one gate driver and two source drivers may be used, or two or one gate-source integrated driver may be used.

[0123] or in Figure 1B In the structure shown, for example Figure 5DIn this way, the following power supply can be performed: the gate power supply line 11 is connected to one end of the left end or the right end of one side of the upper area row wiring 2L or the lower area row wiring 2L, one end of the gate middle line 11M is connected to the other end of the left end or the right end of one side of the upper area row wiring 2L or the lower area row wiring 2L, the other end of the gate middle line 11M is connected to the left end or the right end of the other side of the upper area row wiring 2L or the lower area row wiring 2L, the source power supply line 12 is connected to the upper end of the upper area column wiring 4L, the other source power supply line 12 is connected to the lower end of the lower area column wiring 4L, and the capacitor power supply line 13 is connected to the left end or the right end of the capacitor connection wiring 8C. The gate power supply line 11 is connected to the output terminal 14O of the gate driver 14, the source power supply line 12 is connected to the output terminal 15O of ​​the source driver 15, and the capacitor power supply line 13 is connected to the common electrode potential or the output terminal 16O of the capacitor power supply 16 or the GND terminal.

[0124] In this case, it is possible to completely eliminate the overlapping portion of the wirings outside the effective area, and to suppress the amount of power consumption outside the effective area. Figure 5D The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Figure 5D In the embodiment, the gate driver 14 is one and the source driver 15 is separated into two, but the present invention is not limited to this. For example, one gate driver and one source driver may be used, or one gate-source integrated driver may be used.

[0125] Figure 7 (a)~ Fig.13 (c) shows that Figure 4A The manufacturing process of a thin film transistor array includes, on an insulating substrate 1, a first conductive layer having a gate electrode 2 and a row wiring 2L, a gate insulating film 3, a second conductive layer having a source electrode 4 and a column wiring 4L and a drain electrode 5, an interlayer insulating film 7, a third conductive layer having a capacitor electrode 8 and a capacitor wiring 8L, a capacitor insulating film 9, and a fourth conductive layer having a pixel electrode 10. The top view above shows the amount of one column of pixels in the N / 2th row, the N / 2+1th row, and the N / 2+2th row from the top of the effective area, and the cross-sectional view below shows the cross-sectional view along the dotted line of the top view.

[0126] Figure 7(a) shows a state in which a gate electrode 2 and a row wiring 2L are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, a source electrode 4 and a column wiring 4L and a drain electrode 5 and a drain connection wiring 5C and a drain pad 5P are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway at the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway at the pixel of the N / 2+1th row. Figure 7 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Figure 7 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0127] Figure 7 (b) shows that Figure 7 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8, a capacitor wiring 8L, and a capacitor connecting wiring 8C3 on it. Figure 7 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C3 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, and the capacitor wiring 8L at the midpoint also serves as the capacitor connection wiring 8C3, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C3 function as a whole. The capacitor connection wiring 8C3 does not overlap with the row wiring 2L and the column wiring 4L.

[0128] Figure 7 (c) shows that Figure 7 The state shown in (b) of FIG. 1 is a structure in which a capacitor insulating film 9 is provided on the top and a pixel electrode 10 is provided on the top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9 and the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrode 10 and the capacitor connection wiring 8C3 in the N / 2th row and the N / 2+1th row, Figure 7By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0129] Figure 8 (a) shows a state in which a gate electrode 2, a row wiring 2L, a gate insulating film 3 thereon, a semiconductor pattern 6 thereon, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, and a capacitor connection wiring 8C2 are provided on an insulating substrate 1. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway at the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway at the pixel of the N / 2+1th row. The capacitor connection wiring 8C2 does not overlap with the row wiring 2L and the column wiring 4L. Figure 8 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring as a whole. Figure 8 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring as a whole.

[0130] Figure 8 (b) shows that Figure 8 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8 and a capacitor wiring 8L on it. Figure 8 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. When the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, the capacitor wiring 8L at the midpoint at this time is electrically connected to the capacitor connection wiring 8C2 of the second conductive layer via the opening of the interlayer insulating film 7.

[0131] Figure 8 (c) shows that Figure 8The state shown in (b) of FIG. 1 is a structure in which a capacitor insulating film 9 is provided on the top and a pixel electrode 10 is provided on the top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9 and the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrode 10 and the capacitor connection wiring 8C2 in the N / 2th row and the N / 2+1th row, Figure 8 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0132] Fig. 9 (a) shows a state in which a gate electrode 2, a row wiring 2L, a gate insulating film 3 thereon, a semiconductor pattern 6 thereon, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, and a capacitor connection wiring 8C2 are provided on an insulating substrate 1. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway at the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway at the pixel of the N / 2+1th row. The capacitor connection wiring 8C2 does not overlap with the row wiring 2L and the column wiring 4L. Fig. 9 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig. 9 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0133] Fig. 9 (b) shows that Fig. 9 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8, a capacitor wiring 8L, and a capacitor connecting wiring 8C3 on it. Fig. 9In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C3 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, and the capacitor wiring 8L at the midpoint also serves as the capacitor connection wiring 8C3, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C3 function as a whole. In addition, the capacitor wiring 8L at the midpoint is electrically connected to the capacitor connection wiring 8C2 of the second conductive layer via the opening of the interlayer insulating film 7.

[0134] Fig. 9 (c) shows that Fig. 9 The state shown in (b) of FIG. 1 is a structure in which a capacitor insulating film 9 is provided on the top and a pixel electrode 10 is provided on the top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9 and the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrode 10 and the capacitor connection wiring 8C3 in the N / 2th row and the N / 2+1th row, Fig. 9 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0135] Fig.10 (a) shows a state in which a gate electrode 2, a row wiring 2L, and a capacitor connection wiring 8C1 are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, and a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, and a drain pad 5P are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C1 does not overlap with the row wiring 2L and the column wiring 4L. Fig.10 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.10In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0136] Fig.10 (b) shows that Fig.10 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8 and a capacitor wiring 8L on it. Fig.10 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. When the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, the midpoint capacitor wiring 8L at this time is electrically connected to the capacitor connection wiring 8C1 via the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3.

[0137] Fig.10 (c) shows that Fig.10 The state shown in (b) of FIG. 1 is a structure in which a capacitor insulating film 9 is provided on the top and a pixel electrode 10 is provided on the top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9 and the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrode 10 and the capacitor connection wiring 8C1 in the N / 2th row and the N / 2+1th row, Fig.10 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0138] Fig.11 (a) shows a state in which a gate electrode 2, a row wiring 2L, and a capacitor connection wiring 8C1 are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, and a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C2 of the second conductive layer is electrically connected to the capacitor connection wiring 8C1 of the first conductive layer via the opening of the gate insulating film 3. In addition, the capacitor connection wiring 8C1~2 does not overlap with the row wiring 2L and the column wiring 4L. Fig.11In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.11 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0139] Fig.11 (b) shows that Fig.11 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8 and a capacitor wiring 8L on it. Fig.11 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L as a whole serve as the capacitor wiring. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. When the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, the capacitor wiring 8L at the midpoint at this time is electrically connected to the capacitor connection wiring 8C2 via the opening of the interlayer insulating film 7.

[0140] Fig.11 (c) shows that Fig.11 The state shown in (b) of FIG. 1 is a structure in which a capacitor insulating film 9 is provided on the top and a pixel electrode 10 is provided on the top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9 and the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrode 10 and the capacitor connection wiring 8C2 in the N / 2th row and the N / 2+1th row, Fig.11 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0141] Fig.12(a) shows a state in which a gate electrode 2, a row wiring 2L, and a capacitor connection wiring 8C1 are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, and a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, and a drain pad 5P are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C1 does not overlap with the row wiring 2L and the column wiring 4L. Fig.12 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.12 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0142] Fig.12 (b) shows that Fig.12 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8, a capacitor wiring 8L, and a capacitor connecting wiring 8C3 on it. Fig.12 In the state shown in (b), the capacitor wiring 8L connects a plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a capacitor wiring as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C3 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, and the capacitor wiring 8L at the midpoint serves as the capacitor connection wiring 8C3, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C3 function as a capacitor connection wiring 8C3 as a whole. In addition, the capacitor wiring 8L at the midpoint is electrically connected to the capacitor connection wiring 8C1 of the first conductive layer via the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3. The capacitor connection wirings 8C1 and 8C3 do not overlap with the row wiring 2L and the column wiring 4L.

[0143] Fig.12 (c) shows that Fig.12The state shown in (b) of FIG. 1 is a structure in which a capacitor insulating film 9 is provided on the top and a pixel electrode 10 is provided on the top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9 and the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrode 10 and the capacitor connection wiring 8C3 in the N / 2th row and the N / 2+1th row, Fig.12 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0144] Fig.13 (a) shows a state in which a gate electrode 2, a row wiring 2L, and a capacitor connection wiring 8C1 are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, and a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C2 of the second conductive layer is electrically connected to the capacitor connection wiring 8C1 of the first conductive layer via an opening in the gate insulating film. In addition, the capacitor connection wiring 8C1~2 does not overlap with the row wiring 2L and the column wiring 4L. Fig.13 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.13 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0145] Fig.13 (b) shows that Fig.13 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8, a capacitor wiring 8L, and a capacitor connecting wiring 8C3 on it. Fig.13In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C3 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, and the capacitor wiring 8L at the midpoint also serves as the capacitor connection wiring 8C3, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C3 function as a whole. In addition, the capacitor wiring 8L at the midpoint is electrically connected to the capacitor connection wiring 8C2 of the second conductive layer via the opening of the interlayer insulating film 7.

[0146] Fig.13 (c) shows that Fig.13 The state shown in (b) of FIG. 1 is a structure in which a capacitor insulating film 9 is provided on the top and a pixel electrode 10 is provided on the top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9 and the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrode 10 and the capacitor connection wiring 8C3 in the N / 2th row and the N / 2+1th row, Fig.13 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0147] Fig.14 (a)~ Fig. 20 (c) shows that Figure 4B The manufacturing process of a thin film transistor array includes, on an insulating substrate 1, a first conductive layer having a source electrode 4, a column wiring 4L, and a drain electrode 5, a gate insulating film 3, a second conductive layer having a gate electrode 2 and a row wiring 2L, an interlayer insulating film 7, a third conductive layer having a capacitor electrode 8 and a capacitor wiring 8L, a capacitor insulating film 9, and a fourth conductive layer having a pixel electrode 10. The top view above shows pixels in the N / 2th row, the N / 2+1th row, and the N / 2+2th row from the top of the effective area, and the cross-sectional view below is a cross-sectional view along the dotted line of the top view.

[0148] Fig.14(a) shows a state in which a semiconductor pattern 6 is provided on an insulating substrate 1, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P are provided thereon, a gate insulating film 3 is provided thereon, and a gate electrode 2, a row wiring 2L are provided thereon. The row wiring 2L extends in the transverse direction. The column wiring 4L extends in the longitudinal direction, and the column wiring 4L in the upper area ends halfway at the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway at the pixel of the N / 2+1th row. Fig.14 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.14 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0149] Fig.14 (b) shows that Fig.14 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8, a capacitor wiring 8L, and a capacitor connecting wiring 8C3 on it. Fig.14 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C3 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, and the capacitor wiring 8L at the midpoint also serves as the capacitor connection wiring 8C3, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C3 function as a whole. The capacitor connection wiring 8C3 does not overlap with the row wiring 2L and the column wiring 4L.

[0150] Fig.14 (c) shows that Fig.14 The state shown in (b) of FIG. 1 has a capacitor insulating film 9 on top and a pixel electrode 10 on top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9, the opening of the interlayer insulating film 7, and the opening of the gate insulating film 3. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 and the capacitor connection wiring 8C3 in the N / 2th row and the N / 2+1th row, Fig.14By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0151] Fig.15 (a) shows a state in which a semiconductor pattern 6 is provided on an insulating substrate 1, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P is provided thereon, a gate insulating film 3 is provided thereon, and a gate electrode 2, a row wiring 2L, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C2 does not overlap with the row wiring 2L and the column wiring 4L. Fig.15 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.15 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0152] Fig.15 (b) shows that Fig.15 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8 and a capacitor wiring 8L on it. Fig.15 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L as a whole serve as the capacitor wiring. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. When the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, the capacitor wiring 8L at the midpoint at this time is electrically connected to the capacitor connection wiring 8C2 via the opening of the interlayer insulating film 7.

[0153] Fig.15 (c) shows that Fig.15The state shown in (b) of FIG. 1 has a capacitor insulating film 9 on top and a pixel electrode 10 on top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9, the opening of the interlayer insulating film 7, and the opening of the gate insulating film 3. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 and the capacitor connection wiring 8C2 in the N / 2th row and the N / 2+1th row, Fig.15 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0154] Fig.16 (a) shows a state in which a semiconductor pattern 6 is provided on an insulating substrate 1, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P is provided thereon, a gate insulating film 3 is provided thereon, and a gate electrode 2, a row wiring 2L, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C2 does not overlap with the row wiring 2L and the column wiring 4L. Fig.16 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.16 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0155] Fig.16 (b) shows that Fig.16 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8, a capacitor wiring 8L, and a capacitor connecting wiring 8C3 on it. Fig.16In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C3 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wirings, and the capacitor wiring 8L at the midpoint serves as the capacitor connection wiring 8C3, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C3 function as a whole. In addition, the capacitor wiring 8L at the midpoint is electrically connected to the capacitor connection wiring 8C2 of the second conductive layer via the opening of the interlayer insulating film 7.

[0156] Fig.16 (c) shows that Fig.16 The state shown in (b) of FIG. 1 has a capacitor insulating film 9 on top and a pixel electrode 10 on top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9, the opening of the interlayer insulating film 7, and the opening of the gate insulating film 3. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 and the capacitor connection wiring 8C3 in the N / 2th row and the N / 2+1th row, Fig.16 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0157] Fig.17 (a) shows a state in which a semiconductor pattern 6 is provided on an insulating substrate 1, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, and a capacitor connection wiring 8C1 are provided thereon, a gate insulating film 3 is provided thereon, and a gate electrode 2, and a row wiring 2L are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C1 does not overlap with the row wiring 2L and the column wiring 4L. Fig.17 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.17In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0158] Fig.17 (b) shows that Fig.17 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8 and a capacitor wiring 8L on it. Fig.17 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. When the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, the midpoint capacitor wiring 8L at this time is electrically connected to the capacitor connection wiring 8C1 of the first conductive layer via the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3.

[0159] Fig.17 (c) shows that Fig.17 The state shown in (b) of FIG. 1 has a capacitor insulating film 9 on top and a pixel electrode 10 on top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9, the opening of the interlayer insulating film 7, and the opening of the gate insulating film 3. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 and the capacitor connection wiring 8C1 in the N / 2th row and the N / 2+1th row, Fig.17 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0160] Fig.18 (a) shows a state in which a semiconductor pattern 6 is provided on an insulating substrate 1, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, and a capacitor connection wiring 8C1 are provided thereon, a gate insulating film 3 is provided thereon, and a gate electrode 2, a row wiring 2L, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C2 of the second conductive layer is electrically connected to the capacitor connection wiring 8C1 of the first conductive layer via an opening in the gate insulating film 3. In addition, the capacitor connection wiring 8C1~2 does not overlap with the row wiring 2L and the column wiring 4L. Fig.18 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.18 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0161] Fig.18 (b) shows that Fig.18 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8 and a capacitor wiring 8L on it. Fig.18 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L as a whole serve as the capacitor wiring. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. When the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, the capacitor wiring 8L at the midpoint at this time is electrically connected to the capacitor connection wiring 8C2 via the opening of the interlayer insulating film 7.

[0162] Fig.18 (c) shows that Fig.18 The state shown in (b) of FIG. 1 has a capacitor insulating film 9 on top and a pixel electrode 10 on top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9, the opening of the interlayer insulating film 7, and the opening of the gate insulating film 3. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 and the capacitor connection wiring 8C2 in the N / 2th row and the N / 2+1th row, Fig.18 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0163] Fig.19(a) shows a state in which a semiconductor pattern 6 is provided on an insulating substrate 1, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, a capacitor connection wiring 8C1 is provided thereon, a gate insulating film 3 is provided thereon, and a gate electrode 2, a row wiring 2L is provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway at the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway at the pixel of the N / 2+1th row. The capacitor connection wiring 8C1 does not overlap with the row wiring 2L and the column wiring 4L. Fig.19 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.19 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0164] Fig.19 (b) shows that Fig.19 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8, a capacitor wiring 8L, and a capacitor connecting wiring 8C3 on it. Fig.19 In the state shown in (b), the capacitor wiring 8L connects a plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a capacitor wiring as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C3 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wirings, and the capacitor wiring 8L at the midpoint serves as the capacitor connection wiring 8C3, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C3 function as a capacitor connection wiring 8C3 as a whole. In addition, the capacitor wiring 8L at the midpoint is electrically connected to the capacitor connection wiring 8C1 of the first conductive layer via the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3. The capacitor connection wirings 8C1 and 8C3 do not overlap with the row wiring 2L and the column wiring 4L.

[0165] Fig.19 (c) shows that Fig.19The state shown in (b) of FIG. 1 has a capacitor insulating film 9 on top and a pixel electrode 10 on top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9, the opening of the interlayer insulating film 7, and the opening of the gate insulating film 3. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 and the capacitor connection wiring 8C3 in the N / 2th row and the N / 2+1th row, Fig.19 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0166] Fig. 20 (a) shows a state in which a semiconductor pattern 6 is provided on an insulating substrate 1, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, and a capacitor connection wiring 8C1 are provided thereon, a gate insulating film 3 is provided thereon, and a gate electrode 2, a row wiring 2L, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C2 of the second conductive layer is electrically connected to the capacitor connection wiring 8C1 of the first conductive layer via an opening in the gate insulating film. In addition, the capacitor connection wirings 8C1 and 8C2 do not overlap with the row wiring 2L and the column wiring 4L. Fig. 20 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig. 20 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0167] Fig. 20 (b) shows that Fig. 20 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8, a capacitor wiring 8L, and a capacitor connecting wiring 8C3 on it. Fig. 20In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C3 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wirings, and the capacitor wiring 8L at the midpoint serves as the capacitor connection wiring 8C3, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C3 function as a whole. In addition, the capacitor wiring 8L at the midpoint is electrically connected to the capacitor connection wiring 8C2 of the second conductive layer via the opening of the interlayer insulating film 7.

[0168] Fig. 20 (c) shows that Fig. 20 The state shown in (b) of FIG. 1 has a capacitor insulating film 9 on top and a pixel electrode 10 on top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9, the opening of the interlayer insulating film 7, and the opening of the gate insulating film 3. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 and the capacitor connection wiring 8C3 in the N / 2th row and the N / 2+1th row, Fig.13 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0169] Fig.21 (a)~ Fig.23 (b) shows that Figure 4C The manufacturing process of a thin film transistor array includes a first conductive layer having a gate electrode 2, a row wiring 2L, and a drain sub-electrode 5S, a gate insulating film 3, a second conductive layer having a source electrode 4, a column wiring 4L, a drain electrode 5, and a capacitor electrode 8, an interlayer insulating film 7, and a third conductive layer having a pixel electrode 10 on an insulating substrate 1, like a TFT. The top view above shows pixels in the N / 2th row, the N / 2+1th row, and the N / 2+2th row from the top of the effective area, and the cross-sectional view below is a cross-sectional view along the dotted line of the top view.

[0170] Fig.21(a) shows a state in which a gate electrode 2, a row wiring 2L, and a drain sub-electrode 5S are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, and a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, a capacitor electrode 8, a capacitor wiring 8L, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The drain electrode 5 is connected to the drain sub-electrode 5S via an opening in the gate insulating film 3, and the drain sub-electrode 5S overlaps with the capacitor electrode 8 via the gate insulating film 3. Fig.21 In the state shown in (a), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C2 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, and the capacitor wiring 8L at the midpoint also serves as the capacitor connection wiring 8C2, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C2 function as a whole. The capacitor connection wiring 8C2 does not overlap with the row wiring 2L and the column wiring 4L.

[0171] Fig.21 (b) shows that Fig.21 The structure shown in (a) has an interlayer insulating film 7 on top and a pixel electrode 10 on top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 and the capacitor connection wiring 8C2 in the N / 2th row and the N / 2+1th row, Fig.21 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (a) of FIG. 8 , it is possible to keep Cs the same.

[0172] Fig. 22(a) shows a state in which a gate electrode 2, a row wiring 2L, a drain sub-electrode 5S, and a capacitor connection wiring 8C1 are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, and a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, and a drain pad 5P are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C1 does not overlap with the row wiring 2L and the column wiring 4L. Fig. 22 In the state shown in (a), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. When the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, the capacitor wiring 8L at the midpoint at this time is electrically connected to the capacitor connection wiring 8C1 of the first conductive layer via the opening of the gate insulating film 3.

[0173] Fig. 22 (b) shows that Fig. 22 The structure shown in (a) has an interlayer insulating film 7 on top and a pixel electrode 10 on top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 and the capacitor connection wiring 8C1 in the N / 2th row and the N / 2+1th row, Fig. 22 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (a) of FIG. 8 , it is possible to keep Cs the same.

[0174] Fig.23 (a) shows a state in which a gate electrode 2, a row wiring 2L, a drain sub-electrode 5S, and a capacitor connection wiring 8C1 are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, and a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway at the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway at the pixel of the N / 2+1th row. Fig.23In the state shown in (a), the capacitor wiring 8L connects a plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a capacitor wiring as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C2 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wirings, and the capacitor wiring 8L at the midpoint serves as the capacitor connection wiring 8C2, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C2 function as a capacitor connection wiring 8C2 as a whole. In addition, the capacitor wiring 8L at the midpoint is electrically connected to the capacitor connection wiring 8C1 of the first conductive layer via the opening of the gate insulating film. The capacitor connection wirings 8C1 and 8C2 do not overlap with the row wiring 2L and the column wiring 4L.

[0175] Fig.23 (b) shows that Fig.23 The structure shown in (a) of FIG. 1 has an interlayer insulating film 7 and a pixel electrode 10 thereon. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 of the N / 2th row and the N / 2th row+1 and the capacitor connection wiring 8C2, Fig.23 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (a) of FIG. 8 , it is possible to keep Cs the same.

[0176] Fig.24 (a)~ Fig.26 (b) shows that Figure 4D The manufacturing process of a thin film transistor array includes a first conductive layer having a source electrode 4, a column wiring 4L, a drain electrode 5, and a drain connecting wiring 5C, a gate insulating film 3, a second conductive layer having a gate electrode 2, a row wiring 2L, and a drain sub-electrode 5S, an interlayer insulating film 7, and a third conductive layer having a pixel electrode 10 on an insulating substrate 1 in this order, like a TFT. The top view above shows pixels in the N / 2th row, the N / 2+1th row, and the N / 2+2th row from the top of the effective area, and the cross-sectional view below is a cross-sectional view along the dotted line of the top view.

[0177] Fig.24(a) shows a state in which a semiconductor pattern 6 is provided on an insulating substrate 1, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, a capacitor electrode 8, a capacitor wiring 8L, a capacitor connection wiring 8C1, a gate insulating film 3, and a gate electrode 2, a row wiring 2L, and a drain sub-electrode 5S are provided above the insulating substrate 1. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The drain electrode 5 is connected to the drain sub-electrode 5S via an opening in the gate insulating film 3, and the drain sub-electrode 5S overlaps with the capacitor electrode 8 via the gate insulating film 3. Fig.24 In the state shown in (a), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C1 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, and the capacitor wiring 8L at the midpoint serves as the capacitor connection wiring 8C1, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C1 function as a whole. The capacitor connection wiring 8C1 does not overlap with the row wiring 2L and the column wiring 4L.

[0178] Fig.24 The state shown in (b) is shown in Fig.24 The structure shown in (a) of FIG. 1 has an interlayer insulating film 7 on top and a pixel electrode 10 on top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 and the capacitor connection wiring 8C1 in the N / 2th row and the N / 2+1th row, Fig.24 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (a) of FIG. 8 , it is possible to keep Cs the same.

[0179] Fig.25(a) shows a state in which a semiconductor pattern 6 is provided on an insulating substrate 1, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P are provided thereon, a gate insulating film 3 is provided thereon, and a gate electrode 2, a row wiring 2L, a drain sub-electrode 5S, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C2 does not overlap with the row wiring 2L and the column wiring 4L. Fig.25 In the state shown in (a), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L as a whole serve as the capacitor wiring. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. When the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, the capacitor wiring 8L at the midpoint at this time is electrically connected to the capacitor connection wiring 8C2 via the opening of the gate insulating film 3. The capacitor connection wiring 8C2 does not overlap with the row wiring 2L and the column wiring 4L.

[0180] Fig.25 (b) shows that Fig.25 The state shown in (a) of FIG. 1 is provided with an interlayer insulating film 7 on the top and a pixel electrode 10 on the top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 and the capacitor connection wiring 8C2 in the N / 2th row and the N / 2+1th row, Fig.25 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (a) of FIG. 8 , it is possible to keep Cs the same.

[0181] Fig.26 (a) shows a state in which a semiconductor pattern 6 is provided on an insulating substrate 1, a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, and a capacitor connection wiring 8C1 are provided thereon, a gate insulating film 3 is provided thereon, and a gate electrode 2, a row wiring 2L, a drain sub-electrode 5S, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway at the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway at the pixel of the N / 2+1th row. Fig.26In the state shown in (a), the capacitor wiring 8L connects a plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a capacitor wiring as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C1 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wirings, and the capacitor wiring 8L at the midpoint serves as the capacitor connection wiring 8C1, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C1 function as a capacitor connection wiring 8C1 as a whole. In addition, the capacitor wiring 8L at the midpoint is electrically connected to the capacitor connection wiring 8C2 of the second conductive layer via the opening of the gate insulating film. The capacitor connection wirings 8C1 and 8C2 do not overlap with the row wiring 2L and the column wiring 4L.

[0182] Fig.26 (b) shows that Fig.26 The structure shown in (a) has an interlayer insulating film 7 on it and a pixel electrode 10 on it. The pixel electrode 10 is electrically connected to the drain pad 5P through the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3. In addition, since Cs increases according to the amount of overlap between the pixel electrodes 10 of the N / 2th row and the N / 2th row+1 and the capacitor connection wiring 8C2, Fig.26 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (a) of FIG. 8 , it is possible to keep Cs the same.

[0183] In addition, although an example is shown in which the source electrode 4 and the drain electrode 5 are located in the top contact of the upper layer of the semiconductor pattern 6, the source electrode 4 and the drain electrode 5 can also be located in the bottom contact of the lower layer of the semiconductor pattern 6, or the source electrode 4 and the drain electrode 5 can be coplanar with the semiconductor pattern 6 on the same layer.

[0184] As the material of the insulating substrate 1, inorganic substances such as glass, and organic substances such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polycarbonate, polyimide (PI), polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE), polypropylene (PP), nylon (Ny), and epoxy resin can be used.

[0185] As materials for the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, metals such as Al, Ag, Cu, Cr, Ni, Mo, Au, Pt, and Nb, conductive oxides such as ITO, carbon, and conductive polymers can be used. As methods for making the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, ink can be printed and fired, or they can be formed by photolithography, etching, and resist stripping after full film formation by sputtering or the like. Alternatively, they can be formed by resist printing, etching, and resist stripping after full film formation by sputtering or the like.

[0186] As materials for the gate insulating film 3, the interlayer insulating film 7, and the capacitor insulating film 9, inorganic substances such as SiO2, SiON, and SiN, and organic substances such as polyvinylphenol (PVP) and epoxy resin can be used. The gate insulating film 3, the interlayer insulating film 7, and the capacitor insulating film 9 can be obtained by vacuum film formation such as sputtering and CVD, or coating and firing of a solution.

[0187] As the material of the semiconductor pattern 6, inorganic semiconductors such as amorphous Si and poly-Si, organic semiconductors such as polythiophene, acene, and allylamine, and oxide semiconductors such as In2O3, Ga2O3, ZnO, SnO2, InGaZnO, InGaSnO, and InSnZnO can be used. As a method for making the semiconductor pattern 6, it is also possible to form the semiconductor pattern 6 by photolithography, etching, and resist stripping after film formation by plasma CVD or the like. Alternatively, there is also a method of printing and firing a solution by inkjet, dispenser, relief printing, or the like.

[0188] In addition, Figure 5A to Figure 5D In the construction shown in Fig.37 , Fig.39 Compared with the structure shown in , the number of required source driver output terminals 15O is doubled. However, since the number of pixels handled by each source driver output terminal 15O is halved, even if the number of source driver output terminals 15O is doubled, the power consumption in the source driver is smaller than the multiple and is roughly the same. In addition, the power consumption in the source driver is smaller than the amount of power consumption in the wiring, so even if the power consumption in the source driver increases, the overall power consumption is reduced.

[0189] (Details of the Second Embodiment)

[0190] In the thin film transistor array of the second embodiment, power supply can be provided by connecting the gate power supply line 11 to one end of at least a portion of the plurality of row wirings 2L, connecting the first source power supply line 12 to one end of the column wiring 4L formed in one of the two regions on the side opposite to the other of the two regions, connecting the second source power supply line 12 to one end of the column wiring 4L formed in the other of the two regions on the side opposite to the one of the two regions, and connecting the capacitor power supply line 13 to both ends or one end of the capacitor wiring 8L. Furthermore, the other end of the row wiring 2L to which the gate power supply line 11 is connected may be connected to the gate middle line 11M, and connected to the row wiring 2L to which the gate power supply line 11 is not connected via the gate middle line 11M.

[0191] Specifically, in Figure 2A In the construction shown in , for example Fig.27A In this way, power can be supplied by connecting the gate power supply line 11 to the left or right end of the row wiring 2L, connecting the source power supply line 12 to the upper end of the upper region column wiring 4L, connecting another source power supply line 12 to the lower end of the lower region column wiring 4L, and connecting the capacitor power supply line 13 to the upper and lower ends of the capacitor wiring 8L. The gate power supply line 11 is connected to the output terminal 14O of the gate driver 14, the source power supply line 12 is connected to the output terminal 15O of ​​the source driver 15, and the capacitor power supply line 13 is connected to the common electrode potential or the output terminal 16O or the GND terminal of the capacitor power supply 16. (The common electrode potential refers to the potential applied to the opposing electrode in a display device having a structure in which a display medium is sandwiched between a thin film transistor array and an opposing substrate having an opposing electrode. It is suitable for use in the case where the display medium is a liquid crystal. On the other hand, in the case where the display medium is an electrophoretic particle, it is suitable to use the capacitor power supply potential, the GND potential, or the common electrode potential.)

[0192] exist Fig.27A In the case of , even outside the effective area, the wiring overlaps less, and the power consumption outside the effective area can be suppressed. Fig.27A In FIG. 1 , the only place where the wirings overlap each other outside the effective area is the intersection (2(M-1)) of the source power supply line 12 and the capacitor power supply line 13. Fig.27A The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Fig.27A In the embodiment, there are two gate drivers 14 and two source drivers 15, but the present invention is not limited to this. For example, one gate driver and two source drivers may be used, or two or one gate-source integrated driver may be used.

[0193] Or, in Figure 2A In the structure shown, for example Fig.27BIn this way, the following power supply can be performed: the gate power supply line 11 is connected to one end of the left end or the right end of one of the upper region row wiring 2L or the lower region row wiring 2L, one end of the gate middle line 11M is connected to the other end of the left end or the right end of one of the upper region row wiring 2L or the lower region row wiring 2L, the other end of the gate middle line 11M is connected to the left end or the right end of the other row wiring 2L of the upper region row wiring 2L or the lower region row wiring 2L, the source power supply line 12 is connected to the upper end of the upper region column wiring 4L, the other source power supply line 12 is connected to the lower end of the lower region column wiring 4L, and the capacitor power supply line 13 is connected to the lower end or the upper end of the capacitor wiring 8L. The gate power supply line 11 is connected to the output terminal 14O of the gate driver 14, the source power supply line 12 is connected to the output terminal 15O of ​​the source driver 15, and the capacitor power supply line 13 is connected to the common electrode potential or the output terminal 16O of the capacitor power supply 16 or the GND terminal.

[0194] In this case, even outside the effective area, wiring overlaps less frequently, and power consumption outside the effective area can be suppressed. Fig.27B In FIG. 1 , the only place where the wirings overlap each other outside the effective region is the intersection (at (M-1)) of the source power supply line 12 and the capacitor power supply line 13 . Fig.27B The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Fig.27B In the embodiment, the gate driver 14 is one and the source driver 15 is separated into two, but the present invention is not limited to this. For example, one gate driver and one source driver may be used, or one gate-source integrated driver may be used.

[0195] Fig.28 (a)~ Fig.28 (c) shows that Fig.27A The manufacturing process of a thin film transistor array includes, on an insulating substrate 1, a first conductive layer having a gate electrode 2 and a row wiring 2L, a gate insulating film 3, a second conductive layer having a source electrode 4 and a column wiring 4L and a drain electrode 5, an interlayer insulating film 7, a third conductive layer having a capacitor electrode 8 and a capacitor wiring 8L, a capacitor insulating film 9, and a fourth conductive layer having a pixel electrode 10. The top view above shows the amount of two columns of pixels in the N / 2th row, the N / 2+1th row, and the N / 2+2th row from the top of the effective area, and the cross-sectional view below shows the cross-sectional view along the dotted line of the top view.

[0196] Fig.28(a) shows a state in which a gate electrode 2 and a row wiring 2L are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, and a source electrode 4 and a column wiring 4L and a drain electrode 5 and a drain pad 5P are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway at the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway at the pixel of the N / 2+1th row. Fig.28 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.28 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0197] Fig.28 (b) shows that Fig.28 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8 and a capacitor wiring 8L on it. Fig.28 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L.

[0198] Fig.28 (c) shows that Fig.28 The state shown in (b) has a structure in which a capacitor insulating film 9 is provided thereon and a pixel electrode 10 is provided thereon. The pixel electrode 10 is electrically connected to the drain pad 5P via an opening of the capacitor insulating film 9 and an opening of the interlayer insulating film 7 .

[0199] exist Figure 2B In the construction shown in , for example Fig.27C In this way, power can be supplied by connecting the gate power supply line 11 to the left or right end of the row wiring 2L, connecting the source power supply line 12 to the upper end of the upper region column wiring 4L, connecting another source power supply line 12 to the lower end of the lower region column wiring 4L, and connecting the capacitor power supply line 13 to the left or right end of the capacitor connection wiring 8C. The gate power supply line 11 is connected to the gate driver output terminal 14O, the source power supply line 12 is connected to the source driver output terminal 15O, and the capacitor power supply line 13 is connected to the common voltage output terminal or the capacitor voltage output terminal 16O or the GND terminal.

[0200] In this case, it is possible to completely eliminate the overlapping portion of the wirings outside the effective area, and to suppress the amount of power consumption outside the effective area. Fig.27C The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Fig.27C In the embodiment, there are two gate drivers and two source drivers are separated, but the present invention is not limited to this. For example, one gate driver and two source drivers may be used, or two or one gate-source integrated driver may be used.

[0201] Or, in Figure 2B In the structure shown, Fig.27D In this way, the following power supply can be performed: the gate power supply line 11 is connected to one end of the left end or the right end of one side of the upper area row wiring 2L or the lower area row wiring 2L, one end of the gate middle line 11M is connected to the other end of the left end or the right end of one side of the upper area row wiring 2L or the lower area row wiring 2L, the other end of the gate middle line 11M is connected to the left end or the right end of the other side of the upper area row wiring 2L or the lower area row wiring 2L, the source power supply line 12 is connected to the upper end of the upper area column wiring 4L, another source power supply line 12 is connected to the lower end of the lower area column wiring 4L, and the capacitor power supply line 13 is connected to the left end or the right end of the capacitor connection wiring 8C. The gate power supply line 11 is connected to the gate driver output terminal 14O, the source power supply line 12 is connected to the source driver output terminal 15O, and the capacitor power supply line 13 is connected to the common voltage output terminal or the capacitor voltage output terminal 16O or the GND terminal.

[0202] In this case, it is possible to completely eliminate the overlapping portion of wirings outside the effective area, thereby reducing the amount of power consumption outside the effective area. Fig.27D The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Fig.27D In the embodiment, the gate driver is one and the source driver is separated into two, but the present invention is not limited to this. For example, one gate driver and one source driver may be used, or one gate-source integrated driver may be used.

[0203] Fig.29 (a)~ Fig.29 (c) shows that Figure 4AThe manufacturing process of a thin film transistor array includes, on an insulating substrate 1, a first conductive layer having a gate electrode 2 and a row wiring 2L, a gate insulating film 3, a second conductive layer having a source electrode 4 and a column wiring 4L and a drain electrode 5, an interlayer insulating film 7, a third conductive layer having a capacitor electrode 8 and a capacitor wiring 8L, a capacitor insulating film 9, and a fourth conductive layer having a pixel electrode 10. The top view above shows the amount of two columns of pixels in the N / 2th row, the N / 2+1th row, and the N / 2+2th row from the top of the effective area, and the cross-sectional view below shows the cross-sectional view along the dotted line of the top view.

[0204] Fig.29 (a) shows a state in which a gate electrode 2, a row wiring 2L, and a capacitor connection wiring 8C1 are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, and a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C2 of the second conductive layer is electrically connected to the capacitor connection wiring 8C1 of the first conductive layer via an opening in the gate insulating film 3. In addition, the capacitor connection wiring 8C1~2 does not overlap with the row wiring 2L and the column wiring 4L. Fig.29 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.29 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0205] Fig.29 (b) shows that Fig.29 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8, a capacitor wiring 8L, and a capacitor connecting wiring 8C3 on it. Fig.29In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C3 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, and the capacitor wiring 8L at the midpoint also serves as the capacitor connection wiring 8C3, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C3 function as a whole. In addition, the capacitor wiring 8L at the midpoint is electrically connected to the capacitor connection wiring 8C2 of the second conductive layer via the opening of the interlayer insulating film 7.

[0206] Fig.29 (c) shows that Fig.29 The state shown in (b) of FIG. 1 is a structure in which a capacitor insulating film 9 is provided on the top and a pixel electrode 10 is provided on the top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9 and the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrode 10 and the capacitor connection wiring 8C3 in the N / 2th row and the N / 2+1th row, Fig.29 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0207] Alternatively, as described in detail in the first embodiment, the capacitor connection wiring 8C may be one or two layers of the capacitor connection wiring 8C1 of the first conductive layer, the capacitor connection wiring 8C2 of the second conductive layer, and the capacitor connection wiring 8C3 of the third conductive layer. Figure 4B As shown in the TFT shown in FIG. 1 , the TFT array includes a first conductive layer having a source electrode 4, a column wiring 4L, and a drain electrode 5, a gate insulating film 3, a second conductive layer having a gate electrode 2, a row wiring 2L, an interlayer insulating film 7, a third conductive layer having a capacitor electrode 8, a capacitor wiring 8L, a capacitor insulating film 9, and a fourth conductive layer having a pixel electrode 10, and has a capacitor connection wiring 8C. Alternatively, as Figure 4C As shown in the TFT shown in FIG. 1 , the TFT array includes a first conductive layer having a gate electrode 2, a row wiring 2L, and a drain sub-electrode 5S, a gate insulating film 3, a second conductive layer having a source electrode 4, a column wiring 4L, a drain electrode 5, a capacitor electrode 8, and a capacitor wiring 8L, an interlayer insulating film 7, and a third conductive layer having a pixel electrode 10, and has a capacitor connection wiring 8C. Alternatively, as shown in FIG. Figure 4DAs shown in the figure, the TFT array includes, in sequence, a first conductive layer having a source electrode 4, a column wiring 4L, a drain electrode 5, a capacitor electrode 8, and a capacitor wiring 8L, a gate insulating film 3, a second conductive layer having a gate electrode 2, a row wiring 2L, and a drain sub-electrode 5S, an interlayer insulating film 7, and a third conductive layer having a pixel electrode 10, and has a capacitor connecting wiring 8C.

[0208] In addition, although an example is shown in which the source electrode 4 and the drain electrode 5 are located in the top contact of the upper layer of the semiconductor pattern 6, the source electrode 4 and the drain electrode 5 can also be located in the bottom contact of the lower layer of the semiconductor pattern 6, or the source electrode 4 and the drain electrode 5 can be coplanar with the semiconductor pattern 6 on the same layer.

[0209] The thin film transistor array of the second embodiment can also be formed by using the same material and by the same method as that of the thin film transistor array of the first embodiment.

[0210] In addition, Figures 27A to 27D In the structure shown, Fig.37 , Fig.39 Compared with the structure shown in FIG. 1 , the number of required source driver output terminals 15O is doubled. However, since the number of pixels handled by each source driver output terminal 15O is halved, even if the number of source driver output terminals 15O is doubled, the power consumption in the source driver is smaller than the multiple and is roughly the same. In addition, the power consumption in the source driver is smaller than the reduction in the power consumption in the wiring, so even if the power consumption in the source driver increases, the overall power consumption is reduced.

[0211] (Details of the Third Embodiment)

[0212] In the thin film transistor array of the third embodiment, power can be supplied by connecting the gate power supply line 11 to one end of at least a part of the plurality of row wirings 2L, connecting the first source power supply line 12 to one end of the column wiring 4L formed in one of the two regions on the side opposite to the other of the two regions, connecting the second source power supply line 12 to one end of the column wiring 4L formed in the other of the two regions on the side opposite to the one of the two regions, and connecting the capacitor power supply line 13 to both ends or one end of the capacitor wiring 8L. Furthermore, the other end of the row wiring 2L to which the gate power supply line 11 is connected may be connected to the gate middle line 11M, and connected to the row wiring 2L to which the gate power supply line 11 is not connected via the gate middle line 11M.

[0213] Specifically, in Figure 3A In the construction shown in , for example Fig. 30AIn that way, power can be supplied in the following manner: the gate power supply line 11 is connected to the left end or the right end of the row wiring 2L, the source power supply line 12 is connected to the upper end of the upper area column wiring 4L, another source power supply line 12 is connected to the lower end of the lower area column wiring 4L, and the capacitor power supply line 13 is connected to the upper and lower ends of the capacitor wiring 8L. The gate power supply line 11 is connected to the output terminal 14O of the gate driver 14, the source power supply line 12 is connected to the output terminal 15O of ​​the source driver 15, and the capacitor power supply line 13 is connected to the common electrode potential or the output terminal 16O or the GND terminal of the capacitor power supply 16. (The common electrode potential refers to the potential applied to the opposing electrode in a display device having a structure in which a display medium is sandwiched between a thin film transistor array and an opposing substrate having an opposing electrode. It is suitable for use in the case where the display medium is a liquid crystal. On the other hand, in the case where the display medium is an electrophoretic particle, it is suitable to use the capacitor power supply potential, the GND potential, or the common electrode potential.)

[0214] exist Fig. 30A In the case of , even outside the effective area, the wiring overlaps less, and the power consumption outside the effective area can be suppressed. Fig. 30A In FIG. 4 , the only place where the wirings overlap with each other outside the effective area is the intersection (at (4M-2)) of the source power supply line 12 and the capacitor power supply line 13. Fig. 30A The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Fig. 30A In the embodiment, there are two gate drivers 14 and two source drivers 15, but the present invention is not limited to this. For example, one gate driver and two source drivers may be used, or two or one gate-source integrated driver may be used.

[0215] Or, in Figure 3A In the structure shown, for example Fig. 30B In this way, the following power supply can be performed: the gate power supply line 11 is connected to one end of the left end or the right end of one side of the upper area row wiring 2L or the lower area row wiring 2L, one end of the gate middle line 11M is connected to the other end of the left end or the right end of one side of the upper area row wiring 2L or the lower area row wiring 2L, the other end of the gate middle line 11M is connected to the left end or the right end of the other side of the upper area row wiring 2L or the lower area row wiring 2L, the source power supply line 12 is connected to the upper end of the upper area column wiring 4L, another source power supply line 12 is connected to the lower end of the lower area column wiring 4L, and the capacitor power supply line 13 is connected to the lower end or the upper end of the capacitor wiring 8L. The gate power supply line 11 is connected to the output terminal 14O of the gate driver 14, the source power supply line 12 is connected to the output terminal 15O of ​​the source driver 15, and the capacitor power supply line 13 is connected to the common electrode potential or the output terminal 16O of the capacitor power supply 16 or the GND terminal.

[0216] In this case, outside the effective area, wiring overlaps less frequently, and power consumption outside the effective area can be suppressed. Fig. 30B In FIG. 1 , the only place where the wirings overlap each other outside the effective region is the intersection ((2M-1)) of the source power supply line 12 and the capacitor power supply line 13. Fig. 30B The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Fig. 30B In the embodiment, the gate driver 14 is one and the source driver 15 is separated into two, but the present invention is not limited to this. For example, one gate driver and one source driver may be used, or one gate-source integrated driver may be used.

[0217] Fig.31 (a)~ Fig.31 (c) shows that Figure 4A The manufacturing process of a thin film transistor array includes, on an insulating substrate 1, a first conductive layer having a gate electrode 2 and a row wiring 2L, a gate insulating film 3, a second conductive layer having a source electrode 4 and a column wiring 4L and a drain electrode 5, an interlayer insulating film 7, a third conductive layer having a capacitor electrode 8 and a capacitor wiring 8L, a capacitor insulating film 9, and a fourth conductive layer having a pixel electrode 10. The top view above shows the amount of one column of pixels in the N / 2th row, the N / 2+1th row, and the N / 2+2th row from the top of the effective area, and the cross-sectional view below shows the cross-sectional view along the dotted line of the top view.

[0218] Fig.31 (a) shows a state in which a gate electrode 2 and a row wiring 2L are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, and a source electrode 4 and a column wiring 4L and a drain electrode 5 and a drain pad 5P are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway at the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway at the pixel of the N / 2+1th row. Fig.31 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.31 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0219] Fig.31 (b) shows that Fig.31 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8 and a capacitor wiring 8L on it. Fig.31 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L.

[0220] Fig.31 (c) shows that Fig.31 The state shown in (b) has a structure in which a capacitor insulating film 9 is provided thereon and a pixel electrode 10 is provided thereon. The pixel electrode 10 is electrically connected to the drain pad 5P via an opening of the capacitor insulating film 9 and an opening of the interlayer insulating film 7 .

[0221] exist Figure 3B In the structure shown, Fig. 30C In this way, the following power supply can be performed: the gate power supply line 11 is connected to the left end or the right end of the row wiring 2L, the source power supply line 12 is connected to the upper end of the upper region column wiring 4L, another source power supply line 12 is connected to the lower end of the lower region column wiring 4L, and the capacitor power supply line 13 is connected to the left end or the right end of the capacitor connection wiring 8C. The gate power supply line 11 is connected to the gate driver output terminal 14O, the source power supply line 12 is connected to the source driver output terminal 15O, and the capacitor power supply line 13 is connected to the common voltage output terminal or the capacitor voltage output terminal 16O or the GND terminal.

[0222] In this case, it is possible to completely eliminate the overlapping portion of wirings outside the effective area, thereby reducing the amount of power consumption outside the effective area. Fig. 30C The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Fig. 30C In the embodiment, there are two gate drivers and two source drivers are separated, but the present invention is not limited to this. For example, one gate driver and two source drivers may be used, or two or one gate-source integrated driver may be used.

[0223] or in Figure 3B In the structure shown, for example Fig.30DIn this way, the following power supply can be performed: the gate power supply line 11 is connected to one end of the left end or the right end of one side of the upper area row wiring 2L or the lower area row wiring 2L, one end of the gate middle line 11M is connected to the other end of the left end or the right end of one side of the upper area row wiring 2L or the lower area row wiring 2L, the other end of the gate middle line 11M is connected to the left end or the right end of the other side of the upper area row wiring 2L or the lower area row wiring 2L, the source power supply line 12 is connected to the upper end of the upper area column wiring 4L, another source power supply line 12 is connected to the lower end of the lower area column wiring 4L, and the capacitor power supply line 13 is connected to the left end or the right end of the capacitor connection wiring 8L. The gate power supply line 11 is connected to the gate driver output terminal 14O, the source power supply line 12 is connected to the source driver output terminal 15O, and the capacitor power supply line 13 is connected to the common voltage output terminal or the capacitor voltage output terminal 16O or the GND terminal.

[0224] In this case, it is possible to completely eliminate the overlapping portion of the wirings outside the effective area, and to suppress the amount of power consumption outside the effective area. Fig.30D The input terminals of the gate driver 14, source driver 15, and capacitor power supply 16 are omitted. Fig.30D In the embodiment, the gate driver is one and the source driver is separated into two, but the present invention is not limited to this. For example, one gate driver and one source driver may be used, or one gate-source integrated driver may be used.

[0225] Fig.32 (a)~ Fig.32 (c) shows that Figure 4A The manufacturing process of a thin film transistor array includes, on an insulating substrate 1, a first conductive layer having a gate electrode 2 and a row wiring 2L, a gate insulating film 3, a second conductive layer having a source electrode 4 and a column wiring 4L and a drain electrode 5, an interlayer insulating film 7, a third conductive layer having a capacitor electrode 8 and a capacitor wiring 8L, a capacitor insulating film 9, and a fourth conductive layer having a pixel electrode 10. The top view above shows a column of pixels in the N / 2th row, the N / 2+1th row, and the N / 2+2th row from the top of the effective area, and the cross-sectional view below shows a cross-sectional view along the dotted line of the top view.

[0226] Fig.32(a) shows a state in which a gate electrode 2, a row wiring 2L, and a capacitor connection wiring 8C1 are provided on an insulating substrate 1, a gate insulating film 3 is provided thereon, a semiconductor pattern 6 is provided thereon, and a source electrode 4, a column wiring 4L, a drain electrode 5, a drain connection wiring 5C, a drain pad 5P, and a capacitor connection wiring 8C2 are provided thereon. The row wiring 2L extends in the horizontal direction. The column wiring 4L extends in the vertical direction, and the column wiring 4L in the upper area ends halfway through the pixel of the N / 2th row, and the column wiring 4L in the lower area ends halfway through the pixel of the N / 2+1th row. The capacitor connection wiring 8C2 of the second conductive layer is electrically connected to the capacitor connection wiring 8C1 of the first conductive layer via an opening in the gate insulating film 3. In addition, the capacitor connection wiring 8C1~2 does not overlap with the row wiring 2L and the column wiring 4L. Fig.32 In the state shown in (a), the gate electrode 2 branches out from the continuous row wiring 2L. However, the row wiring 2L may connect a plurality of gate electrodes 2, and the gate electrode 2 may also play the role of the row wiring 2L, and the gate electrode 2 and the row wiring 2L may play the role of the row wiring 2L as a whole. Fig.32 In the state shown in (a), the source electrode 4 branches out from the continuous column wiring 4L. However, the column wiring 4L may connect a plurality of source electrodes 4, the source electrode 4 may also function as the column wiring 4L, and the source electrode 4 and the column wiring 4L may function as the column wiring 4L as a whole.

[0227] Fig.32 (b) shows that Fig.32 The state shown in (a) has an interlayer insulating film 7 on it, and a capacitor electrode 8, a capacitor wiring 8L, and a capacitor connecting wiring 8C3 on it. Fig.32 In the state shown in (b), the capacitor wiring 8L connects the plurality of capacitor electrodes 8, and the capacitor electrode 8 also serves as the capacitor wiring 8L, and the capacitor electrode 8 and the capacitor wiring 8L function as a whole. However, the capacitor electrode 8 may be branched from the continuous capacitor wiring 8L. The capacitor connection wiring 8C3 connects the capacitor wiring 8L at the midpoint when the capacitor wiring 8L connected between the capacitor electrodes 8 and the capacitor electrode 8 as a whole are regarded as capacitor wiring, and the capacitor wiring 8L at the midpoint also serves as the capacitor connection wiring 8C3, and the capacitor wiring 8L at the midpoint and the capacitor connection wiring 8C3 function as a whole. In addition, the capacitor wiring 8L at the midpoint is electrically connected to the capacitor connection wiring 8C2 of the second conductive layer via the opening of the interlayer insulating film 7.

[0228] Fig.32 (c) shows that Fig.32The state shown in (b) of FIG. 1 is a structure in which a capacitor insulating film 9 is provided on the top and a pixel electrode 10 is provided on the top. The pixel electrode 10 is electrically connected to the drain pad 5P via the opening of the capacitor insulating film 9 and the opening of the interlayer insulating film 7. In addition, since Cs increases according to the amount of overlap between the pixel electrode 10 and the capacitor connection wiring 8C3 in the N / 2th row and the N / 2+1th row, Fig.32 By making the capacitor electrodes 8 in the N / 2-th row and the N / 2+1-th row smaller than the capacitor electrodes 8 in other rows as shown in (b) of FIG. 8 , it is possible to keep Cs the same.

[0229] Alternatively, as described in detail in the first embodiment, the capacitor connection wiring 8C may be one or two layers of the capacitor connection wiring 8C1 of the first conductive layer, the capacitor connection wiring 8C2 of the second conductive layer, and the capacitor connection wiring 8C3 of the third conductive layer. Figure 4B As shown in the TFT shown in FIG. 1 , the TFT array includes a first conductive layer having a source electrode 4, a column wiring 4L, and a drain electrode 5, a gate insulating film 3, a second conductive layer having a gate electrode 2, a row wiring 2L, an interlayer insulating film 7, a third conductive layer having a capacitor electrode 8, a capacitor wiring 8L, a capacitor insulating film 9, and a fourth conductive layer having a pixel electrode 10, and has a capacitor connection wiring 8C. Alternatively, as Figure 4C As shown in the TFT shown in FIG. 1 , the TFT array includes a first conductive layer having a gate electrode 2, a row wiring 2L, and a drain sub-electrode 5S, a gate insulating film 3, a second conductive layer having a source electrode 4, a column wiring 4L, a drain electrode 5, a capacitor electrode 8, and a capacitor wiring 8L, an interlayer insulating film 7, and a third conductive layer having a pixel electrode 10, and has a capacitor connection wiring 8C. Alternatively, as shown in FIG. Figure 4D As shown in the figure, the TFT array includes, in sequence, a first conductive layer having a source electrode 4, a column wiring 4L, a drain electrode 5, a capacitor electrode 8, and a capacitor wiring 8L, a gate insulating film 3, a second conductive layer having a gate electrode 2, a row wiring 2L, and a drain sub-electrode 5S, an interlayer insulating film 7, and a third conductive layer having a pixel electrode 10, and has a capacitor connecting wiring 8C.

[0230] In addition, although an example is shown in which the source electrode 4 and the drain electrode 5 are located in the top contact of the upper layer of the semiconductor pattern 6, the source electrode 4 and the drain electrode 5 can also be located in the bottom contact of the lower layer of the semiconductor pattern 6, or the source electrode 4 and the drain electrode 5 can be coplanar with the semiconductor pattern 6 on the same layer.

[0231] The thin film transistor array of the third embodiment can also be formed by using the same material and by the same method as that of the thin film transistor array of the first embodiment.

[0232] In addition, Figures 30A to 30D In the structure shown, Fig.37 , Fig.39 Compared with the structure shown in FIG. 1 , the number of source driver output terminals 15O required is quadrupled. However, since the number of pixels handled by each source driver output terminal 15O is reduced to one fourth, even if the number of source driver output terminals 15O is quadrupled, the power consumption in the source driver is smaller than four times and is roughly the same. In addition, the power consumption in the source driver is smaller than the reduction in the power consumption in the wiring, so even if the power consumption in the source driver increases, the overall power consumption is reduced.

[0233] Example

[0234] (Example 1)

[0235] Produced Figure 1B The TFT shown. The number of column wirings 2M = 690, the number of row wirings N / 2 = 96. Figure 5D The connection was made using a 1-row stripe image, and +15V and -15V were written alternately row by row. The current waveform of the power supply of the source driver IC can be observed using the current probe of an oscilloscope (Keysight, Infinivision DSO-X 4024A). The average current of the positive power supply during writing is 0.7mA, and the average current of the negative power supply is -0.7mA. The power consumption calculated by multiplying by the voltage ±15V is a total of 21mW, and the power consumption calculated by multiplying by the frame time 20ms is 0.42mJ / frame. This is the power consumption in the column wiring. In addition, although the current probe of the oscilloscope was used to observe the current waveform of the power supply of the gate driver IC, it was too small to be observed. In other words, the power consumption in the row wiring is smaller than that in the column wiring. In addition, the theoretical power consumption of the driver IC is less than 0.06mJ / frame.

[0236] (Example 2)

[0237] Produced Figure 2B The TFT shown. The number of column wirings 2M = 690, the number of row wirings N / 2 = 96. Fig.27D, using a 1-row stripe image, +15V and -15V were written alternately row by row. The current waveform of the power supply of the source driver IC can be observed using the current probe of the oscilloscope. The average current of the positive power supply during writing is 0.7mA, and the average current of the negative power supply is -0.7mA. The power consumption calculated by multiplying by the voltage ±15V is a total of 21mW, and the power consumption calculated by multiplying by the frame time 20ms is 0.42mJ / frame. This is the power consumption in the column wiring. In addition, although the current probe of the oscilloscope was used to observe the current waveform of the power supply of the gate driver IC, it was too small to be observed. In other words, the power consumption in the row wiring is smaller than that in the column wiring. In addition, the power consumption of the logic power supply of the driver IC is less than 0.06mJ / frame.

[0238] (Example 3)

[0239] Produced Figure 3B The TFT shown in the figure has a column wiring number 4M = 1380 and a row wiring number N / 4 = 48. Fig.30D , using a 1-row stripe image, +15V and -15V were written alternately row by row. The current waveform of the power supply of the source driver IC can be observed using the current probe of the oscilloscope. The average current of the positive power supply during writing is 0.4mA, and the average current of the negative power supply is -0.4mA. The power consumption calculated by multiplying by the voltage ±15V is a total of 12mW, and the power consumption calculated by multiplying by the frame time 20ms is 0.24mJ / frame. This is the power consumption in the column wiring. In addition, although the current probe of the oscilloscope was used to observe the current waveform of the power supply of the gate driver IC, it was too small to be observed. In other words, the power consumption in the row wiring is smaller than that in the column wiring. In addition, the power consumption of the logic power supply of the driver IC is less than 0.06mJ / frame.

[0240] In the above, each measurement was performed using the embodiment with capacitor connection wiring. Figure 1A , Figure 2A , Figure 3A The same results can be obtained in the embodiment shown in which no capacitor connecting wiring is provided in the center of the active area.

[0241] (Comparative Example)

[0242] Produced Fig.38 The TFT shown in the figure has a column wiring number M = 345 and a row wiring number N = 192. Fig.39The connection was made using a 1-row stripe image, and +15V and -15V were written alternately row by row. The current waveform of the power supply of the source driver IC can be observed using the current probe of the oscilloscope. The average current of the positive power supply during writing is 1.4mA, and the average current of the negative power supply is -1.4mA. The power consumption calculated by multiplying by the voltage ±15V is a total of 42mW, and the power consumption calculated by multiplying by the frame time 20ms is 0.84mJ / frame. This is the power consumption in the column wiring. In addition, although the current probe of the oscilloscope was used to observe the current waveform of the power supply of the gate driver IC, it was too small to be observed. In other words, the power consumption in the row wiring is smaller than that in the column wiring. In addition, the power consumption of the logic power supply of the driver IC is less than 0.06mJ / frame.

[0243] Industrial Applicability

[0244] The present invention can be used in display devices such as electronic paper.

[0245] Description of Reference Numerals

[0246] 1…Insulating substrate

[0247] 2…Gate electrode

[0248] 2L…row wiring

[0249] 3…Gate insulation film

[0250] 4…Source electrode

[0251] 4L… Column wiring

[0252] 5…Drain electrode

[0253] 5C…Drain connection wiring

[0254] 5P…Drain pad

[0255] 5S…Drain secondary electrode

[0256] 6…Semiconductor pattern

[0257] 6C…Channel

[0258] 7…Interlayer insulation film

[0259] 8…Capacitor electrode

[0260] 8L…Capacitor wiring

[0261] 8C…Capacitor connection wiring

[0262] 8C1…Capacitor connection wiring (first conductive layer)

[0263] 8C2…Capacitor connection wiring (second conductive layer)

[0264] 8C3…Capacitor connection wiring (third conductive layer)

[0265] 9…Capacitor insulation film

[0266] 10…Pixel electrode

[0267] 11…Gate power supply line

[0268] 11M…gate middle line

[0269] 12…Source power supply line

[0270] 13…Capacitor power supply line

[0271] 14…Gate Driver

[0272] 14O…Gate driver output terminal

[0273] 15…Source driver

[0274] 15O…Source driver output terminal

[0275] 16…Capacitor power supply

[0276] 16O…Capacitor voltage output terminal

Claims

1. A thin film transistor array, comprising: Insulating substrate; A plurality of column wirings extending along a first direction on the insulating substrate; a plurality of row wirings extending along a second direction orthogonal to the first direction; a plurality of capacitor wirings extending along the first direction; and A plurality of pixels are arranged in a matrix along the first direction and the second direction, and have a thin film transistor, a pixel electrode and a capacitor electrode. The plurality of pixels form a rectangular effective area having a matrix structure of M columns and N rows, with N pixels arranged along the first direction and M pixels arranged along the second direction, wherein: M and N are natural numbers. The thin film transistor has a gate electrode, a source electrode, and a drain electrode. The source electrode is connected to the column wiring, The gate electrode is connected to the row wiring, The drain electrode is connected to the pixel electrode, The capacitor electrode is connected to the capacitor wiring, The row wiring has a length that spans M pixels arranged along the second direction in the active area. The column wiring has a length that spans N / 2 pixels arranged along the first direction in the active region, and does not have a length that spans N pixels arranged along the first direction in the active region. The capacitor wiring has a different length from the column wiring and has a length spanning N pixels arranged along the first direction in the effective area. The length of each capacitor wiring is greater than the length of each column wiring extending in the same direction.

2. The thin film transistor array according to claim 1, further comprising a capacitor connecting wiring extending along the second direction, The capacitor connection wiring connects the midpoints of the full lengths of the capacitor wirings for all of the multiple capacitor wirings arranged along the second direction in the effective area, thereby dividing the effective area into two areas arranged along the first direction, and the capacitor connection wiring does not overlap with either the row wiring or the column wiring.

3. The thin film transistor array according to claim 1, The M columns and N rows in the effective area satisfy M≥N / 2.

4. The thin film transistor array according to claim 1, The interval between the adjacent pixels in the first direction is constant.

5. The thin film transistor array according to claim 2, By configuring one of the column wirings for each of the columns consisting of N / 2 pixels arranged along the first direction, M column wirings are provided in each of the two regions, and a total of 2M column wirings are provided in the entire effective region. By configuring one row wiring for each row consisting of the M pixels arranged along the second direction, N / 2 row wirings are provided in each of the two regions, and a total of N row wirings are provided in the entire effective region. By arranging one capacitor wire for each column composed of N pixels arranged in the first direction, M capacitor wires are provided in the entire effective area.

6. The thin film transistor array according to claim 2, By configuring one of the column wirings for each of the columns consisting of N / 2 pixels arranged along the first direction, M column wirings are provided in each of the two regions, and a total of 2M column wirings are provided in the entire effective region. By configuring one row wiring for each row consisting of the M pixels arranged along the second direction, N / 2 row wirings are provided in each of the two regions, and a total of N row wirings are provided in the entire effective region. By arranging one capacitor wiring for every two rows of the N pixels arranged in the first direction, M / 2 capacitor wirings are provided in the entire effective region.

7. The thin film transistor array according to claim 2, By configuring two column wirings for each column consisting of N / 2 pixels arranged along the first direction, 2M column wirings are provided in each of the two regions, and a total of 4M column wirings are provided in the entire effective region. By configuring one row wiring for every two rows consisting of the M pixels arranged along the second direction, N / 4 row wirings are provided in each of the two regions, and a total of N / 2 row wirings are provided in the entire effective region. By arranging one capacitor wire for each column composed of N pixels arranged in the first direction, M capacitor wires are provided in the entire effective area.

8. The thin film transistor array according to claim 2, At least a portion of the plurality of row wirings is connected to a gate power supply line at one end, The column wiring formed in one of the two regions has a first source power supply line connected to one end on the opposite side to the other of the two regions. The column wiring formed in the other of the two regions has a second source power supply line connected to one end on the opposite side to the one of the two regions. A capacitor power supply line is connected to at least one end of the capacitor connection wiring.

9. The thin film transistor array according to claim 8, The row wiring to which the gate power supply line is connected at one end is connected to the row wiring to which the gate power supply line is not connected via a gate intermediate line connected at the other end.

10. The thin film transistor array according to claim 8, The gate power supply line is connected to the gate driver output terminal, The source power supply line is connected to the source driver output terminal, The capacitor power supply line is connected to one of a common voltage output terminal, a capacitor voltage output terminal, and a GND terminal.

11. The thin film transistor array according to any one of claims 1 to 10, comprising at least: a layer having the gate electrode and the row wiring; a gate insulating film; a layer having the source electrode, the column wiring, and the drain electrode; Interlayer insulating film; a layer having the capacitor electrode and the capacitor wiring; Capacitor insulating films; as well as a layer having the pixel electrode, The capacitor connection wiring is located in at least any one of the following layers and is connected to the capacitor wiring: a layer having the capacitor electrode and the capacitor wiring; a layer having the source electrode, the column wiring, and the drain electrode; as well as A layer having the gate electrode and the row wiring.

12. The thin film transistor array according to claim 11, The capacitor connection wiring is connected to the capacitor wiring via an opening formed in at least one of the interlayer insulating film and the gate insulating film.

13. The thin film transistor array according to any one of claims 1 to 10, comprising at least: a layer having the source electrode, the column wiring, and the drain electrode; a gate insulating film; a layer having the gate electrode and the row wiring; Interlayer insulating film; a layer having the capacitor electrode and the capacitor wiring; Capacitor insulating films; as well as a layer having the pixel electrode, The capacitor connection wiring is located in at least any one of the following layers and is connected to the capacitor wiring: a layer having the capacitor electrode and the capacitor wiring; a layer having the source electrode, the column wiring, and the drain electrode; as well as A layer having the gate electrode and the row wiring.

14. The thin film transistor array according to claim 13, The capacitor connection wiring is connected to the capacitor wiring via an opening formed in at least one of the interlayer insulating film and the gate insulating film.

15. The thin film transistor array according to any one of claims 1 to 10, comprising at least: a layer having the gate electrode, the row wiring, and a drain sub-electrode connected to the drain electrode; a gate insulating film; a layer having the source electrode, the column wiring, the drain electrode, the capacitor electrode, and the capacitor wiring; Interlayer insulating film; as well as a layer having the pixel electrode, The capacitor connection wiring is located in at least any one of the following layers and is connected to the capacitor wiring: a layer having the source electrode, the column wiring, the drain electrode, the capacitor electrode, and the capacitor wiring; as well as A layer including the gate electrode, the row wiring, and the drain sub-electrode.

16. The thin film transistor array according to claim 15, The capacitor connection wiring is connected to the capacitor wiring via an opening formed in the gate insulating film.

17. The thin film transistor array according to any one of claims 1 to 10, comprising at least: a layer having the source electrode, the column wiring, the drain electrode, the capacitor electrode, and the capacitor wiring; a gate insulating film; a layer having the gate electrode, the row wiring, and a drain sub-electrode connected to the drain electrode; Interlayer insulating film; as well as a layer having the pixel electrode, The capacitor connection wiring is located in at least any one of the following layers and is connected to the capacitor wiring: a layer having the source electrode, the column wiring, the drain electrode, the capacitor electrode, and the capacitor wiring; as well as A layer including the gate electrode, the row wiring, and the drain sub-electrode.

18. The thin film transistor array according to claim 17, The capacitor connection wiring is connected to the capacitor wiring via an opening formed in the gate insulating film.

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