Circuit partitioning preprocessing method and gate-level circuit parallel simulation method

Abstract

The present invention proposes a method for circuit partitioning preprocessing and a method for gate-level circuit parallel simulation. The method for circuit partitioning preprocessing includes: step S1: converting the gate-level circuit into a directed graph, and saving the directed graph with a structure; step S2: searching the set V of input nodes with external input from the structure; step S3: exploring the directed graph from the input node, obtaining all strongly connected components, and saving them in the form of a structure; step S4: replacing each strongly connected component with an intermediate node, deleting all strongly connected components in the directed graph and adding corresponding intermediate nodes. Compared with the prior art, the present invention realizes the preprocessing of gate-level circuit partitioning, reduces the scale and complexity of the directed graph, and reduces the difficulty of the next step of circuit partitioning.

Description

Technical Field

[0001] The invention relates to EDA circuit parallel simulation, in particular to a circuit partition preprocessing method and a gate-level circuit parallel simulation method. Background Art

[0002] With the rapid development of modern integrated circuit manufacturing technology, VLSIs have tens of millions or even hundreds of millions of gates. In EDA circuit design, in order to speed up the simulation of VLSIs, parallel simulation is an effective way to improve simulation accuracy and shorten the simulation cycle. In order to efficiently parallelize the simulation, the circuit should be reasonably divided before simulation. In the process of circuit division, if the circuit part with feedback is divided internally and then simulated, the correct simulation result cannot be obtained.

[0003] Therefore, how to ensure the rationality of the circuit partitioning results without destroying the circuit part with feedback, while reducing the size of the directed graph, and proposing a circuit partitioning preprocessing method and a gate-level circuit parallel simulation method are technical problems that the industry urgently needs to solve. Summary of the invention

[0004] Aiming at the technical problem in the prior art that in the process of circuit partitioning, the circuit part with feedback is internally divided and then the simulation fails to obtain the correct simulation result, the present invention proposes a circuit partitioning preprocessing method and a gate-level circuit parallel simulation method.

[0005] The technical solution of the present invention is to propose a circuit partition preprocessing method, comprising:

[0006] Step S1: converting the gate-level circuit into a directed graph, and saving the directed graph using a structure;

[0007] Step S2: searching the set V of input nodes with external input from the structure;

[0008] Step S3: Starting from the input node, explore the directed graph, obtain all strongly connected components, and save them in the form of a structure;

[0009] Step S4: Replace each strongly connected component with an intermediate node, delete all strongly connected components in the directed graph and add corresponding intermediate nodes.

[0010] Further, the gate-level circuit is converted into a directed graph including:

[0011] A node in the directed graph represents a gate-level circuit, and a directed edge (a, b) between nodes represents that the output of gate-level circuit a is connected to the output of gate-level circuit b.

[0012] Further, let the structure be G, which includes at least 7 parts, namely G.name, G.matrix, G.input.name, G.input.matrix, G.output.name, G.output.matrix, and G.cost;

[0013] The G.name stores the name of each node of the directed graph;

[0014] The G.matrix stores the adjacency matrix of the directed graph;

[0015] The G.input.name stores the name of the external input to the directed graph;

[0016] The G.input.matrix is ​​a matrix that stores external input information of the directed graph;

[0017] The G.output.name stores the name of the output of the directed graph to the outside;

[0018] The G.output.matrix is ​​a matrix that stores the information of the directed graph to the external output;

[0019] The G.cost stores the cost of each node in the directed graph.

[0020] Further, searching the set V of input nodes with external input from the structure includes:

[0021] According to the G.input.matrix, the input nodes with external input in the directed graph are obtained and recorded as a set V.

[0022] Furthermore, the step S3 further includes:

[0023] Step S31: Starting from any input node in the set V, the Tarjan algorithm based on depth-first search is run in sequence;

[0024] Step S32: After each execution of the Tarjan algorithm, compare whether the strongly connected components obtained in this execution are repeated with the saved strongly connected components. If so, discard the strongly connected components obtained in this execution; otherwise, save the strongly connected components obtained in this execution.

[0025] Furthermore, the step S3 further includes:

[0026] Step S33: Determine whether all nodes in the set V have been visited. If there are still nodes that have not been visited, return to step S31; otherwise, proceed to step S34;

[0027] Step S34: Output all strongly connected components and save the data in the form of a structure.

[0028] Further, the replacing each strongly connected component with an intermediate node, deleting all strongly connected components in the directed graph and correspondingly adding intermediate nodes includes:

[0029] Delete each strongly connected component in the original directed graph and correspondingly add an intermediate node to the directed graph. This intermediate node retains the connection relationship between the original strongly connected component and other nodes.

[0030] Further, the strongly connected component is:

[0031] In a directed graph with n nodes, there are m vertices (m < n), and for any two nodes A and B among the m vertices, there is both a path from A to B and a path from B to A. Then the m vertices are a strongly connected component of the directed graph.

[0032] Further, the cost of each node in the directed graph is: the number of input ports of the gate-level circuit plus 1.

[0033] The present invention also proposes a method for parallel simulation of a gate-level circuit. The method for parallel simulation of the gate-level circuit preprocesses the gate-level circuit by using the above-mentioned method for preprocessing circuit partitioning.

[0034] Compared with the prior art, the present invention has at least the following beneficial effects:

[0035] It realizes the preprocessing of gate-level circuit partitioning, reduces the scale and complexity of the directed graph, and reduces the difficulty of the next circuit partitioning. At the same time, starting from the background of the gate-level circuit and searching from the nodes with external inputs, the number of searches can be reduced. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 is the flowchart of the present invention;

[0038] Figure 2 is the topological diagram of a two-bit shift register;

[0039] Figure 3 is the directed graph of a two-bit shift register;

[0040] Figure 4It is the processed graph of the two-bit shift register directed graph. DETAILED DESCRIPTION

[0041] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0042] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.

[0043] The principle and structure of the present invention are described in detail below with reference to the accompanying drawings and embodiments.

[0044] Due to the complex structure of integrated circuits, in order to speed up the simulation of ultra-large-scale integrated circuits, parallel simulation is an effective way to improve simulation accuracy and shorten the simulation cycle. In order to perform efficient parallel simulation, it is often necessary to reasonably divide the circuit before simulation. However, in the circuit division process, if the circuit part with feedback is internally divided and then simulated, the correct simulation result will not be obtained. The core idea of ​​the present invention is to abstract the gate-level circuit into a directed graph, and use the adjacency matrix to represent the relationship between the nodes in the graph, so that the part with feedback in the circuit is called strong connectivity in the directed graph. Then, according to the directed graph with strong connectivity, it is processed, and the strongly connected component is replaced by an intermediate node, which integrates the relationship between the strongly connected component and other nodes, and generates a new directed graph, thereby realizing the improvement of simulation efficiency without affecting the simulation results.

[0045] The present invention proposes a circuit partitioning preprocessing method, comprising:

[0046] Step S1: converting the gate-level circuit into a directed graph, and saving the directed graph using a structure;

[0047] Step S2: searching the set V of input nodes with external input from the structure;

[0048] Step S3: Starting from the input node, explore the directed graph, obtain all strongly connected components, and save them in the form of a structure;

[0049] Step S4: Replace each strongly connected component with an intermediate node, delete all strongly connected components in the directed graph and add corresponding intermediate nodes.

[0050] In a directed graph G(V,E), V={ , ,…, } is a set of nodes, E={ , ,…, } is the set of edges. To indicate the existence of a directed edge, from vertex Point to the vertex , the resulting matrix D = D (G) = is the adjacency matrix of the directed graph G. In digital circuits, there are often multiple gate-level circuits, adjacent gate-level circuits are connected, and the output of gate-level circuit a is connected to the input of gate-level circuit b. Therefore, the digital circuit can be abstracted as a directed graph. Each node in the directed graph can represent a gate-level circuit. The directed edge (a, b) between the nodes represents that the output of gate circuit a is connected to the input of gate circuit b. The adjacency matrix of the directed graph is Able to represent the connection relationship between various parts in a digital circuit.

[0051] In a digital circuit, there is a feedback relationship between two gate-level circuits. After the output of gate-level circuit a is connected to the input of gate-level circuit b, the output of gate-level circuit b is fed back to gate-level circuit a. This is represented in the digital circuit as the output of gate-level circuit a is connected to the input of gate-level circuit b, and the output of gate-level circuit b is connected to the input of gate-level circuit a. That is, there is a path from gate-level circuit a to gate-level circuit b, and there is a path from gate-level circuit b to gate-level circuit a. After the digital circuit is represented by a directed graph, node A is used to replace gate-level circuit a, and node B is used to replace gate-level circuit b. In the resulting directed graph, there is a path from node A to node B, and there is a path from node B to node A. That is, the directed graph is strongly connected, so the digital circuit with feedback can be converted into a strongly connected directed graph.

[0052] In a strongly connected directed graph, if there are m (m<=n) vertices in a directed graph with n nodes, and for any two nodes A and B among these m vertices, there is a path from A to B and there is also a path from B to A, then these m nodes are a strongly connected component of the directed graph.

[0053] In digital circuits, the circuit parts with feedback are closely connected and not suitable for division. After the digital circuit is converted into a directed graph, the circuit parts with feedback become strongly connected components in the directed graph. In this way, the present invention can find all the strongly connected components in the directed graph and replace the strongly connected components with an intermediate node. The intermediate node inherits the relationship between all nodes in the strongly connected component and other nodes. Therefore, the new directed graph obtained retains the original circuit part structure with feedback, while achieving circuit simplification and improving simulation efficiency.

[0054] The step S1 of using a structure to save data includes: assuming that the structure is G, dividing it into at least 7 parts, namely G.name, G.matrix, G.input.name, G.input.matrix, G.output.name, G.output.matrix, and G.cost;

[0055] Among them, G.name stores the names of each node in the directed graph;

[0056] G.matrix stores the adjacency matrix of the directed graph;

[0057] G.input.name stores the name of the external input to the directed graph;

[0058] G.input.matrix is ​​a matrix that stores external input information for the directed graph;

[0059] G.output.name stores the name of the directed graph's external output;

[0060] G.output.matrix is ​​a matrix that stores the information of the directed graph's external output;

[0061] G.cost stores the cost of each node in the directed graph.

[0062] After the data is saved in the structure, the information such as each node, input and output, and cost of the digital circuit can be quickly obtained through the structure. Among them, the cost of each node in the directed graph is the number of input ports of the gate-level circuit plus 1.

[0063] For example, in step S2, the set V of input nodes with external input is searched from the structure, which can directly obtain the input nodes with external input in the directed graph through G.input.matrix and count them as a set V. There are fewer input nodes with external input in the gate-level circuit, so starting the search from the input nodes with external input can reduce the number of searches.

[0064] Among the algorithms for finding strongly connected components of directed graphs, the most widely used one is the Tarjan algorithm. The Tarjan algorithm is based on depth-first search. The directed graph converted from digital circuits is relatively complex, and a depth-first search cannot guarantee traversal of all nodes. Therefore, this patent starts from the circuit perspective, obtains the nodes with external inputs in the directed graph, and runs the Tarjan algorithm from the nodes with external inputs in the directed graph in sequence, and records the strongly connected components obtained each time it is run.

[0065] When performing depth-first exploration, repeated nodes or strongly connected components may be explored, so it is necessary to discard the repeated operation results. The obtained strongly connected components are not repeated, which just represents all the feedback relationships in the digital circuit.

[0066] Specifically, step S3 also includes:

[0067] Step S31: Starting from any node in the set V, the Tarjan algorithm based on depth-first search is run in sequence;

[0068] Step S32: After each execution of the Tarjan algorithm, compare whether the strongly connected components obtained in this execution are

[0069] If it is repeated with the saved strongly connected component, the strongly connected component obtained this time is discarded, otherwise the strongly connected component obtained this time is saved.

[0070] When all nodes have been visited, the calculation is completed, stops, and outputs the strongly connected components. Specifically, step S33: determine whether all nodes in the set V have been visited. If there are still nodes that have not been visited, return to step S31, otherwise go to step S34;

[0071] Step S34: Output all strongly connected components and save the data in the form of a structure.

[0072] After the above steps, all strongly connected components can be obtained and saved in the structure. After the strongly connected components are obtained, an intermediate node can be used to replace the original strongly connected component. This node inherits the relationship between all nodes in the original strongly connected component and other nodes. The weight of the intermediate node is the sum of the weights of all nodes in the strongly connected component.

[0073] After replacing the original strongly connected components with intermediate nodes, adding a directed graph and deleting the nodes in the original strongly connected components in the directed graph, a new directed graph can be obtained, and the intermediate nodes inherit the original strongly connected components, that is, the feedback relationship of the digital circuit is retained, and the scale and complexity of the directed graph are reduced, thereby reducing the time for the next circuit division.

[0074] See also Figures 2 to 4, which is a schematic diagram of preprocessing in one embodiment of the present invention, specifically, Figure 2 is a topological diagram of a two-bit shift register. It can be seen from the figure that it includes 20 gate-level circuits, namely gate-level circuit a1 to gate-level circuit a20, among which the output of gate-level circuit a4 is connected to the input of gate-level circuit a5, and the output of gate-level circuit a5 is connected to the input of gate-level circuit a4, that is, there is a feedback relationship between gate-level circuit a4 and gate-level circuit a5. Similarly, it can be seen that there is a feedback relationship between gate-level circuit a9 and gate-level circuit a10, gate-level circuit a14 and gate-level circuit a15, and gate-level circuit a19 and gate-level circuit a20.

[0075] Figure 3 It is a directed graph of a two-bit shift register. According to the division method, each node of the directed graph represents a gate-level circuit. As can be seen from the figure, node a1 represents Figure 2 In the gate level circuit a1, node a2 represents Figure 2 The gate-level circuit a2 in the middle, and the gate-level circuits a1 to a20 are represented as nodes a1 to a20 respectively. Its directed edge (a2, a4) represents Figure 2 The output of the gate-level circuit a2 is connected to the input of the gate-level circuit a4, so that all the connection relationships in the two-bit shift register are represented as directed edges, thereby obtaining a corresponding directed graph.

[0076] After obtaining the directed graph, start searching from the input of the external node to obtain all the strongly connected components, save them in the structure, and then use an intermediate node to replace the original strongly connected component.

[0077] from Figure 3 It can be seen that between node a4 and node a5, there exists a path from node a4 to node a5, and there exists a path from node a5 to node a4; between node a9 and node a10, there exists a path from node a9 to node a10, and there exists a path from node a10 to node a9; between node a14 and node a15, there exists a path from node a14 to node a15, and there exists a path from node a15 to node a14; between node a19 and node a20, there exists a path from node a19 to node a20, and there exists a path from node a20 to node a19, that is, the directed graph is strongly connected, and its strongly connected component represents the circuit part with feedback in the two-bit shift register.

[0078] See also Figure 4, after all the strongly connected components in the directed graph are obtained, the intermediate nodes are generated to replace the original strongly connected components. As can be seen from the figure, the newly generated intermediate nodes are nodes F1, F2, F3 and F4, where node F1 replaces the strong connection between nodes a4 and a5 in the directed graph. At the same time, node F1 is also connected to nodes a2, a3, a6 and a8, and their connection relationship is that nodes a2 and a3 point to node F1, and node F1 points to nodes a6 and a8; in the original directed graph, node a2 points to node a4, node a3 points to node a5, node a4 points to node a6, and node a5 points to node a8. By comparison, it can be found that the connection relationship between node F1 and nodes a2, a3, a6 and a8 is consistent with the connection relationship between nodes a4 and a5 and nodes a2, a3, a4 and a8 in the original directed graph, that is, the generated intermediate nodes inherit the connection relationship of the original nodes. Similarly, the connection relationship between node F2 and node a6, node a8, node a11 and node a12 is consistent with the connection relationship between node a9 and node a10 and node a6, node a8, node a11 and node a12 in the original directed graph; the connection relationship between node F3 and node a12, node a13, node a16, node a17 and node a18 is consistent with the connection relationship between node a14 and node a15 and node a12, node a13, node a16, node a17 and node a18 in the original directed graph; the connection relationship between node F4 and node a16 and node a18 is consistent with the connection relationship between node a19 and node a20 and node a16 and node a18 in the original directed graph. It can be seen that after replacing the strongly connected components with the newly generated nodes, the generated directed graph inherits all the strongly connected components and connection relationships in the original directed graph.

[0079] Thus, this patent has realized the preprocessing of circuit division, reduced the scale and complexity of the directed graph, and reduced the difficulty of the next step of circuit division. At the same time, the feedback relationship existing in the original digital circuit is retained through the intermediate nodes, avoiding the problem of distortion of simulation results.

[0080] The present invention also proposes a gate-level circuit parallel simulation method, which adopts the circuit partition preprocessing method in the gate-level circuit parallel simulation.

[0081] The above are only partial or preferred embodiments of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A method for circuit partitioning preprocessing, characterized in that: include: Step S1: converting the gate-level circuit into a directed graph, and saving the directed graph using a structure; Step S2: searching the set V of input nodes with external input from the structure; Step S3: Starting from the input node, explore the directed graph, obtain all strongly connected components, and save them in the form of a structure; Step S4: replacing each strongly connected component with an intermediate node, deleting all strongly connected components in the directed graph and adding corresponding intermediate nodes; Suppose the structure is G, which includes at least 7 parts, namely G.name, G.matrix, G.input.name, G.input.matrix, G.output.name, G.output.matrix, and G.cost; The G.name stores the name of each node of the directed graph; The G.matrix stores the adjacency matrix of the directed graph; The G.input.name stores the name of the external input to the directed graph; The G.input.matrix is ​​a matrix that stores external input information of the directed graph; The G.output.name stores the name of the output of the directed graph to the outside; The G.output.matrix is ​​a matrix that stores the information of the directed graph to the external output; The G.cost stores the cost of each node in the directed graph.

2. The circuit partitioning preprocessing method according to claim 1, characterized in that: The gate-level circuit is converted into a directed graph comprising: A node in the directed graph represents a gate-level circuit, and a directed edge (a, b) between nodes represents that the output of gate-level circuit a is connected to the output of gate-level circuit b.

3. The circuit partitioning preprocessing method according to claim 2, characterized in that: The step of searching the set V of input nodes with external input from the structure includes: According to the G.input.matrix, the input nodes with external input in the directed graph are obtained and recorded as a set V.

4. The circuit partitioning preprocessing method according to claim 1, characterized in that: The step S3 further comprises: Step S31: Starting from any input node in the set V, the Tarjan algorithm based on depth-first search is run in sequence; Step S32: After each execution of the Tarjan algorithm, compare whether the strongly connected components obtained in this execution are repeated with the saved strongly connected components. If so, discard the strongly connected components obtained in this execution; otherwise, save the strongly connected components obtained in this execution.

5. The circuit partitioning preprocessing method according to claim 4, characterized in that: The step S3 further comprises: Step S33: Determine whether all nodes in the set V have been visited. If there are still nodes that have not been visited, return to step S31; otherwise, proceed to step S34; Step S34: Output all strongly connected components and save the data in the form of a structure.

6. The circuit partitioning preprocessing method according to claim 1, characterized in that: The replacing each strongly connected component with an intermediate node, deleting all strongly connected components in the directed graph and adding corresponding intermediate nodes comprises: Delete each strongly connected component in the original directed graph, and add an intermediate node to the directed graph accordingly. The intermediate node retains the connection relationship between the original strongly connected component and other nodes.

7. The circuit partitioning preprocessing method according to claim 1, characterized in that: The strongly connected components are: In a directed graph with n nodes, there are m vertices (m < n), and for any two nodes A and B among the m vertices, there is a path from A to B and a path from B to A. Then the m vertices form a strongly connected component of the directed graph.

8. The circuit partitioning preprocessing method according to claim 1, characterized in that: The cost of each node in the directed graph is: the number of input ports of the gate-level circuit plus 1.

9. A method for parallel simulation of gate-level circuits, characterized in that: The method for parallel simulation of the gate-level circuit preprocesses the gate-level circuit by using the circuit partitioning preprocessing method described in any one of claims 1 to 7.

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