Semiconductor structure and method for forming the same

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. The semiconductor structure comprises: a substrate; a first conductive structure, located on the surface of the substrate; a wiring layer, embedded between the substrate and the first conductive structure in a direction perpendicular to the substrate, and the wiring layer extends out of the first conductive structure in a direction parallel to the substrate; a first plug, extending in a direction perpendicular to the substrate, one end of the first plug is electrically connected to the end of the wiring layer extending out of the first conductive structure, and the other end is used to connect to an external circuit. The present invention solves the problem of difficult wiring layout due to the reduction in cutting path size, avoids the problem of structural layout easily violating design principles, and ensures the reliability and stability of subsequent test results of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the advancement of advanced manufacturing processes and in order to improve the effective utilization rate of wafers, the structure used for electrical testing of chips in semiconductor structures strives to make the size of the cutting path smaller and smaller in design. The electrical test structure usually includes pads arranged in an array and wiring around the pads. The pads are used for probe testing and electrical connection with external circuits. However, as the size of the cutting path is reduced, the area available for wiring around the pads is reduced, which increases the difficulty of winding layout.

[0003] In order to solve this technical problem, the method used in the prior art is to reduce the pad size to increase the area around the pad available for wiring. Although this method can provide sufficient area for wiring, during the wafer test, the probe is very likely to slip out of the surface of the smaller pad or even pierce outside the pad area, resulting in unstable WAT (Wafer Acceptance Test) results, low reliability, and easy damage to the probe.

[0004] Therefore, how to improve the winding structure in the semiconductor structure, avoid the problem of difficult winding layout due to the reduction of the cutting path size, and improve the reliability and stability of the semiconductor structure test results. Summary of the invention

[0005] The invention provides a semiconductor structure and a forming method thereof, which are used to solve the problem that the winding layout is difficult due to the reduction of the cutting path size.

[0006] In order to solve the above problems, the present invention provides a semiconductor structure, comprising:

[0007] substrate;

[0008] A first conductive structure, located on the surface of the substrate;

[0009] a wiring layer, embedded between the substrate and the first conductive structure in a direction perpendicular to the substrate, and extending out of the first conductive structure in a direction parallel to the substrate;

[0010] The first plug extends in a direction perpendicular to the substrate, one end of the first plug is electrically connected to the end of the wiring layer extending out of the first conductive structure, and the other end of the first plug is used to connect to an external circuit.

[0011] Optionally, the base is a substrate, and the first conductive structure includes a plurality of pads arranged at intervals along a first direction;

[0012] The wiring layer includes a plurality of wirings located between the substrate and the pad, the end of each wiring extending out of the pad along the first direction, and at least one first plug is provided at the end of each wiring extending out of the pad, and the first direction is parallel to the substrate.

[0013] Optionally, also include:

[0014] The connection layer is located above the wiring layer in a direction perpendicular to the substrate and is arranged in the same layer as the plurality of pads. One end of the connection layer is electrically connected to the first plug at the end of a wiring below one of the pads, and the other end is electrically connected to another of the pads.

[0015] Optionally, along a second direction, a projection of the pad in a direction perpendicular to the substrate covers a plurality of the wirings located therebelow, and the second direction is parallel to the substrate and perpendicular to the first direction.

[0016] Optionally, the base includes a substrate and a second conductive structure located on a surface of the substrate, and the first conductive structure is located above the second conductive structure;

[0017] The wiring layer includes a plurality of wirings located between the first conductive structure and the second conductive structure. An end of each of the wirings extends out of the first conductive structure, and at least one first plug is disposed at an end of each of the wirings extending out of the first conductive structure.

[0018] Optionally, also include:

[0019] a plurality of second plugs, wherein one end of the second plug is electrically connected to the second conductive structure and the other end of the second plug is electrically connected to the first conductive structure;

[0020] Each of the wirings passes through a gap between two adjacent second plugs.

[0021] Optionally, the material of the first conductive structure is a metal material, and the material of the wiring layer is a polysilicon material or a metal material.

[0022] In order to solve the above problem, the present invention further provides a method for forming a semiconductor structure, comprising the following steps:

[0023] providing a substrate;

[0024] forming a wiring layer on the surface of the substrate;

[0025] forming a first plug at an end of the wiring layer, wherein the first plug extends in a direction perpendicular to the substrate and is used for connecting to an external circuit;

[0026] A first conductive structure is formed on the wiring layer, and an end portion of the wiring layer formed with the first plug extends out of the first conductive structure along a direction parallel to the substrate.

[0027] Optionally, the specific steps of forming a wiring layer on the surface of the substrate include:

[0028] forming a first dielectric layer covering the substrate;

[0029] Etching the first dielectric layer to form a first opening exposing the substrate;

[0030] A first conductive material is deposited in the first opening to form the wiring layer.

[0031] Optionally, the specific steps of forming the wiring layer include:

[0032] Etching the first dielectric layer to form a plurality of first openings arranged along a second direction, wherein the first openings extend along the first direction and expose the substrate, the first direction is parallel to the substrate, and the second direction is parallel to the substrate and perpendicular to the first direction;

[0033] A first conductive material is filled into the first openings to form a wiring layer including a plurality of wirings.

[0034] Optionally, the specific step of forming the first plug at the end of the wiring layer includes:

[0035] forming a second dielectric layer covering the first dielectric layer and the wiring layer;

[0036] Etching the second dielectric layer to form a second opening exposing an end portion of the wiring layer;

[0037] A second conductive material is deposited in the second opening to form the first plug.

[0038] Optionally, the specific steps of forming the first conductive structure on the wiring layer include:

[0039] A third conductive material is deposited on the surface of the second dielectric layer to form the first conductive structure exposing the first plug.

[0040] Optionally, the first conductive structure includes a plurality of pads arranged at intervals along the first direction, and the plurality of wiring layers are distributed one by one under the plurality of pads;

[0041] The substrate surface also includes a second plug located between two adjacent wirings below one of the pads, wherein one end of the second plug is electrically connected to the substrate, and the other end of the second plug is electrically connected to one of the pads.

[0042] Optionally, the specific step of forming the first conductive structure on the wiring layer further includes:

[0043] A third conductive material is deposited on the surface of the second dielectric layer to form the first conductive structure exposing the first plug, and a connecting layer is formed at the same time, wherein one end of the connecting layer is electrically connected to the first plug at the end of a wiring under one of the pads, and the other end is electrically connected to another of the pads.

[0044] Optionally, the base includes a substrate and a second conductive structure located on a surface of the substrate; the first conductive structure is located above the second conductive structure;

[0045] The wiring layer includes a plurality of wirings located between the first conductive structure and the second conductive structure. An end of each of the wirings extends out of the first conductive structure, and at least one first plug is disposed at an end of each of the wirings extending out of the first conductive structure.

[0046] Optionally, the semiconductor structure includes a plurality of second plugs, one end of the second plug is electrically connected to the second conductive structure, and the other end of the second plug is electrically connected to the first conductive structure;

[0047] Each of the wirings passes through a gap between two adjacent second plugs.

[0048] Optionally, the material of the first conductive structure is a metal material, and the material of the wiring layer is a polysilicon material or a metal material.

[0049] The semiconductor structure and the method for forming the same provided by the present invention avoid occupying the peripheral space coplanar with the first conductive structure by arranging the wiring layer between the substrate and the first conductive structure and connecting the wiring layer with the external circuit through the first plug located at the end of the wiring layer, and do not need to reduce the area of ​​the first conductive structure. This solves the problem of difficult wiring layout due to the reduction of the cutting path size, avoids the problem of structural layout easily violating the design principles, and ensures the reliability and stability of subsequent test results of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Attached Figure 1 is a schematic top view of a semiconductor structure in a specific embodiment of the present invention;

[0051] Attached Figure 2 is a schematic diagram of the cross-sectional structure of the first conductive structure and the wiring layer in a specific implementation manner of the present invention;

[0052] Attached Figures 3A-3C is a three-dimensional schematic diagram of a semiconductor structure in a specific embodiment of the present invention;

[0053] Attached Figure 4is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention;

[0054] Attached Figures 5A-5M It is a schematic diagram of the main process structure in the process of forming a semiconductor structure according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0055] The specific implementation manner of the semiconductor structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0056] This specific embodiment provides a semiconductor structure, Figure 1 is a schematic top view of a semiconductor structure in a specific embodiment of the present invention, Figure 2 is a schematic diagram of the cross-sectional structure of the first conductive structure and the wiring layer in a specific embodiment of the present invention, Figures 3A-3C Schematic diagram of a semiconductor structure in a specific embodiment of the present invention. Figure 1-Figure 2 , Figure 3A-3C As shown, the semiconductor structure provided in this specific embodiment includes:

[0057] Base 10;

[0058] A first conductive structure 11, located on the surface of the substrate 10;

[0059] a wiring layer, embedded between the substrate 10 and the first conductive structure 11 in a direction perpendicular to the substrate 10, and extending out of the first conductive structure 11 in a direction parallel to the substrate 10;

[0060] The first plug 13 extends in a direction perpendicular to the substrate 10 , one end of the first plug 13 is electrically connected to the end of the wiring layer extending out of the first conductive structure 11 , and the other end is used to connect to an external circuit.

[0061] Specifically, the material of the first conductive structure 11 can also be a metal material such as tungsten, copper, aluminum, etc. The first conductive structure 11 is located on the substrate 10 and is used to transmit external electrical signals to the substrate 10. The external circuit can be a circuit for transmitting external electrical signals to the first conductive structure 11, such as a circuit for transmitting a test electrical signal to the first conductive structure 11. Figure 1 and Figure 2 At the angle shown, a portion of the wiring layer located below the first conductive structure 11 is not visible and is therefore represented by a dotted line.

[0062] In this specific embodiment, the wiring layer is embedded between the substrate 10 and the first conductive structure 11 along the Z-axis direction, avoiding the occupation of the peripheral area coplanar with the first conductive structure 11 (for example, the area outside the first conductive structure 11 along the Y-axis direction), so that even when the cutting path size is small, sufficient wiring space can be obtained, simplifying the winding layout process in the semiconductor structure, avoiding the problem that the structural layout is easy to violate the design principles, ensuring the reliability of the subsequent test results of the semiconductor structure, and the stability of the performance of the semiconductor structure. At the same time, the first plug for leading out the wiring layer is located at the end of the wiring layer extending out of the first conductive structure 11, so as not to affect the setting of the first conductive structure 11.

[0063] Optionally, the base is a substrate, and the first conductive structure 11 includes a plurality of pads arranged at intervals along a first direction;

[0064] The wiring layer includes a plurality of wirings 12 located between the substrate 10 and the pad, an end of each wiring 12 extending out of the pad along the first direction, and at least one first plug 13 is provided at the end of each wiring 12 extending out of the pad, and the first direction is parallel to the substrate 10.

[0065] Optionally, the semiconductor structure further includes:

[0066] The connection layer is located above the wiring layer in a direction perpendicular to the substrate 10 and is arranged in the same layer as the multiple pads. One end of the connection layer is electrically connected to the first plug 13 at the end of a wiring 12 located below the pad, and the other end is electrically connected to another pad.

[0067] Specifically, the base 10 may be a semiconductor substrate having an active area (AA), and in this case, the wiring layer is located between the semiconductor substrate and the first conductive structure. Figure 1 , Figure 2 and Figure 3AAs shown, the first conductive structure 11 includes a plurality of pads located on the surface of the substrate 10 and arranged in parallel along the X-axis direction, such as a first pad Pad1, a second pad Pad2, a third pad Pad3, ..., a nineteenth pad Pad19, and a twentieth pad Pad20. The number of pads included in the first conductive structure 11 can be selected by those skilled in the art according to the design requirements of the integrated circuit, such as the requirements of the electrical performance test. The surface of the substrate 10 also has a test structure 15 for transmitting a test electrical signal to the wiring layer. The plurality of wiring layers are distributed one by one between the plurality of pads and the substrate 10, that is, each pad has a corresponding wiring layer directly below it, and each wiring layer has a plurality of wirings 12 arranged in parallel along the Y-axis direction, and each wiring 12 is in the shape of a long strip extending along the X-axis direction. Each end of the wiring 12 extending out of the pad has at least one first plug 13. For example, the wiring layer between the first pad Pad1 and the substrate 10 includes three wirings 12 arranged in parallel along the Y-axis direction, and each wiring 12 extends along the X-axis direction. In order to ensure the stability of the electrical connection, each end of the wiring 12 extending out of the pad has more than two first plugs 13. The material of the first plug 13 can also be a metal material such as tungsten, copper, aluminum, etc. The "plurality" described in this specific embodiment refers to more than two.

[0068] The connection layer is located above the wiring layer and is arranged in the same layer as the pad, and includes a first connection line 141 and a second connection line 142. One end of the first connection line 141 is used to electrically connect the first plug 13 at one end of the wiring line located below one pad, and the other end is used to electrically connect another pad. One end of the second connection line 142 is used to electrically connect the test structure 15, and the other end is used to electrically connect the first plug 13 at the other end of the wiring line located below one pad. For example, Figure 2As shown, the test structure 15 is electrically connected to one end of the first plug 13 through the second connection line 142, and the other end of the first plug 13 is electrically connected to the left end of a wiring 12 located at the bottom of the second pad Pad2; the right end of the wiring 12 is connected to the end of another first plug 13, and the other end of another first plug 13 is electrically connected to the third pad Pad3 through the first connection line. With this connection mode, the electrical test signal is sequentially transmitted to the third pad Pad3 through the test structure 15, the second connection line 142, the first plug 13 connected to the left end of the wiring 12 under the second pad Pad2, the wiring 12 under the second pad Pad2, the first plug 13 connected to the right end of the wiring 12 under the second pad Pad2, and the first connection line 141. Therefore, part of the transmission path of the test electrical signal is set at the bottom of the pad, which reduces the occupation of the space around the pad and improves the space utilization rate in the semiconductor structure.

[0069] In this specific implementation, the connection layer and the pad are arranged in the same layer, so that the connection layer and the pad can be formed synchronously, thereby achieving further simplification of the semiconductor process.

[0070] exist Figure 2 It only shows that the connection layer is connected to one wiring 12 and one pad. A person skilled in the art may connect the connection layer to multiple wirings 12 and / or multiple pads at the same time according to the test requirements, and this specific embodiment does not limit this.

[0071] In order to further improve the space utilization of the semiconductor structure, optionally, along a second direction, the projection of the pad in a direction perpendicular to the substrate 10 covers the plurality of wirings 12 located thereunder, and the second direction is parallel to the substrate 10 and perpendicular to the first direction.

[0072] Specifically, along Figure 1 , Figure 2 In the Y-axis direction of the bonding pad, the projection of the bonding pad in the Z-axis direction completely covers the wiring 12 located therebelow. The wiring 12 extends out of the bonding pad along the X-axis direction.

[0073] In other specific embodiments, Figure 3B , Figure 3C As shown, the base includes a substrate and a second conductive structure 30 located on the surface of the substrate, and the first conductive structure 11 is located above the second conductive structure 30;

[0074] The wiring layer includes a plurality of wirings 12 located between the first conductive structure 11 and the second conductive structure 30 . An end of each wiring 12 extends out of the first conductive structure 11 , and at least one first plug 13 is disposed at the end of each wiring 12 extending out of the first conductive structure 11 .

[0075] Optionally, the semiconductor structure further includes:

[0076] A plurality of second plugs 31, wherein one end of the second plug 31 is electrically connected to the second conductive structure 30, and the other end of the second plug 31 is electrically connected to the first conductive structure 11;

[0077] Each of the wirings 12 passes through a gap between two adjacent second plugs 31 .

[0078] Figure 3C yes Figure 3B A top view of the structure, and in Figure 3C The first conductive structure 11 is not shown in the figure, so as to clearly show the relative position relationship between the second plug 31 and the wiring 12. Figure 3B , Figure 3C As shown, the substrate can also be a semiconductor substrate with the second conductive structure 30 on the surface, in which case the wiring layer is embedded between the second conductive structure 30 and the first conductive structure 11. The wiring layer is not in direct contact with the first conductive structure 11 and the second conductive structure 30, that is, the wiring layer is isolated from the first conductive structure 11 located above it and the second conductive structure 30 located below it by insulating materials. The first conductive structure 11 and the second conductive structure 30 transmit electrical signals through the second plug 31. For example, when the first conductive structure 11 includes a plurality of pads arranged along the X-axis direction, the test signal can be transmitted to another pad through the wiring 12 under one pad. The wiring 12 passes through the gap between two adjacent second plugs 31, that is, the wiring 12 and the second plug 31 are independent and electrically isolated from each other to avoid signal crosstalk between the wiring 12 and the second plug 31.

[0079] Those skilled in the art can select the materials of the first conductive structure 11 and the wiring layer according to actual needs, and this specific embodiment does not limit this. Optionally, the materials of the first conductive structure 11 and the second conductive structure 30 are metal materials, and the material of the wiring layer is polysilicon material or metal material. For example, when the base is a substrate, the material of the wiring layer can be polysilicon material; when the base includes a substrate and a second conductive structure located on the surface of the substrate, the material of the wiring layer can be a metal material. The material of the second plug 31 can be the same as that of the first plug 13, for example, both are tungsten.

[0080] In addition, this specific embodiment also provides a method for forming a semiconductor structure. Figure 4 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention, Figures 5A-5M This is a schematic diagram of the main process structure in the process of forming a semiconductor structure in a specific embodiment of the present invention. The schematic diagram of the semiconductor structure formed in this specific embodiment can be seen in Figure 1 , Figure 2 , Figure 3A and Figure 3B .like Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 4 and Figure 5A-5M As shown, the method for forming a semiconductor structure provided in this specific embodiment includes the following steps:

[0081] Step S41, providing a substrate 10, such as Figure 5A shown.

[0082] Specifically, the substrate 10 may be a semiconductor substrate with an active area (AA) formed thereon, or may be a semiconductor substrate with a metal layer covering its surface. The following description will be made by taking the substrate 10 as a semiconductor substrate with an active area formed thereon as an example.

[0083] Step S42, forming a wiring layer on the surface of the substrate 10, such as Figure 5E shown.

[0084] Optionally, the specific steps of forming a wiring layer on the surface of the substrate 10 include:

[0085] A first dielectric layer 40 is formed covering the substrate 10, such as Figure 5A As shown;

[0086] The first dielectric layer 40 is etched to form a first opening 401 exposing the substrate 10. Figure 5C As shown;

[0087] Depositing a first conductive material in the first opening 401 to form the wiring layer, such as Figure 5E shown.

[0088] Optionally, the specific steps of forming the wiring layer include:

[0089] Etching the first dielectric layer 40 to form a plurality of first openings 401 arranged along a second direction, wherein the first openings 401 extend along the first direction and expose the substrate, wherein the first direction is parallel to the substrate 10 , and the second direction is parallel to the substrate 10 and perpendicular to the first direction;

[0090] The first openings 401 are filled with a first conductive material to form a wiring layer including a plurality of wirings 12 .

[0091] Specifically, after forming the first dielectric layer 40 covering the substrate 10, a first photoresist layer 41 is formed on the surface of the first dielectric layer 40, wherein the first photoresist layer 41 has a plurality of first etching windows 411, such as Figure 5B Then, the first dielectric layer 40 is etched along the first etching window 411 to form a plurality of first openings 401 exposing the substrate 10 in the first dielectric layer 40, as shown in FIG. Figure 5C As shown; then, an initial wiring 42 is formed to fill the first opening 401 and cover the top surface of the first dielectric layer 40; finally, a portion of the initial wiring 42 is removed by a chemical mechanical polishing process to expose the first dielectric layer 40, and the initial wiring 42 remaining in the first opening 401 is used as a wiring 12, as shown in FIG. Figure 5E shown.

[0092] Step S43, forming a first plug 13 at the end of the wiring layer, wherein the first plug 13 extends in a direction perpendicular to the substrate 10 and is used to connect to an external circuit. Figure 5J shown.

[0093] Optionally, the specific steps of forming the first plug 13 at the end of the wiring layer include:

[0094] A second dielectric layer 43 is formed covering the first dielectric layer 40 and the wiring layer. Fig. 5F As shown;

[0095] The second dielectric layer 43 is etched to form a second opening 431 exposing the end of the wiring layer. Figure 5H As shown;

[0096] A second conductive material is deposited in the second opening 431 to form the first plug 13. Figure 5J shown.

[0097] Specifically, after forming the second dielectric layer 43, a second photoresist layer 44 is deposited on the second dielectric layer 43, and the second photoresist layer 44 has a second etching window 441 exposing the second dielectric layer 43. Figure 5G Afterwards, the second dielectric layer 43 is etched from the second etching window 441 to form a plurality of second openings 431 exposing the wiring 12, as shown in FIG. Figure 5H Next, an initial first plug 45 is formed to fill the second opening 431 and cover the top surface of the second dielectric layer 43, as shown in FIG. Fig.5I As shown; finally, a portion of the initial first plug 45 is removed by a chemical mechanical polishing process, and the initial first plug 45 remaining in the second opening 431 serves as a first plug 13.

[0098] Step S44, forming a first conductive structure 11 on the wiring layer, wherein the end of the wiring layer formed with the first plug 13 extends out of the first conductive structure 11 in a direction parallel to the substrate 10, such as Figure 1 , Figure 2 and Figure 5K As shown, Figure 5K is a side view of the semiconductor structure, and the first plug 13 is not substantially in contact with the first conductive structure 11 .

[0099] Optionally, the specific steps of forming the first conductive structure 11 on the wiring layer include:

[0100] A third conductive material is deposited on the surface of the second dielectric layer 43 to form the first conductive structure 11 exposing the first plug 13 .

[0101] Optionally, the first conductive structure 11 includes a plurality of pads arranged at intervals along the first direction, and the plurality of wiring layers are distributed one by one under the plurality of pads;

[0102] The surface of the substrate 10 further includes a second plug 31 located between two adjacent wirings 12 below one of the pads, and one end of the second plug 31 is electrically connected to the substrate 10 , and the other end is electrically connected to one of the pads.

[0103] Optionally, the specific step of forming the first conductive structure 11 on the wiring layer further includes:

[0104] A third conductive material is deposited on the surface of the second dielectric layer to form the first conductive structure 11 exposing the first plug 13, and a connection layer is formed at the same time, wherein one end of the connection layer is electrically connected to the first plug 13 at the end of a wiring 12 located under one of the pads, and the other end is electrically connected to another of the pads. Figure 5L , Figure 5M shown. Figure 5L and Figure 5M They are Figure 5K The cross-sectional schematic diagrams at two other angles. The pad is formed simultaneously with the first connection line 141 and the second connection line 142, thereby further simplifying the formation process of the semiconductor structure and reducing the manufacturing cost.

[0105] In other specific embodiments, the base includes a substrate and a second conductive structure 30 located on a surface of the substrate; the first conductive structure 11 is located above the second conductive structure 30;

[0106] The wiring layer includes a plurality of wirings 12 located between the first conductive structure 11 and the second conductive structure 30 . An end of each wiring 12 extends out of the first conductive structure 11 , and at least one first plug 13 is disposed at the end of each wiring 12 extending out of the first conductive structure 11 .

[0107] Optionally, the semiconductor structure includes a plurality of second plugs 31, one end of the second plug 31 is electrically connected to the second conductive structure 30, and the other end of the second plug 31 is electrically connected to the first conductive structure 11;

[0108] Each of the wirings 12 passes through a gap between two adjacent second plugs 31 .

[0109] Optionally, the material of the first conductive structure 11 is a metal material, and the material of the wiring layer is a polysilicon material or a metal material. For example, when the base is a substrate, the material of the wiring layer may be a polysilicon material; when the base includes a substrate and a second conductive structure located on the surface of the substrate, the material of the wiring layer may be a metal material.

[0110] The semiconductor structure and the method for forming the same provided in this specific embodiment avoid occupying the peripheral space coplanar with the first conductive structure by setting the wiring layer between the substrate and the first conductive structure and connecting it to the external circuit through the first plug located at the end of the wiring layer, and there is no need to reduce the area of ​​the first conductive structure. This solves the problem of difficult wiring layout due to the reduction of the cutting path size, avoids the problem of structural layout easily violating the design principles, and ensures the reliability and stability of subsequent test results of the semiconductor structure.

[0111] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A base, wherein the base is a substrate; A first conductive structure, located on the surface of the substrate, wherein the first conductive structure comprises a plurality of pads arranged at intervals along a first direction; a wiring layer, embedded between the substrate and the first conductive structure in a direction perpendicular to the substrate, and extending out of the first conductive structure in a direction parallel to the substrate; A first plug extending in a direction perpendicular to the substrate, one end of the first plug being electrically connected to an end of the wiring layer extending out of the first conductive structure, and the other end being used for connecting to an external circuit, and the material of the first plug being tungsten; The wiring layer includes a plurality of wirings located between the substrate and the pad, an end of each wiring extends out of the pad along the first direction, and at least one first plug is provided at the end of each wiring extending out of the pad, and the first direction is parallel to the substrate; The connection layer is located above the wiring layer in a direction perpendicular to the substrate and is arranged in the same layer as the plurality of pads. One end of the connection layer is electrically connected to the first plug at the end of a wiring below one of the pads, and the other end is electrically connected to another of the pads.

2. The semiconductor structure according to claim 1, characterized in that: Along a second direction, a projection of the pad in a direction perpendicular to the substrate covers a plurality of the wirings located therebelow, and the second direction is parallel to the substrate and perpendicular to the first direction.

3. The semiconductor structure according to claim 1, characterized in that: The material of the first conductive structure is a metal material, and the material of the wiring layer is a polysilicon material or a metal material.

4. A semiconductor structure, characterized in that: include: A substrate, comprising a substrate and a second conductive structure located on a surface of the substrate; A first conductive structure is located on the surface of the substrate, and the first conductive structure is located above the second conductive structure; a wiring layer, embedded between the substrate and the first conductive structure in a direction perpendicular to the substrate, and extending out of the first conductive structure in a direction parallel to the substrate; A first plug extending in a direction perpendicular to the substrate, one end of the first plug being electrically connected to an end of the wiring layer extending out of the first conductive structure, and the other end being used for connecting to an external circuit, and the material of the first plug being tungsten; The wiring layer includes a plurality of wirings located between the first conductive structure and the second conductive structure, an end portion of each of the wirings extends out of the first conductive structure, and at least one first plug is disposed at an end portion of each of the wirings extending out of the first conductive structure; a plurality of second plugs, wherein one end of the second plug is electrically connected to the second conductive structure and the other end of the second plug is electrically connected to the first conductive structure; Each of the wirings passes through a gap between two adjacent second plugs.

5. The semiconductor structure according to claim 4, characterized in that: The material of the first conductive structure is a metal material, and the material of the wiring layer is a polysilicon material or a metal material.

6. A method for forming a semiconductor structure, characterized in that: The steps include: Providing a substrate, wherein the substrate is a substrate; Forming a wiring layer on the surface of the substrate, including: forming a first dielectric layer covering the substrate; etching the first dielectric layer to form a first opening exposing the substrate; depositing a first conductive material in the first opening to form the wiring layer; Forming a first plug at the end of the wiring layer, comprising: forming a second dielectric layer covering the first dielectric layer and the wiring layer; etching the second dielectric layer to form a second opening exposing the end of the wiring layer; depositing a second conductive material in the second opening to form the first plug; the first plug extends in a direction perpendicular to the substrate for connecting to an external circuit; Forming a first conductive structure on the wiring layer, comprising: depositing a third conductive material on the surface of the second dielectric layer to form the first conductive structure exposing the first plug; the end of the wiring layer formed with the first plug extends out of the first conductive structure in a direction parallel to the substrate; Wherein, the first conductive structure comprises a plurality of pads arranged at intervals along a first direction, and the plurality of wiring layers are distributed one by one under the plurality of pads; The substrate surface also includes a second plug located between two adjacent wirings below one of the pads, wherein one end of the second plug is electrically connected to the substrate, and the other end of the second plug is electrically connected to one of the pads.

7. The method for forming a semiconductor structure according to claim 6, characterized in that: The specific steps of forming the wiring layer include: Etching the first dielectric layer to form a plurality of first openings arranged along a second direction, wherein the first openings extend along the first direction and expose the substrate, the first direction is parallel to the substrate, and the second direction is parallel to the substrate and perpendicular to the first direction; A first conductive material is filled into the first openings to form a wiring layer including a plurality of wirings.

8. The method for forming a semiconductor structure according to claim 6, characterized in that: The specific step of forming a first conductive structure on the wiring layer also includes: A third conductive material is deposited on the surface of the second dielectric layer to form the first conductive structure exposing the first plug, and a connecting layer is formed at the same time, wherein one end of the connecting layer is electrically connected to the first plug at the end of a wiring under one of the pads, and the other end is electrically connected to another of the pads.

9. The method for forming a semiconductor structure according to claim 6, characterized in that: The material of the first conductive structure is a metal material, and the material of the wiring layer is a polysilicon material or a metal material.

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