Memory structure and method of forming the same

Abstract

A memory structure and a method for forming the same include: providing a substrate; forming a plurality of memory gate structures separated from each other on the substrate, with an isolation groove between adjacent memory gate structures, the memory gate structure including a floating gate layer and a control gate layer located on the floating gate layer; forming an isolation layer in the isolation groove, wherein the top surface of the isolation layer is lower than the top surface of the control gate layer, and the top surface of the isolation layer is higher than the bottom surface of the control gate layer; forming a notch on the exposed sidewall of the control gate layer, wherein the bottom of the notch is lower than or flush with the top surface of the isolation layer; and forming an initial metal silicide layer on the exposed control gate layer surface and the top surface of the isolation layer. By forming a notch at the junction of the isolation layer and the control gate layer, the surface area of ​​the junction is effectively increased, and the accumulation of the material of the initial metal silicide layer at the junction is avoided, thereby forming a sharp protrusion in the subsequent annealing process, which affects the electrical performance of the memory structure finally formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and a forming method thereof. Background Art

[0002] In recent years, flash memory has developed particularly rapidly. The main feature of flash memory is that it can retain stored information for a long time without power supply.

[0003] NAND flash memory is a better storage solution than hard disk drives. Since NAND flash memory reads and writes data in pages, it is suitable for storing continuous data, such as pictures, audio or other file data. At the same time, it is widely used in the storage field of mobile communication devices and portable multimedia devices due to its low cost, large capacity, fast writing speed and short erasing time.

[0004] However, the performance of the NAND memory structure formed in the prior art still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a memory structure and a method for forming the same, which can avoid material accumulation of the initial metal silicide layer, thereby reducing the formation of sharp protrusions and improving the electrical performance of the finally formed memory structure.

[0006] To solve the above problems, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a plurality of discrete memory gate structures on the substrate, with isolation grooves between adjacent memory gate structures, the memory gate structure comprising a floating gate layer and a control gate layer located on the floating gate layer; forming an isolation layer in the isolation groove, wherein the top surface of the isolation layer is lower than the top surface of the control gate layer, and the top surface of the isolation layer is higher than the bottom surface of the control gate layer; forming a notch on the exposed sidewall of the control gate layer, wherein the bottom of the notch is lower than or flush with the top surface of the isolation layer; and forming an initial metal silicide layer on the exposed surface of the control gate layer and the top surface of the isolation layer.

[0007] Optionally, the storage gate structure further includes: a first gate dielectric layer located between the floating gate layer and the substrate.

[0008] Optionally, the storage gate structure further includes: a second gate dielectric layer located between the floating gate layer and the control gate layer.

[0009] Optionally, the method for forming the storage gate structure and the isolation groove includes: forming a first gate dielectric material film on the substrate; forming a floating gate material film on the first gate dielectric material film; forming a second gate dielectric material film on the floating gate material film; forming a control gate material film on the second gate dielectric material film; forming a mask structure on the control gate material film; forming a patterned layer on the mask structure, the patterned layer having an opening exposing a portion of the mask structure; using the patterned layer as a mask to etch a portion of the mask structure, the control gate material film, the second gate dielectric material film, the floating gate material film and the first gate dielectric material film until the top surface of the substrate is exposed, thereby forming the storage gate structure and the isolation groove; after forming the storage gate structure and the isolation groove, removing the patterned layer and the mask structure.

[0010] Optionally, the floating gate material film and the control gate material film are both made of semiconductor materials.

[0011] Optionally, the semiconductor material includes polysilicon doped with P-type or N-type ions.

[0012] Optionally, the second gate dielectric material film is a single-layer structure or a multi-layer structure.

[0013] Optionally, when the second gate dielectric material film is a multi-layer structure, the second gate dielectric material film includes a first silicon oxide layer located on the floating gate material film, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0014] Optionally, the method for forming the isolation layer and the gap includes: forming an initial isolation layer in the isolation groove, the top surface of the initial isolation layer is lower than the top surface of the control gate layer, and the top surface of the initial isolation layer is higher than the bottom surface of the control gate layer; forming a barrier layer on the exposed surface of the control gate layer; using a first etching process to remove part of the initial isolation layer, exposing part of the control gate layer, and forming the isolation layer; using a second etching process to remove part of the exposed control gate layer to form the gap; after forming the gap, removing the barrier layer.

[0015] Optionally, the height of the portion of the initial isolation layer removed is 50 angstroms to 100 angstroms, and the height is perpendicular to the top direction of the isolation layer.

[0016] Optionally, the depth of the notch is 40 angstroms to 60 angstroms, and the depth is perpendicular to the side wall direction of the control gate layer.

[0017] Optionally, the material of the barrier layer is different from the material of the initial isolation layer.

[0018] Optionally, the material of the barrier layer includes silicon nitride; and the material of the isolation layer includes silicon oxide.

[0019] Optionally, the barrier layer is formed by a rapid thermal nitrogen process.

[0020] Optionally, the first etching process adopts a wet etching process, and the etching solution of the first etching process includes a hydrofluoric acid solution and a hydrogen peroxide solution.

[0021] Optionally, the second etching process adopts a wet etching process, and the etching solution of the second etching process includes a tetramethylammonium hydroxide solution or a mixed solution of hydrogen peroxide and ammonia heated to 60° C. to 80° C.

[0022] Optionally, after forming the initial metal silicide layer, the method further includes: performing annealing treatment on the initial metal silicide layer to make the initial metal silicide layer react with the control gate layer to form a metal silicide layer.

[0023] Optionally, the formation process of the initial metal silicide layer includes a physical vapor deposition process; and the material of the initial metal silicide layer includes a nickel-platinum alloy.

[0024] Optionally, the initial metal silicide layer has a thickness of 150 angstroms to 200 angstroms.

[0025] Correspondingly, the present invention also provides a memory structure formed by any of the above methods, comprising: a substrate; a plurality of discrete memory gate structures located on the substrate, with isolation grooves between adjacent memory structures, the memory gate structure comprising a floating gate layer and a control gate layer located on the floating gate layer; an isolation layer located in the isolation groove, the top surface of the isolation layer being lower than the top surface of the control gate layer, and the top surface of the isolation layer being higher than the bottom surface of the control gate layer; a notch located on the exposed sidewall of the control gate layer, the bottom of the notch being lower than or flush with the top surface of the isolation layer; and an initial metal silicide layer formed on the surface of the control gate layer and the top surface of the isolation layer.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the technical solution of the present invention, a notch is formed on the exposed side wall of the control gate layer, the bottom of the notch is lower than or flush with the top surface of the isolation layer, and the notch is located at the junction of the side wall surface of the control gate layer and the top surface of the isolation layer, effectively increasing the surface area of ​​the junction. Therefore, when the initial metal silicide layer is formed, the material of the initial metal silicide layer is effectively distributed through the increased surface area, avoiding the accumulation of materials. In the subsequent annealing treatment, the formation of sharp protrusions due to material accumulation is reduced.

[0028] Since the tip area of ​​the sharp protrusion is very small and the charge is dense, a strong electric field is easily formed, which reduces the electrical performance of the memory structure finally formed. The technical solution of the present invention reduces the formation of sharp protrusions, thereby reducing the strong electric field formed by the sharp protrusions, thereby improving the electrical performance of the memory structure finally formed.

[0029] Furthermore, in the technical solution of the present invention, the process for forming the barrier layer adopts a rapid thermal nitrogen process. The rapid thermal nitrogen process can directly utilize nitrogen-containing gas to react with the control gate layer to generate silicon nitride, thereby avoiding the problem of using a deposition process to form silicon nitride on both the control gate layer and the initial isolation layer, and subsequently needing to further remove the silicon nitride on the initial isolation layer. The rapid thermal nitrogen process can simplify the manufacturing steps and improve production efficiency.

[0030] Furthermore, in the technical solution of the present invention, the height of the removed portion of the initial isolation layer is 50 angstroms to 100 angstroms. This height range avoids the removal of the initial isolation layer from being too high, which would cause the gap formed by subsequent etching to cause greater damage to the control gate layer; it also avoids the removal of the initial isolation layer from being too low, which would cause the subsequent gap to have a smaller surface area, and would have a poor effect of distributing the initial metal silicide layer material, and would still form more sharp protrusions in the subsequent annealing process, affecting the performance of the memory structure finally formed.

[0031] Furthermore, in the technical solution of the present invention, the depth of the notch is 40 angstroms to 60 angstroms. This depth range can avoid the damage to the control gate layer caused by the deep notch; at the same time, it also avoids the situation that the surface area increased by the notch is small and the effect of distributing the initial metal silicide layer material is poor. In the subsequent annealing process, more sharp protrusions will still be formed, and the sharp protrusions will generate a strong electric field, affecting the performance of the memory structure finally formed.

[0032] Furthermore, in the technical solution of the present invention, the thickness of the initial metal silicide layer is 150 angstroms to 200 angstroms. The initial metal silicide layer formed within this thickness range can meet the requirement of reducing the contact resistance of the control gate layer after the metal silicide layer is subsequently formed through annealing treatment, while avoiding the accumulation of a large amount of the initial metal silicide layer at the junction A, thereby forming a sharp protrusion and affecting the electrical performance of the final memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figures 1 to 3 It is a schematic diagram of a memory structure;

[0034] Figure 4 for Figure 3 Electron microscope image of the initial metal silicide layer after annealing;

[0035] Figures 5 to 12 It is a schematic diagram of the structures of the various steps of an embodiment of a method for forming a memory structure of the present invention. DETAILED DESCRIPTION

[0036] As described in the background art, the performance of the memory structure formed in the prior art needs to be improved.

[0037] Please refer to Figure 1 A substrate 100 is provided, and a plurality of mutually discrete storage gate structures are formed on the provided substrate 100, and isolation trenches 104 are provided between adjacent storage gate structures. The storage structure includes a first gate dielectric layer 107, a floating gate layer 101 located on the first gate dielectric layer 107, a second gate dielectric layer 102 located on the floating gate layer 101, and a control gate layer 103 located on the second gate dielectric layer 102.

[0038] Please refer to Figure 2 , an isolation layer 105 is formed in the isolation trench 101 , wherein a top surface of the isolation layer 105 is lower than a top surface of the control gate layer 103 , and a top surface of the isolation layer 105 is higher than a bottom surface of the control gate layer 103 .

[0039] Please refer to Figure 3 , an initial metal silicide layer 106 is formed on the exposed surface of the control gate layer 103 and the top surface of the isolation layer 105 .

[0040] In the above embodiment, the initial metal silicide layer 106 is subsequently annealed to form a metal silicide layer. The function of the metal silicide layer is to reduce the contact resistance between the control gate layer and the conductive structure and improve the electrical performance of the memory structure. The initial metal silicide layer 106 is formed by a physical vapor deposition process. The initial metal silicide layer 106 formed by the physical vapor deposition process will form an accumulation at the junction A between the control gate layer 103 and the isolation layer 105. This is because the junction A is the intersection of the side wall surface of the control gate layer 103 and the top surface of the isolation layer 105. The initial metal silicide layers 106 of the two planes will form an aggregation at the junction A with a large content, and some sharp protrusions (such as Figure 4 As shown in FIG. 1 , since the tip area of ​​the sharp protrusion is very small and the charge is dense, a strong electric field is easily formed, thereby reducing the electrical performance of the memory structure finally formed.

[0041] On this basis, the present invention provides a memory structure and a method for forming the same. By forming a notch on the side wall of the control gate layer, the notch is located at the junction of the side wall surface of the control gate layer and the top surface of the isolation layer, thereby reducing the material accumulation of the initial metal silicide layer here. In the subsequent annealing treatment, the formation of sharp protrusions due to material accumulation is reduced, and the generation of strong electric fields is avoided, thereby improving the electrical performance of the memory structure.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 5 to 12 , is a structural schematic diagram of a formation process of a memory structure according to an embodiment of the present invention.

[0044] Please refer to Figure 5 , providing a substrate 200.

[0045] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0046] Please continue to refer to Figure 5 A plurality of separate storage gate structures are formed on the substrate 200 , and isolation trenches 204 are provided between adjacent storage gate structures. The storage gate structure includes a floating gate layer 201 and a control gate layer 203 located on the floating gate layer 201 .

[0047] In this embodiment, the storage gate structure further includes: a first gate dielectric layer 207 located between the floating gate layer 201 and the substrate 200 , and a second gate dielectric layer 202 located between the floating gate layer 201 and the control gate layer 203 .

[0048] In this embodiment, the method for forming the storage gate structure and the isolation groove 204 includes: forming a first gate dielectric material film on the substrate 200; forming a floating gate material film on the first gate dielectric material film; forming a second gate dielectric material film on the floating gate material film; forming a control gate material film on the second gate dielectric material film; forming a mask structure on the control gate material film; forming a patterned layer on the mask structure, the patterned layer having an opening exposing a portion of the mask structure; etching a portion of the mask structure, the control gate material film, the second gate dielectric material film, the floating gate material film and the first gate dielectric material film using the patterned layer as a mask until the top surface of the substrate is exposed to form the storage gate structure and the isolation groove 204; after forming the storage gate structure and the isolation groove 204, removing the patterned layer and the mask structure (not shown).

[0049] In this embodiment, the materials of the floating gate material film and the control gate material film are both semiconductor materials. Specifically, the semiconductor material is polysilicon doped with P-type or N-type ions.

[0050] In this embodiment, the mask structure includes a first mask layer located on the initial substrate, and a second mask layer located on the surface of the first mask layer; in other embodiments, the first mask structure may also be a single-layer structure.

[0051] In this embodiment, the patterned layer is located on the second mask layer, the material of the patterned layer includes photoresist, and the formation process of the patterned layer includes a photolithography patterning process; the process of removing the patterned layer includes a wet stripping process or an ashing process, and the gas of the ashing process is an oxygen-containing gas, such as oxygen or ozone.

[0052] In this embodiment, the second gate dielectric layer 202 adopts a multi-layer structure, and the second gate dielectric layer 202 includes a first silicon oxide layer (not labeled) located on the floating gate layer 201, a silicon nitride layer (not labeled) located on the first silicon oxide layer, and a second silicon oxide layer (not labeled) located on the silicon nitride layer.

[0053] The first silicon oxide layer and the second silicon oxide layer of the second gate dielectric layer 202 can be well combined with the base crystal, and the silicon nitride layer is in the middle, which can block the extension of defects (such as pinholes). Therefore, the three-layer structure design can complement the deficiencies.

[0054] In other embodiments, the second gate dielectric layer may also adopt a single-layer structure.

[0055] In this embodiment, an isolation layer is formed in the isolation trench 204, and the top surface of the isolation layer is lower than the top surface of the control gate layer 203, and the top surface of the isolation layer is higher than the bottom surface of the control gate layer 203. A notch is formed on the exposed sidewall of the control gate layer 203, and the bottom of the notch is lower than or flush with the top surface of the isolation layer. For the formation process of the isolation layer and the notch, please refer to Figures 6 to 11 .

[0056] Please refer to Figure 6 , an initial isolation layer 205 is formed in the isolation trench 204 , wherein a top surface of the initial isolation layer 205 is lower than a top surface of the control gate layer 203 , and a top surface of the initial isolation layer 205 is higher than a bottom surface of the control gate layer 203 .

[0057] In this embodiment, the method for forming the initial isolation layer 205 includes: forming an isolation material film in the isolation groove 204, and the isolation material film fills the isolation groove 204; etching back a portion of the isolation material film to form the initial isolation layer 205, and the top surface of the initial isolation layer 205 is lower than the top surface of the control gate layer 203, and the top surface of the initial isolation layer 205 is higher than the bottom surface of the control gate layer 203 (not shown).

[0058] Please refer to Figure 7 , a blocking layer 208 is formed on the exposed surface of the control gate layer 203 .

[0059] The barrier layer 208 and the initial isolation layer 205 are made of different materials. This is to ensure that when the initial isolation layer 205 is subsequently etched, a larger etching selectivity ratio can be generated between the barrier layer 208 and the initial isolation layer 205 .

[0060] In this embodiment, the material of the barrier layer 208 is silicon nitride, and the material of the initial isolation layer 205 is silicon oxide.

[0061] In this embodiment, the barrier layer 208 is formed by a rapid thermal nitrogen process.

[0062] The parameters of the rapid thermal nitrogen process are: the reaction gas includes NH3, NO or N2O, the temperature is 600°C to 1100°C, and the time is 5s to 180s.

[0063] The rapid thermal nitrogen process can directly utilize nitrogen-containing gas to react with the control gate layer 203 to generate silicon nitride, thereby avoiding the problem of using a deposition process to form silicon nitride on both the control gate layer 203 and the initial isolation layer 205, and subsequently needing to further remove the silicon nitride on the initial isolation layer 205. The rapid thermal nitrogen process can simplify the manufacturing steps and improve production efficiency.

[0064] Please refer to Figure 8 , using a first etching process to remove a portion of the initial isolation layer 205 , exposing a portion of the control gate layer 203 , and forming the isolation layer 209 .

[0065] In this embodiment, the first etching process adopts a wet etching process, and the etching solution of the first etching process is a hydrofluoric acid solution and a hydrogen peroxide solution.

[0066] A portion of the initial isolation layer 205 is removed by a first etching process to form the isolation layer 209 . The top surface of the isolation layer 209 is lower than the top surface of the control gate layer 203 , and the top surface of the isolation layer 209 is higher than the bottom surface of the control gate layer 203 .

[0067] Specifically, the top surface of the isolation layer 209 is lower than the bottom of the barrier layer 208 . The purpose of this is to subsequently form a gap on the side wall of the control gate layer 203 exposed between the bottom of the barrier layer 208 and the top surface of the isolation layer 209 .

[0068] In this embodiment, the height of the removed portion of the initial isolation layer 205 is 50 angstroms to 100 angstroms, and the height is perpendicular to the top direction of the isolation layer 209. If the height of the removed initial isolation layer 205 is too high, the height of the exposed side wall of the control gate layer 203 is also high, and the gap formed by subsequent etching will be large, so that the damage to the control gate layer 203 is also large, which will affect the performance of the memory structure finally formed; if the height of the removed initial isolation layer 205 is too low, the height of the exposed side wall of the control gate layer 203 is also low, and the gap formed by subsequent etching will be small, and the surface area increased by the gap is also small, so that when the initial metal silicide layer is subsequently deposited, the material of the initial metal silicide layer will still accumulate at the junction A between the isolation layer 209 and the control gate layer 203, and then form a sharp protrusion after annealing, and the sharp protrusion generates a strong electric field, which affects the performance of the memory structure finally formed.

[0069] Please refer to Fig. 9 , a second etching process is used to remove a portion of the exposed control gate layer 203 to form the gap 210 .

[0070] In this embodiment, the second etching process adopts a wet etching process, and the etching solution of the second etching process is a tetramethylammonium hydroxide solution (TMAH). Since the etching rate of the tetramethylammonium hydroxide solution on the {100} crystal plane family and the {110} crystal plane family of semiconductor materials is greater than the etching rate on the {111} crystal plane family of semiconductor materials, the formed gap 210 can be processed into a sigma shape, and the sigma shape can further increase the surface area of ​​the gap 210, thereby better sharing the material of the initial metal silicide layer deposited subsequently, avoiding the accumulation of materials, and reducing the formation of sharp protrusions due to material accumulation in the subsequent annealing process.

[0071] In other embodiments, the etching solution of the second etching process may also be a mixed solution of hydrogen peroxide and ammonia heated to 60° C. to 80° C.

[0072] The notch 210 is formed on the exposed sidewall of the control gate layer 203 by the second etching process. The bottom of the notch 210 is lower than or flush with the top surface of the isolation layer 209 , and the bottom direction of the notch 210 is parallel to the top surface of the isolation layer 209 .

[0073] Since the notch 210 is located at the junction A between the side wall surface of the control gate layer 203 and the top surface of the isolation layer 209, the surface area of ​​the junction A is effectively increased by the notch 210. Therefore, when the initial metal silicide layer is subsequently formed, the material of the initial metal silicide layer is effectively distributed through the increased surface area, thereby avoiding the accumulation of materials. During the annealing treatment of the initial metal silicide layer, the formation of sharp protrusions due to material accumulation is reduced, thereby reducing the strong electric field formed by the sharp protrusions, which affects the electrical performance of the finally formed memory structure.

[0074] In this embodiment, the depth of the notch 210 is 40 angstroms to 60 angstroms, and the depth is perpendicular to the side wall direction of the control gate layer 203. If the depth of the notch 210 is deep, the damage to the control gate layer 203 is also large, which will affect the performance of the memory structure finally formed; if the depth of the notch 210 is shallow, the surface area increased by the notch 210 is also small, so that when the initial metal silicide layer is subsequently deposited, the material of the initial metal silicide layer will still accumulate at the junction A between the isolation layer and the control gate layer, and then form a sharp protrusion during the annealing process, and the sharp protrusion generates a strong electric field, which affects the performance of the memory structure finally formed.

[0075] Please refer to Fig.10 After forming the notch 210 , the barrier layer 208 is removed.

[0076] In this embodiment, the blocking layer 208 is removed by a third etching process, the third etching process adopts an isotropic wet etching process, and the etching solution adopts a hydrofluoric acid solution and a hydrogen peroxide solution.

[0077] Please refer to Fig.11 , an initial metal silicide layer 206 is formed on the exposed surface of the control gate layer 203 and the top surface of the isolation layer 209 .

[0078] Since the notch 210 is formed at the junction A, the surface area of ​​the junction A is effectively increased. Therefore, when depositing the initial metal silicide layer 206, the increased surface area of ​​the notch 210 can effectively distribute the material of the initial metal silicide layer 206, thereby avoiding the accumulation of the material of the initial metal silicide layer 206 at the junction A.

[0079] In this embodiment, the material of the initial metal silicide layer 206 is a nickel-platinum alloy, in which nickel accounts for 90% and platinum accounts for 10%.

[0080] The initial metal silicide layer 206 is formed by a physical vapor deposition process; the thickness of the initial metal silicide layer is 150 angstroms to 200 angstroms.

[0081] The initial metal silicide layer 206 formed within this thickness range can meet the requirement of reducing the contact resistance of the control gate layer 203 after the metal silicide layer is subsequently formed through annealing treatment, while avoiding the accumulation of a large amount of the initial metal silicide layer 206 at the junction A, thereby forming a sharp protrusion and affecting the electrical performance of the final memory structure.

[0082] Please refer to Fig.12 After the initial metal silicide layer 206 is formed, the initial metal silicide layer 206 is annealed to allow the initial metal silicide layer 206 to react with the control gate layer 203 to form a metal silicide layer 211 .

[0083] The function of the metal silicide layer 211 is to reduce the contact resistance between the control gate layer 203 and the conductive structure, thereby improving the electrical performance of the memory structure.

[0084] In this embodiment, the annealing treatment includes a first annealing process and a second annealing process. The parameters of the first annealing process include: annealing temperature 270℃~290℃, annealing time 30s~120s; the parameters of the second annealing process include: annealing temperature 450℃~500℃, annealing time 30s~120s.

[0085] Please continue to refer to Fig.11 Accordingly, the present invention also provides a memory structure formed by the above method, comprising: a substrate 200; a plurality of mutually discrete memory gate structures located on the substrate 200, with an isolation groove between adjacent memory structures, the memory gate structure comprising a floating gate layer 201 and a control gate layer 203 located on the floating gate layer 201; an isolation layer 209 located in the isolation groove, the top surface of the isolation layer 209 being lower than the top surface of the control gate layer 203, and the top surface of the isolation layer 209 being higher than the bottom surface of the control gate layer 203; a notch 210 located on the sidewall exposed by the control gate layer 203, the bottom of the notch 210 being lower than or flush with the top surface of the isolation layer 209; and an initial metal silicide layer 206 formed on the surface of the control gate layer 203 and the top surface of the isolation layer 209.

[0086] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a memory structure, characterized in that: include: providing a substrate; Forming a plurality of mutually independent storage gate structures on the substrate, with isolation trenches between adjacent storage gate structures, the storage gate structure comprising a floating gate layer and a control gate layer located on the floating gate layer; forming an isolation layer in the isolation trench, wherein a top surface of the isolation layer is lower than a top surface of the control gate layer, and a top surface of the isolation layer is higher than a bottom surface of the control gate layer; forming a notch on the exposed sidewall of the control gate layer, wherein the bottom of the notch is lower than or flush with the top surface of the isolation layer; An initial metal silicide layer is formed on the exposed surface of the control gate layer and the top surface of the isolation layer, and the initial metal silicide layer on the sidewall of the control gate layer protrudes from the sidewall of the floating gate layer; wherein, The method for forming the isolation layer and the gap includes: forming an initial isolation layer in the isolation groove, wherein the top surface of the initial isolation layer is lower than the top surface of the control gate layer, and the top surface of the initial isolation layer is higher than the bottom surface of the control gate layer; forming a barrier layer on the exposed surface of the control gate layer; using a first etching process to remove part of the initial isolation layer, exposing part of the control gate layer, and forming the isolation layer; using a second etching process to remove part of the exposed control gate layer to form the gap; after forming the gap, removing the barrier layer.

2. The method for forming a memory structure according to claim 1, wherein: The storage gate structure further includes: a first gate dielectric layer located between the floating gate layer and the substrate.

3. The method for forming a memory structure according to claim 2, wherein: The storage gate structure further includes: a second gate dielectric layer located between the floating gate layer and the control gate layer.

4. The method for forming a memory structure according to claim 3, wherein: The method for forming the storage gate structure and the isolation groove comprises: forming a first gate dielectric material film on the substrate; forming a floating gate material film on the first gate dielectric material film; forming a second gate dielectric material film on the floating gate material film; forming a control gate material film on the second gate dielectric material film; forming a mask structure on the control gate material film; forming a patterned layer on the mask structure, the patterned layer having an opening exposing part of the mask structure; etching part of the mask structure, the control gate material film, the second gate dielectric material film, the floating gate material film and the first gate dielectric material film using the patterned layer as a mask until the top surface of the substrate is exposed, thereby forming the storage gate structure and the isolation groove; after forming the storage gate structure and the isolation groove, removing the patterned layer and the mask structure.

5. The method for forming a memory structure according to claim 4, wherein: The floating gate material film and the control gate material film are both made of semiconductor materials.

6. The method for forming a memory structure according to claim 5, wherein: The semiconductor material includes polysilicon doped with P-type or N-type ions.

7. The method for forming a memory structure according to claim 4, wherein: The second gate dielectric material film is a single-layer structure or a multi-layer structure.

8. The method for forming a memory structure according to claim 7, wherein: When the second gate dielectric material film is a multi-layer structure, the second gate dielectric material film includes a first silicon oxide layer located on the floating gate material film, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

9. The method for forming a memory structure according to claim 1, wherein: The height of the removed portion of the initial isolation layer is 50 angstroms to 100 angstroms, and the height is perpendicular to the top direction of the isolation layer.

10. The method for forming a memory structure according to claim 1, wherein: The depth of the notch is 40 angstroms to 60 angstroms, and the depth is perpendicular to the side wall direction of the control gate layer.

11. The method for forming a memory structure according to claim 1, wherein: The material of the barrier layer is different from that of the initial isolation layer.

12. The method for forming a memory structure according to claim 11, wherein: The material of the blocking layer includes silicon nitride; the material of the isolation layer includes silicon oxide.

13. The method for forming a memory structure according to claim 12, wherein: The barrier layer is formed by a rapid thermal nitrogen process.

14. The method for forming a memory structure according to claim 1, wherein: The first etching process adopts a wet etching process, and the etching solution of the first etching process includes a hydrofluoric acid solution and a hydrogen peroxide solution.

15. The method for forming a memory structure according to claim 1, wherein: The second etching process adopts a wet etching process, and the etching solution of the second etching process includes a tetramethylammonium hydroxide solution or a mixed solution of hydrogen peroxide and ammonia heated to 60° C. to 80° C.

16. The method for forming a memory structure according to claim 1, wherein: After forming the initial metal silicide layer, the method further includes: performing annealing treatment on the initial metal silicide layer to make the initial metal silicide layer react with the control gate layer to form a metal silicide layer.

17. The method for forming a memory structure according to claim 1, wherein: The formation process of the initial metal silicide layer includes a physical vapor deposition process; the material of the initial metal silicide layer includes a nickel-platinum alloy.

18. The method for forming a memory structure according to claim 1, wherein: The thickness of the initial metal silicide layer is 150 angstroms to 200 angstroms.

19. A memory structure formed by the method according to any one of claims 1 to 18, characterized in that: include: substrate; A plurality of memory gate structures separated from each other and located on the substrate, with isolation trenches between adjacent memory structures, the memory gate structures comprising a floating gate layer and a control gate layer located on the floating gate layer; an isolation layer located in the isolation trench, wherein a top surface of the isolation layer is lower than a top surface of the control gate layer, and a top surface of the isolation layer is higher than a bottom surface of the control gate layer; A notch is located on the exposed sidewall of the control gate layer, and the bottom of the notch is lower than or flush with the top surface of the isolation layer.

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