Voltage Source Converter Generating Pulse Trains Using Two Voltage Levels

Abstract

The voltage source converter (10) comprises a first converter arm (ua) connected between a junction (j) and a first DC terminal (DC1), a second converter arm (la) connected between the junction and a second DC terminal (DC2), and a capacitor string (C1, C2) connected between the DC terminals. The arm (ua, la) comprises cells (Cua1, Cua2, Cua3, Cua4, Cla1, Cla2, Cla3, Cla4). The converter comprises a control unit (12) which controls a group of cells (Cua1, Cua2, Cua3, Cua4) used in conversion for commutating a current passing through one of the arms (ua), wherein the group comprises the cells of this arm. In this control, the control unit (12) obtains a current (I DCL ) value and inserts or bypasses the cell (Cua4) selected as the last used in the group to reach one of the levels when the current is at zero level.

Description

Technical Field

[0001] The present invention relates generally to voltage source converters. More particularly, the present invention relates to a voltage source converter configured to generate a pulse train using two voltage levels. Background Art

[0002] Modular multilevel converters are often used in different high voltage applications. MMC uses submodules in a phase leg between two direct current (DC) terminals for forming a sinusoidal waveform, such as an alternating current (AC) waveform. Such a submodule includes a pair of switches in parallel with a capacitor.

[0003] Quasi-two-level (Quasi-Two Level, Q2L) conversion technology has been introduced into various high-voltage applications, such as into power transmission and distribution systems. Q2L conversion technology uses a unit similar to a submodule of MMC. The Q2L converter more particularly uses two converter arms with a unit connected in parallel with a DC link capacitor. These units include a main switch in parallel with an auxiliary switch and a buffer capacitor. However, in the Q2L technology, a single pulse train with pulses between two voltage levels is generated using a unit. This type of technology is described, for example, by Gowaid et al. in "Quasi Two-Level Operation of Modular Multilevel Converter for Use in a High-Power DC Transformer WithDC Fault Isolation Capability", IEEE Transactions On Power Electronics, Vol.30, No.1, January 2015. It is also described by Mertens and Kucka in “Quasi Two-Level PWM Operation of an MMC Phase Leg With Reduced Module Capacitance”, IEEE Transactions On Power Electronics, Vol. 31, No. 10, October 2016. The Q2L converter can be considered as an intermediate step between a standard two-level (2L) converter and MMC. During the transition between the two voltage levels present in the phase voltage waveform of the 2L converter, which is t DThe dwell time is stepped. This is done to limit the dv / dt generated by the converter during this transition. Higher dv / dt values ​​may lead to increased electromagnetic interference (EMI) and insulation stress on the reactors connected to the converter. Moreover, in Q2L, there are no advanced requirements on the gate unit, because the series connection relies on active snubbers and not on advanced gate units.

[0004] The Q2L converter has an advantage over MMC because the required capacitance of each cell is much lower than the corresponding capacitance of each submodule. This reduction in capacitance occurs because each cell capacitance is only charged or discharged during the time when the transition between the upper and lower arms of one phase leg occurs. This is significantly less than the charge / discharge time experienced by the submodule capacitors in MMC.

[0005] A problem with the use of a Q2L converter is that resonances may appear in the converter arm currents, the energy of which is dissipated over time as converter losses.

[0006] Therefore, it is necessary to limit this resonance in order to limit this loss.

[0007] Therefore, it is of interest to obtain improvements in Q2L technology in limiting resonances. Summary of the invention

[0008] The present invention aims to limit the resonance caused by the operation of a voltage source converter using a quasi-two-level conversion technique.

[0009] According to a first aspect, the object is achieved by a voltage source converter configured to generate a pulse train using two voltage levels, the converter comprising: a first converter arm connected between a junction and a first DC terminal having a first voltage level; a second converter arm connected between the junction and a second DC terminal having a second voltage level; and a capacitor string connected between the first DC terminal and the second DC terminal, wherein at least one of the converter arms comprises a cell;

[0010] The voltage source converter further comprises a control section controlling a group of cells used in the transformation between two voltage levels for commutating a current travelling through a corresponding one of the converter arms involved in the transformation, the group comprising the cells of the converter arms,

[0011] Wherein the control section, when controlling a cell group, is configured to obtain a value of a current traveling between the capacitor string and the converter arm, and to process a cell in the group selected as last used to reach one of the voltage levels, the processing comprising inserting or bypassing the cell when the current between the capacitor string and the converter arm is at a zero level.

[0012] According to a second aspect, the object is achieved by a method of limiting resonance in a voltage source converter, the voltage source converter using two voltage levels to generate a pulse train, the converter comprising: a first converter arm connected between a junction and a first DC terminal having a first voltage level; a second converter arm connected between the junction and a second DC terminal having a second voltage level; and a capacitor string connected between the first DC terminal and the second DC terminal, wherein at least one of the converter arms comprises cells, the method comprising controlling a group of cells used in a transformation between the two voltage levels for commutating a current travelling through a corresponding one of the converter arms involved in the transformation, the group comprising the cells of the converter arms,

[0013] The control of unit groups includes

[0014] obtain the value of the current traveling between the capacitor string and the converter arm, and

[0015] A cell in the group selected as last used is processed to reach one of the voltage levels, the processing comprising inserting or bypassing the cell when the current between the capacitor string and the converter arm is at a zero level.

[0016] According to a third aspect, the object is achieved by a computer program product for limiting resonance in a voltage source converter, the voltage source converter generating a pulse train using two voltage levels, the voltage source converter generating a pulse train using two voltage levels, the converter comprising: a first converter arm connected between a junction and a first DC terminal having a first voltage level; a second converter arm connected between the junction and a second DC terminal having a second voltage level; and a capacitor string connected between the first DC terminal and the second DC terminal, wherein at least one of the converter arms comprises a cell, the converter comprising a control section controlling a group of cells used in the conversion between the two voltage levels for commutating a current travelling through a corresponding one of the arms involved in the conversion, the group comprising the cells of the converter arm,

[0017] The computer program product comprises a data carrier carrying computer program code, which causes a control unit of a control group to

[0018] obtain the value of the current traveling between the capacitor string and the converter arm, and

[0019] The cell selected as the last used in the group is processed to reach one of the voltage levels, the processing including inserting or bypassing the cell when the current between the capacitor string and the arm is at a zero level.

[0020] The last cell of the conversion may be the cell actively selected by the control to be used last in the conversion. However, it is not necessarily the cell that is physically connected last in the cell structure, such as in a converter arm.

[0021] According to some other aspects, the selection is performed during the transition, ie when the commutation process is ongoing. Thus, the method may further comprise selecting the cell that was last used in the transition during the transition, ie when the commutation is ongoing.

[0022] The value of the current traveling between the capacitor string and the converter arm may be one or more measurements of the current.

[0023] In the conversion, there is also a dwell time during which the cell group remains in an intermediate step of transition between two levels.The capacitors of the cell group can be connected in parallel with a branch of capacitors during commutation, the branch comprising at least one of the capacitors of the string.

[0024] The control section may also be configured to obtain a cell voltage of the group of cells. The cell voltage may include one or more measured values ​​of the cell voltage of each cell in the group.

[0025] In a first variation of the first aspect, the control section may be further configured to determine a difference between a voltage of a branch of the capacitor and a sum of cell voltages provided by the cell group, wherein the last cell is processed when the voltage difference is negative.

[0026] In a corresponding first variant of the second aspect, the method in this case comprises determining the difference between the voltage of a branch of the capacitor and the sum of the cell voltages provided by the group of cells, wherein the last cell is processed when the voltage difference is negative.

[0027] According to a second variation of the first aspect, the control section is further configured to sort the cells according to the cell voltage balancing scheme so that the last cell to be inserted or bypassed is the last cell of the cell sequence obtained by the sorting.

[0028] According to a corresponding second variation of the second aspect, the method further comprises sorting the cells according to a cell voltage balancing scheme such that the last inserted or bypassed cell is the last cell of the cell sequence obtained by the sorting.

[0029] The cell last used in the transition between the two voltage levels may be selected by the control section before the transition has been started. Therefore, the method may further include selecting the cell last used in the transition between the two voltage levels before the transition has been started.

[0030] The current running between the capacitor string and the converter arm can additionally be obtained before the switching is started.

[0031] When this is done, the control section may also be configured to predict when the current traveling between the DC link capacitor string and the converter arm will reach zero according to the cell voltage balancing scheme, based on the obtained current and cell sequence, and process the selected cell at the predicted zero level.

[0032] When this is done, the method may further include predicting when the current traveling between the DC link capacitor string and the converter arm will reach zero based on the obtained current and cell sequence according to the cell voltage balancing scheme. In this case, processing of the selected cell is performed at the predicted zero level.

[0033] Dwell time can also be taken into account in the prediction.

[0034] The cell voltages of the cells in the group can likewise be obtained before the switching is started.

[0035] In this case, the control section may additionally be configured to predict the sum of cell voltages provided by the cell group during conversion based on the obtained cell voltages and the cell sequence, predict when the voltage difference is negative, and process the last cell when the voltage difference is predicted to be negative.

[0036] In this case, the method may additionally include predicting the sum of the cell voltages provided by the cell group during the transformation based on the obtained cell voltages and the cell sequence, and predicting when the voltage difference is negative. In this case, the processing of the selected cell may be performed when the voltage difference is predicted to be negative.

[0037] Dwell time can also be considered in these latter predictions.

[0038] In some variations of the voltage source converter, the first converter arm and the second converter arm comprise a cell.

[0039] It is also possible to use different control schemes in the transition between the two voltage levels, wherein in a first scheme the processing of the cells of the first and second arm is interleaved and in a second scheme the cells of one arm are first fully processed before processing the cells of the other arm.

[0040] The last cell processed may comprise the last cell inserted into the first converter arm, which may be done for the transition from the first voltage level to the second voltage level in both schemes.

[0041] The last processed cell may comprise the last bypassed cell in the second converter arm, which may be done for a transition from the first voltage level to the second voltage level in the first approach.A branch of capacitors may also comprise a complete chain of capacitors.

[0042] The sum of the cells of the arm may be rated for the full converter voltage, ie the difference between the first voltage and the second voltage. Thus, the cells are combinedly sized to handle the full converter voltage.

[0043] In some variations of the voltage source converter, it also includes a third converter arm connected between the junction and a neutral point having a third voltage level between the first voltage level and the second voltage level, the neutral point being a midpoint of the capacitor string connected between the first DC terminal and the second DC terminal.

[0044] In such a voltage source converter comprising a neutral branch, the capacitor branch may comprise half of the capacitor string.

[0045] It is possible that when the converter comprises a neutral branch, the first converter arm and the second converter arm comprise a unit and the neutral branch comprises a bidirectional switch for connecting the contact to the neutral point. Alternatively, the first converter arm and the second converter arm may comprise a switch and a neutral branch unit.

[0046] The cell may have a unipolar voltage contribution capability, which may be achieved by having the cell in a half-bridge configuration.

[0047] Each cell may include a first main switch, a first auxiliary switch, and a buffer capacitor, wherein the first main switch of the cell is configured to switch between two voltage levels, and the first auxiliary switch of the cell is configured to connect the buffer capacitor to introduce a positive slope or a negative slope in the transition between the two voltage levels. Each cell may additionally include a first damping resistor between the first auxiliary switch and the buffer capacitor.

[0048] It is also possible that each cell comprises a first diode bypassing the first damping resistor. In a variant, the first diode is connected between a first connection point and a second connection point, wherein the first connection point is the connection point between the first auxiliary switch and the first main switch, and the second connection point is the connection point between the first damping resistor and the buffer capacitor.

[0049] Alternatively or additionally, the cell may have a bipolar voltage contribution capability, for example be implemented as a full-bridge cell, ie a cell having a full-bridge structure.

[0050] It is also possible that at least one arm comprising a cell also comprises switches. In this case, these switches are configured to be switched on when the cell of the arm is operated to switch between two of the voltage levels.

[0051] If the arm includes cells with bipolar voltage contribution capability, each cell with bipolar voltage contribution capability may include a second main switch and a second auxiliary switch, wherein the second main switches of the cells are configured to switch between two voltage levels, one of which is different from those of the first main switch, and the second auxiliary switches of the cells are configured to connect a buffer capacitor to introduce a slope in the transition between the two levels operated by the second auxiliary switch.

[0052] In case the cells have bipolar voltage contribution capability, these cells may comprise a second damping resistor between the second auxiliary switch and the buffer capacitor.

[0053] The unit with bipolar voltage contribution capability may additionally include a second diode bypassing the second damping resistor. Such bypass may include the second diode being connected between the third contact and the second contact, and the second damping resistor being connected to the second contact. The third contact may be a contact between the second main switch and the second auxiliary switch. Alternatively, the second diode may be connected in parallel with the second damping resistor.

[0054] If other cell structures than half-bridge and full-bridge cell structures are used in the converter, the switches of these other cell structures may be provided with damping resistors in a similar manner and optionally also with snubber diodes.

[0055] The switches of the cell may be metal oxide semiconductor field effect transistor (MOSFET) switches or similar switches or combinations of switches with bidirectional current handling capability. They may also be wide bandgap devices such as gallium nitride (GaN) switches or silicon carbide (SiC) switches, i.e. switches on a SiC substrate.

[0056] For a fundamental AC frequency of 50 or 60 Hz, i.e., for a time period of 0.02 to 0.017 seconds, the dwell time may be in the range of tens to hundreds of nanoseconds. Thus, the period may be 10 times the dwell time. 4 Up to 10 6 times.

[0057] The present invention has many advantages. It reduces the losses caused by the occurrence of resonance by using a quasi-two-level (Q2L) conversion technique. Efficiency is thereby also improved. This can be achieved without the need for any additional hardware or special cell design. It is possible to implement the present invention only by additional software, which also makes it economical. The current stress on the components is also limited, which allows the component size to be reduced. It also improves the tolerance of the cell capacitor voltage ripple, allows the capacitance to be reduced, and relaxes the dwell time requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The present invention will be described below with reference to the accompanying drawings, in which

[0059] Figure 1 schematically illustrates a first cell based voltage source converter,

[0060] FIG. 2A shows a diagram for Figure 1 A first variant of the converter using a half-bridge unit,

[0061] FIG. 2B shows a diagram for Figure 1 The second variant of the converter using the half-bridge unit,

[0062] FIG. 2C shows a diagram for Figure 1 The third variant of the converter using the half-bridge unit,

[0063] Figure 3 Schematically shows various voltages and currents of the converter for normal operation,

[0064] Figure 4 A flow chart showing a plurality of method steps for controlling a converter in a first manner for limiting resonance,

[0065] Figure 5 shows the various voltages and currents in the converter during control for limiting resonance,

[0066] Figure 6 A flow chart showing a plurality of method steps for controlling a converter in a second manner for limiting resonance,

[0067] Figure 7 A second cell-based voltage source converter is schematically shown,

[0068] Figure 8 schematically shows a full bridge cell that can be used in a converter, and

[0069] Fig. 9 A storage medium is shown on which computer program code for implementing the resonance limiting functionality may be provided. DETAILED DESCRIPTION

[0070] Hereinafter, a detailed description will be given of preferred embodiments of the present invention.

[0071] Figure 1 One variation of a converter is shown in the form of a cell based voltage source converter 10. The converter operates to convert between alternating current (AC) and direct current (DC). Figure 1 The converter 10 in FIG. 1 is shown as comprising two arms, which are associated with a single AC phase. However, it should be appreciated that there may be three different phases, and therefore a total of six different arms, with two arms per phase.

[0072] As can be seen from the figure, there is a first upper converter arm ua, which has a first end connected to the first DC terminal DC1 through an upper link inductor Ldc / 2 and a second end connected to the first junction j. There is also a second lower converter arm la, which has a first end connected to the junction j and a second end connected to the second DC terminal DC2 through a lower link inductor Ldc / 2. There is also a series of capacitors C1 and C2 connected between the first DC terminal DC1 and the second DC terminal DC2. A first AC terminal AC1 is also provided at the junction j, at which the output voltage is provided.

[0073] In the three-phase case, there will be three arm groups, with each group comprising an upper arm and a lower arm connected to corresponding AC terminals, the first arms of all groups connected to a first DC terminal, and all second arms connected to a second DC terminal.

[0074] The first DC terminal DC1 may be connected to a first pole of a DC power transmission system, such as a High Voltage Direct Current (HVDC) power transmission system, and the second DC terminal DC2 may be connected to a second pole of the same system.

[0075] The first DC terminal DC1 also has a first potential or voltage level +Vdc / 2, which may be positive. Therefore, the first pole may also be referred to as a positive pole. The second DC terminal DC2 has a second potential or voltage level -Vdc / 2, and therefore the second pole may be referred to as a negative pole. The AC terminal AC1 may be connected to an AC system, for example, via a transformer.

[0076] As mentioned above, Figure 1 The type of voltage source converter shown in is only one example of a converter in which the present invention may be used. For example, the converter may be used as a reactive compensation device, such as a static compensator.

[0077] Figure 1The voltage source converter depicted in has a symmetrical unipolar configuration. Therefore, it is connected between a positive potential and a negative potential. As an alternative, it can be connected in an asymmetrical unipolar configuration or a symmetrical bipolar configuration.

[0078] exist Figure 1 In the example given, there are four cells connected in series or cascade in the upper arm ua and the lower arm la. Therefore, the upper arm ua includes four cells Cua1, Cua2, Cua3 and Cua4, while the lower arm la includes four cells Cla1, Cla2, Cla3 and Cla4. A voltage of Vdc / n is applied across each cell, where n is the sum of the cells in the upper or lower arm, meaning that the sum of the cells in the arm provides a voltage of Vdc. However, Figure 1 The rated value of the unit in the arm of the converter in is usually Vdc / n. In addition, the upper arm voltage Vua and the DC link current I between the DC capacitor string and the upper arm ua are also indicated. DCL This current, also called DC link current, travels from the first DC terminal DC1 through the upper arm ua towards the AC terminal AC1.

[0079] Figure 1 The number of cells provided in is only an example. It must therefore be emphasized that the number of cells in an arm may vary, wherein the number generally depends on the shape to be produced in the AC terminal AC1 and the magnitude of the voltages involved.

[0080] A control unit 12 is also provided for controlling all arms of the converter 10. However, in order to simplify the diagram, Figure 1 In FIG. 1 , only dashed arrows are used to indicate the control of the units Cua1 , Cua2 , Cua3 and Cua4 in the upper arm ua. The control section 12 may be implemented by a computer or processor with an associated program memory. Other types of implementations such as using a field programmable gate array (FPGA) are also possible.

[0081] As mentioned above, in Figure 1 The upper arm ua and the lower arm la of the voltage source converter 10 in the example in include a unit. A unit is a part that can be switched when changing between two voltage levels at a junction j. More particularly, a unit is provided for giving a slope to the edge of a pulse generated at a junction j, the slope being a positive slope when changing from Vdc / 2 to +Vdc / 2, and a negative slope when changing from +Vdc / 2 to -Vdc / 2. Positive slope and negative slope are two types of slopes that can be provided in the conversion. A unit with a unipolar voltage contribution capability, such as a unit with a half-bridge structure, is suitable for use in the upper arm ua and the lower arm la. An example of such a unit is schematically shown in FIG. 2A. FIG. 2B and FIG. 2C show variations of the unit.

[0082] The cell Cua1 shown in FIG. 2A comprises a first main switch MSW, and in parallel with this first main switch MSW there is a branch comprising a buffer capacitor Csn in series with a second auxiliary switch ASW. In the cell Cua1 shown in FIG. 2A there is also an optional damping resistor Rd connected in the branch between the auxiliary switch ASW and the buffer capacitor Csn. There is also a cell inductor Lc having a first end connected to the junction between the main switch MSW and the auxiliary switch ASW. The first connection terminal of the cell Cua1 is in this case arranged at the first junction between the two switches MSW and ASW, and the second connection terminal is arranged at the second end of the cell inductor Lc. The cell Cua1 can be switched to provide a voltage contribution corresponding to the voltage of the buffer capacitor Csn or a zero voltage contribution. When providing a voltage corresponding to the voltage of the buffer capacitor Csn, the cell Cua1 inserts the voltage of the buffer capacitor Csn into the arm containing it. When the cell Cua1 does not provide a voltage or provides a zero voltage, the buffer capacitor Csn is bypassed and the voltage is thereby removed. Thus, the unit can be considered to be inserted or alternatively bypassed. In the example given here, the switch is implemented as a semiconductor switch in the form of a metal oxide semiconductor field effect transistor (MOSFET) switch, which can be arranged on a suitable substrate, such as silicon (S) or silicon carbide (Si), wherein SiC is preferred. Therefore, the switch is a Si switch or a SiC switch. It should be appreciated that other types of semiconductor implementations can be used, such as insulated gate bipolar transistors (IGBTs) and reverse parallel diodes on suitable substrates such as Si or SiC. The reverse parallel diode is built into the MOSFET. However, in the figure, they are shown as being external, which is done to better understand the operation. As mentioned above, the damping resistor Rd can also be omitted. When the damping resistor Rd is included, a buffer diode Dsn can also be included, which bypasses the damping resistor Rd and conducts current toward the buffer capacitor Csn. One such variation is shown in FIG. 2B, in which the buffer diode Dsn is connected in parallel with the damping resistor Rd.

[0083] Another variation is shown in FIG. 2C , in which a snubber diode Dsn is connected between a first junction, which is the junction between the two switches ASW and MSW, and a second junction, which is the junction between a damping resistor Rd and a snubber capacitor Csn.

[0084] As mentioned above, the cell is used to introduce a slope in the transition between two voltage levels. The operation for achieving this will now be described in more detail.

[0085] The voltage on the AC output AC1 is a pulse train in which the voltage changes between two levels, a high level defined by +Vdc / 2 and a low level defined by -Vdc / 2. In the transition from one level to the other, the control section 12 inserts or bypasses the unit from the arm so that a step is made, which causes a slope in the transition between the two levels. This slope may also be called a pulse edge. The amount of time that the unit remains or stays at such a step is called the dwell time t D For a fundamental AC frequency of 50 or 60 Hz at the AC terminals, i.e. for a period of 0.02 to 0.017 seconds, the dwell time t D can be in the range of tens to hundreds of nanoseconds. Therefore, the period can be 10 times the dwell time. 4 Up to 10 6 times.

[0086] The snubber capacitor Csn is thus inserted for adjusting the voltage of the pulse edge. The damping resistor Rd in this case damps the current through the snubber capacitor Csn. In the case of the inclusion of a snubber diode Dsn, it reduces the losses in the resistor Rd.

[0087] There are multiple ways in which the upper arm ua and the lower arm la can be operated when switching between the two levels +Vdc / 2 and -Vdc / 2. In a first scheme, the operation of the arms is interleaved, while in a second scheme, the units of one arm are operated first, and when this operation is completed, the units of the other arm are operated.

[0088] In the first scheme, cells in one arm are gradually bypassed while other cells are inserted in the other arm. By doing so, n cells are always connected in parallel to the string of link capacitors C1 and C2.

[0089] For the output current, i.e. the current leaving the converter from the AC terminal AC1, when the voltage changes from the first voltage level Vdc / 2 to the second voltage level -Vdc / 2 - this change is also called commutation from the upper arm to the lower arm, because the current commutates from the upper arm to the lower arm - the control is as follows:

[0090] The process starts when the control section 12 turns off one of the main switches MSW in one of the cells in the upper arm ua, such as the first cell Cua1, and simultaneously turns off the auxiliary switch ASW in one of the cells in the lower arm la, such as the first cell Cla1. The first main switch MSW turned off first in the upper arm ua switches with full-phase current, while the auxiliary switch ASW turned off first in the lower arm la is turned off with zero current.

[0091] This process is then followed for the remaining cells involved in the transformation.

[0092] Therefore, all cells in the upper arm ua are inserted continuously, while those in the lower arm la are bypassed or removed. Those cells in the upper arm ua have reduced current; those cells in the lower arm la have increased current.

[0093] Given that the phase current is positive and cells in the upper arm ua are being inserted, the snubber capacitor Csn of the first cell inserted will be the most charged snubber capacitor. Similarly, the capacitor Csn of the last cell to be bypassed or removed in the lower arm la is the most discharged capacitor as current flows out of the capacitor in the lower arm.

[0094] For the output current, when the voltage changes from the second voltage level -Vdc / 2 to the first voltage level +Vdc / 2 (this change is also called commutation from the lower arm to the upper arm because the current commutates from the lower arm to the upper arm), the control is as follows:

[0095] The process starts with setting the gate signals of a main switch MSW in the lower arm la, such as the main switch MSW in the first unit Cla1, and an auxiliary switch ASW in the upper arm ua, such as the auxiliary switch ASW in the first unit Cua1, to zero, and turning on the auxiliary switch ASW and the main switch MSW of the same unit respectively with an interlocking delay, that is, a delay that ensures that the main switch and the auxiliary switch of the unit are not turned on at the same time.

[0096] Gradually, all cells in the lower arm la are inserted, while those in the upper arm ua are bypassed. Those cells in the lower arm la have a reduced current; those in the upper arm ua have an increased current.

[0097] Assuming the phase current is positive and cells in the lower arm are being inserted, the capacitor of the first cell inserted is the capacitor that will discharge the most. Similarly, the capacitor of the last bypassed cell in the upper arm is the capacitor that charges the most.

[0098] For the input current, i.e. the current entering the converter 10 via the AC terminal AC1, when the voltage changes from the first voltage level +Vdc / 2 to the second voltage level Vdc / 2 and also commutates from the upper arm to the lower arm, the control is as follows:

[0099] The process starts by setting gate signals of the main switch MSW of a cell in an upper arm, such as the first cell Clu1, and the auxiliary switch ASW of a cell in a lower arm, such as the first cell Cla1, to zero, and respectively turning on the auxiliary switch ASW and the main switch MSW of the same cell with an interlocking delay.

[0100] Gradually, all cells in the upper arm ua are inserted, while those in the lower arm la are bypassed. Those cells in the upper arm ua have a reduced current; those in the lower arm have an increased current.

[0101] As the cells of the upper arm are inserted and given that the phase current is negative, the capacitor of the first cell to be inserted is the capacitor that will discharge the most. Similarly, the capacitor of the last cell to be bypassed in the lower arm la is the capacitor that charges the most.

[0102] For the input current, when the voltage changes from the second voltage level -Vdc / 2 to the first voltage level +Vdc / 2, and also commutates from the lower arm la to the upper arm ua, the control is as follows:

[0103] The process starts by turning off one of the main switches MSW in the lower arm la, such as the switch in the first cell Cla1, and simultaneously turning off the auxiliary switch ASW in the upper arm ua, such as the first cell Cua1.

[0104] The main switch MSW is turned off first in the lower arm la, switching with full-phase current, while the auxiliary switch ASW, which is turned off first in the upper arm ua, is turned off with zero current.

[0105] Continuously, all cells in the lower arm la are inserted, while those in the upper arm ua are bypassed. Those cells in the lower arm la have reduced current; those in the upper arm have increased current.

[0106] When inserting a cell in the lower arm la, and a given phase or output current is negative, the capacitor of the first cell inserted is the capacitor that will charge the most. Similarly, the capacitor of the last cell bypassed in the upper arm ua is the capacitor that discharges the most because current flows out of the capacitor in the upper arm.

[0107] In the above-described manner, the changeover between the two voltage levels for the two different current conduction directions according to the first scheme is controlled by the control section 12 .

[0108] A second aspect of the control unit will now be described.

[0109] For the output current from upper arm commutation to lower arm commutation, the operation is as follows:

[0110] (1) Before commutation:

[0111] The gate signal to the auxiliary switch ASW in the lower arm la is 0. Therefore, there is no commutation path available through the switch in the lower arm. Commutation will then involve only the upper arm ua.

[0112] (2) Commutation process:

[0113] Gradually, the main switch MSW in the upper arm ua is turned off, and the auxiliary switch ASW in the upper arm ua is turned on with an interlock delay.

[0114] Following a disconnection event at the master position, the current is forced to commutate through the diode in the upper arm ua.

[0115] In the upper arm: all main switches MSW are turned off at full current; all diodes of the auxiliary switches ASW are subjected to full-phase current; the auxiliary switches ASW are turned on at zero voltage (the auxiliary switch diodes are turned on).

[0116] After the RLC circuit resonant commutation, the current commutates when the accumulated total inserted upper arm unit voltage is higher than the DC link voltage (usually but not necessarily when the last main switch MSW in the upper arm ua is turned off).

[0117] (3) After commutation:

[0118] The main switch MSW in the lower arm 1a is turned on with zero voltage.

[0119] For output current with commutation from lower arm to upper arm, the operation is as follows:

[0120] (1) Before commutation:

[0121] The gate signal to the main switch MSW in the lower arm la is 0. There is no current path available through the auxiliary switches ASW in the lower arm la as they have been disconnected. Therefore, the current will commutate through the cells in the upper arm ua.

[0122] (2) Commutation process:

[0123] Gradually, the auxiliary switch ASW in the upper arm ua is turned off, and the main switch MSW in the upper arm ua is turned on with an interlock delay.

[0124] Once a main switch MSW in the upper arm is first turned on, current begins to commutate through the cells in the upper arm ua. In particular, current commutates through the diode in the upper arm.

[0125] In the upper arm: all main switches MSW (except the main switch turned on first) are turned on with full current; all diodes of the auxiliary switches are subjected to full-phase current; the auxiliary switch ASW is turned off with zero voltage (auxiliary switch diode is turned on).

[0126] When the first main switch in the upper arm is turned on, the current commutates at di / dt

[0127] di / dt=Vcell / Lloop, where Lloop is the inductance of the commutation loop formed by the cell inductance Lc and the DC link inductance Ldc / 2+Ldc / 2.

[0128] (3) After commutation:

[0129] The auxiliary switch ASW in the lower arm 1a is turned on with zero current.

[0130] For input current and commutation from upper arm to lower arm, the operation is as follows:

[0131] (1) Before commutation:

[0132] The gate signal to the main switch MSW in the upper arm ua is set to 0. There is no available path through the auxiliary switches ASW in the upper arm ua because they are already disconnected.

[0133] (2) Commutation process:

[0134] Gradually, the auxiliary switch ASW in the lower arm 1a is turned off, and the main switch MSW in the lower arm 1a is turned on with an interlock delay.

[0135] When a main switch MSW in the lower arm 1a is first turned on, current starts to commutate through the diode in the lower arm 1a.

[0136] In the lower arm: all main switches MSW (except the main switch turned on first) are turned on with full current; all diodes experience full-phase current; the auxiliary switch ASW is turned off with zero voltage (the diode of the auxiliary switch ASW is turned on).

[0137] Current commutates with di / dt

[0138] di / dt=Vcell / Llop

[0139] (3) After commutation:

[0140] The auxiliary switch ASW in the upper arm ua is turned on with zero current.

[0141] For input current and commutation from lower arm to upper arm, the operation is as follows:

[0142] (1) Before commutation:

[0143] The gate signal to the auxiliary position in the upper arm ua is set to zero. There is no commutation path for the current through the switch in the upper arm.

[0144] (2) Commutation process:

[0145] Gradually, the main switch MSW in the lower arm 1a is turned off and the auxiliary switch ASW in the lower arm 1a is turned on with an interlock delay. When the accumulated total inserted lower arm unit voltage is higher than the DC link voltage (usually but not necessarily when the last main switch MSW in the lower arm 1a is turned off), the current commutates through the diode in the lower arm 1a.

[0146] In the lower arm: all main switches MSW are turned off at full current; all diodes of the auxiliary switches ASW are subjected to full-phase current; the auxiliary switches ASW are turned on at zero voltage (the auxiliary switch diodes are turned on). When the lower arm is being inserted, it is connected in parallel with the DC link due to the turned-on auxiliary switch AUX. The current commutates following the resonant commutation of the RLC circuit.

[0147] (3) After commutation:

[0148] The main switch MSW in the upper arm ua is turned on with zero voltage (diode conduction).

[0149] Two approaches have been described above according to which a Q2L conversion technique is used to control a cell in order to convert between two voltage levels.

[0150] There is a problem with the use of the Q2L conversion technique in that resonance may occur on the DC link or phase arm current in at least some of the above-mentioned commutations according to the first and second schemes.

[0151] Furthermore, the energy of these resonances is typically dissipated as heat.

[0152] This results in converter losses and thus has a negative impact on the conversion efficiency. It is therefore of interest to limit such losses.

[0153] The inventors have found that losses are caused by the parallelization of the arm unit capacitors relative to the converter DC link capacitors. Such losses are comparable to the switching losses of the SiC switches and further increase with the converter dwell time. This will further limit the controller's freedom to choose the dwell time in operation.

[0154] When research Figure 3 The cause of the resonance will be better understood when the upper figure shows the DC link voltage Vdc and the sum of the voltages of the inserted cells of the upper arm in the form of the upper phase arm voltage Vua, while the lower figure shows the DC link current I DCL , which is the current running between the DC capacitor string and the converter arm to be commutated, for example the upper converter arm ua. Thus, Figure 3 Curves of voltage and current during operation of the upper arm according to the second kind of scheme are shown with output current and upper-arm to lower-arm commutation.

[0155] The root cause of the parallelization loss of the converter is due to the unbalanced voltage level between the converter DC link voltage Vdc and the sum of the cell voltages in a certain commutation process arm, exemplified as the upper arm voltage Vua. Therefore, in converter operation, this part of the unbalanced capacitive energy cannot be controlled and directed into the converter input or output, but is simply dissipated as losses in the loop resistance.

[0156] Moreover, the parallelization losses may increase with the dwell time of the Q2L-based converter and, in the case of 200ns, such losses may be comparable to the switching losses of the converter using SiC switches and account for 25% of the total losses.

[0157] In order to solve this problem of losses caused by resonance, it is usually recommended to treat one of the cell capacitors used in the commutation in a special way to provide a compensation voltage at the point in time when the loop current crosses zero. Thus, by "entering" the voltage step at the right time, the DC link capacitance, link inductance Ldc / 2 and cell capacitance Csn and inductance L C The formed CLC loop will suddenly reach a state of equilibrium and the resonance will be "cut off". The last inserted capacitor can be considered as a "resonance cutting capacitor / unit".

[0158] It can be appreciated that such problems and solutions are very fundamental and critical to any Q2L based converter for the following reasons:

[0159] 1. This problem is theoretically equivalent to the circulating current of the MMC converter, which is a well-known phenomenon in MMC control and application.

[0160] 2. The reason why MMC does not suffer from such parallelization losses is mainly because for MMC, it consists of very large arm inductors (in the range of mH) and unit capacitors (in the range of mF), which enables phase-locked loop resonance at very low frequencies. The modulation frequency of MMC is fast enough to control and adjust such loop currents and thus avoid excessive energy losses.

[0161] 3. However, for Q2L-based converters, due to the very high resonant frequencies (L: in the range of pH; C: in the range of pF), modulation within the resonant period is not possible even for SiC devices. Therefore, new methods are needed to control the current flow, otherwise the energy can only be dissipated as converter losses.

[0162] Now we will also refer to Figure 4 and Figure 5 Describe in more detail how to solve this problem. Figure 4 A flowchart showing a plurality of method steps in a method for limiting resonance performed by the control unit 12, Figure 5 Shown with Figure 3 Same voltage and current. Therefore, Figure 5 The upper figure shows the DC link voltage Vdc and the upper phase arm voltage Vua when the second scheme is used for upper arm to lower arm commutation with output current, and the lower figure shows the DC link current I when the second scheme is used for upper arm to lower arm commutation with output current.DCL .

[0163] The control section 12 controls a group of cells used in a conversion between two levels with a certain slope for commutating a current traveling through a corresponding one of the arms involved in the conversion, wherein the group includes cells of the arm from which the current is commutated.

[0164] In the exemplary generation of the pulse train, the second scheme is used and there is an output current. Moreover, a transformation is performed from a first voltage level +Vdc / 2 to a second voltage level -Vdc / 2. Thus, the cell group only includes cells in the upper arm ua, and the current to be commutated is the current traveling through the upper arm. The transformation also has a negative slope. At the beginning of the transformation, the sum of the voltages of the uninserted cells allocated for use is generally the same as the DC link voltage Vdc.

[0165] Therefore, the allocated cells to be inserted usually have voltages whose sum corresponds to the desired voltage level for the transformation. However, when the cells are actually inserted, they may be charged or discharged, depending on the current conduction direction. This means that there may be a voltage difference between the DC link voltage Vdc and the sum of the cell voltages Vua for the transformation. For example, if the cells are being charged, they will reach a voltage level such that the sum of the cell voltages connected in parallel with the branches of the capacitors is different from the DC link voltage, and resonance may therefore occur, such as Figure 3 The current I shown in DCL And the branch voltage Vua.

[0166] For an arm through which current travels into the AC terminal, such as the upper arm ua, the control section 12 has the following operation.

[0167] The control section 12 controls a cell group, which includes cells in at least one of the arms, to change between two levels, in this example, the control is performed using the second scheme previously described. In the example, the group consists of all the cells of the upper arm ua. Therefore, the control involves inserting the cells into the upper arm and, when the insertion of all the cells is completed, then bypassing the cells in the lower arm.

[0168] In order to limit the resonance, the control section 12 obtains the value of the current running between the DC link capacitors C1 and C2 and the converter arm to be commutated, which in this case is the DC link current I DCL , step 14. This current can be obtained, for example, by a current transformer connected to the DC link.

[0169] Optionally, the control part 12 also obtains the value of the voltage across the branch of the DC link capacitors to be connected in parallel with the cell group for conversion, step 16. Thus, the capacitors of the cell group will be connected in parallel with the branch of capacitors during commutation. The branch includes at least one of the capacitors in the string, and in this example, the branch of capacitors is identical to the DC link capacitor string, i.e., the branch includes all DC link capacitors. Thus, it includes both the first DC link capacitor C1 and the second DC link capacitor C2. The voltage of the DC link capacitor can be obtained by measuring the DC link voltage Vdc, for example using a voltage transformer.

[0170] The control section 12 can also optionally obtain the voltage of the buffer capacitors Csn of the cell group, since they are used for current commutation in the transformation, step 18. Since the second scheme for transformation between two of the levels with a negative slope is used in this example, the cell is the one being inserted in the upper arm ua.

[0171] Furthermore, during the control, the control unit 12 may monitor the DC link current I DCL .

[0172] When the voltage of the branch of the capacitor and the cell voltage are obtained, the control part 12 can also determine the difference between the voltage Vdc of the branch of the DC link capacitor and the sum Vua of the voltages provided by the cell group (step 20), which can be the sum of the inserted cell voltages of the cell group.

[0173] During the conversion, the control unit 12 then selects the cells to be processed to reach the second voltage level -DC / 2, which selection may include using a specific dwell time at each step. This selection may also include selecting the cell to be processed last to reach the voltage level. All cells except the cell to be processed last can then be inserted or bypassed using the dwell time to reach the desired slope.

[0174] According to aspects of the present invention, the control unit group converts between two levels including processing the cells in the group selected for last use to reach one of the levels, the processing including inserting or bypassing the cell when the DC link current is at a zero level. This can be when the current is close to zero, has reached zero, or is crossing zero. In the illustrated second scheme, this includes the control unit controlling the last cell of the upper arm ua to be inserted at a zero current level (step 22), which can be at a current zero crossing point. As an example, the cell for which this is done can be the fourth cell cua4.

[0175] When determining the difference between the voltage of the branch of the DC link capacitor and the sum of the inserted cell voltages of the cell group, the processing of the last cell, i.e. the insertion or removal of the last cell, can additionally be performed when the voltage difference is negative. In this example, the last cell in the upper arm is inserted when the voltage difference is negative.

[0176] Therefore, the control portion 12 may insert the last unit when two conditions are met, ie when the DC link current is at zero level, such as when it has a current zero crossing and the difference is negative.

[0177] This operation Figure 5 Clearly visible.

[0178] Due to the direction of the DC link current, the inserted cells are being charged, resulting in the desired voltage level being reached before the last cell is inserted. By delaying the insertion of the last cell in the upper arm until the current zero level is reached and optionally also until the above mentioned difference is negative, it can be seen that the resonance is significantly limited and therefore the losses are also reduced.

[0179] It can be seen from this that the resonances and therefore also the losses are limited.

[0180] It should be appreciated here that where there is a transition from the second voltage level to the first voltage level, i.e. a positive slope, and an input current using the second scheme, which current passes through the lower arm la, then the same type of operation will be performed on the cell being inserted into the lower arm.

[0181] In the case of using the first solution in the above mentioned conversion from the first voltage level to the second voltage level, the cell group then comprises cells in both the upper arm and the lower arm. Moreover, in this case, the last cell used in the group may be a cell that is bypassed in the lower arm. Therefore, in this case, it is possible to delay the bypassing of the last cell of the second arm in the sequence to the current zero crossing instead, possibly in combination with a negative voltage difference between the DC link voltage and the sum of the insertion capacitors of the upper and lower arms.

[0182] In the case where the first scheme is used in the above mentioned transition from the second voltage level to the first voltage level, and there is an input current, then in a similar manner it is possible that the last cell used in the group may be the bypassed cell in the upper arm.

[0183] The method can also be changed here by adopting cell voltage balancing. Between transformations, the control unit 12 can sort the cells according to the cell voltage balancing scheme so that the last cell to be inserted or bypassed can be the last cell of the cell sequence obtained by sorting. The cells can be sorted according to voltage. Then these cells can be inserted and bypassed in increasing order or decreasing order according to the sorting order or according to the current direction. Therefore, the cell sequence can be a sequence of increasing cell voltage or a sequence of reducing cell voltage. In this way, it can then be avoided to reuse cells for resonant processing in two consecutive transformations of the same type, for example for two consecutive negative slope transformations.

[0184] There are several advantages associated with the previously described method of limiting resonance.

[0185] ■It reduces the loss caused by resonance by using Quasi Two-Level (Q2L) conversion technology. This also improves efficiency.

[0186] ■ The resonance cutting unit does not require any special design, and in actual operation, it can be selected as any unit by the control unit. Therefore, no additional hardware or special unit design is required. It is possible to implement the present invention only by additional software, which also makes it economical.

[0187] ■ If a "resonance excision cell" needs to have a well-regulated cell voltage to perfectly excise the resonance, this can be achieved by controlling the cell insertion sorting algorithm and the dwell time.

[0188] ■ Ideally, parallelization can be eliminated by the proposed method.

[0189] ■ The current stress on the components is also limited, which allows the component size to be reduced. It also improves the tolerance of the cell capacitor voltage ripple and allows the capacitance to be reduced.

[0190] ■ It also releases freedom in the dwell time selection of the converter control based on Q2L technology, which is crucial for harmonic and EMI issues.

[0191] In About Figure 5 In the described operation, during the commutation process, ie during the transition between two voltage levels, the cells to be processed are selected.

[0192] As an alternative it is possible to preselect the cells before the commutation sequence starts. Thus, the cells can be preselected before the commutation sequence starts, i.e. before the commutation is actually turned on. Additionally, it is possible that the complete initiation sequence can be predicted and calculated by the control before the commutation of each arm is completed. This is particularly the case when cell balancing is performed.

[0193] Now refer to Figure 6 Describe how to achieve this, Figure 6 A flow chart showing an alternative way of limiting resonance performed by the control unit 12 is shown.

[0194] In order to limit resonance, the control unit 12 obtains the value of the output current, ie the current leaving the AC terminals, step 24. The control unit 12 also obtains the DC link current I DCL The control section 12 also obtains the value of the voltage across the branch of the DC link capacitor to be connected in parallel with the group of cells for conversion (step 28), here the voltage across both the first DC link capacitor C1 and the second DC link capacitor C2. The control section 12 likewise obtains the voltage of the buffer capacitor Csn of the cells of the group, step 30. All these values ​​are obtained before conversion is carried out, i.e. before commutation is turned on. The order of the steps can also be freely changed.

[0195] Since the second scheme for transition between two of the levels with a negative slope is used, the cell is the cell being inserted in the upper arm ua, and the DC link current is the current between the DC link capacitor and the upper arm ua.

[0196] The control section 12 then sorts the cells according to the cell voltage balancing scheme so that they can be inserted or bypassed in the cell sequence, step 32. As mentioned previously, sorting may include sorting the cells according to cell voltage.

[0197] Then, the control unit 12 determines the unit sequence, predicts the timing of the steps in the conversion, the DC link current I DCL The point in time when zero is reached and when the difference between the voltage Vdc of the branch of the DC link capacitor and the sum of the voltages Vua provided by the group of cells is negative, step 34 .

[0198] The determination of the cell sequence may be based on the direction of the output current and the type of slope that the transformation to be performed will form). The cell sequence may then start with the cell with the lowest voltage and then proceed sequentially to the cell with the highest voltage. Alternatively, the sequence may start with the cell with the highest voltage and then proceed sequentially to the cell with the lowest voltage. It should be appreciated that more complex cell ordering schemes that do not rely solely on cell voltage may be used. It is also possible that the dwell time varies. For these steps, they are not limited to being equal.

[0199] In the given example, the current is the output current and the transition is from high to low. In this case, the cell sequence may start with the cell with the lowest voltage in the upper arm and then proceed sequentially to the cell with the highest voltage in the upper arm. Thus, the cell with the highest voltage may be selected as the last cell to be processed, which in this case is the last cell to be inserted.

[0200] The prediction of the zero current level and the voltage difference can be made based on a model of the converter.

[0201] The DC link current can be predicted based on the obtained DC link current, the determined cell sequence and the dwell time. In a similar manner, the voltage difference can be predicted based on the DC link voltage, the predicted sum of the cell capacitor voltages during the transformation, the determined cell sequence and the dwell time. The prediction of the changes in the sum of the DC voltages and the DC link current includes predicting the changes in these due to the charging or discharging of the cell capacitors. The prediction in this case also includes predicting and applying the resonance effects.

[0202] Based on the above mentioned predictions, the control part 12 then predicts when the DC link current will reach zero, such as when it will have a zero crossing, and possibly also when the voltage difference will be negative. The timing of the last unit to be processed is then set to when the DC link current is at zero level and the voltage difference is negative.

[0203] Then, the initiation scheme, i.e. the data about which cells are to be inserted and when, can be stored in a timing table and when it is time to perform the transformation, the control section 12 inserts the cells according to the settings in the initiation table, which therefore includes processing the last cell in the sequence of cells at a predicted zero current level when the voltage difference is predicted to be negative, step 36.

[0204] Therefore, the steps performed by all cells except the last cell in the sequence are determined based on the dwell time. However, when a negative voltage difference is also predicted, the insertion timing of the last cell is determined based on the predicted current zero crossing.

[0205] You can also Figure 1 The converter in the present invention has several variations, one of which is Figure 7 Shown in.

[0206] Figure 7 The converter 10 in FIG. 1 is shown to include three arms, which are also all associated with a single AC phase. It should also be appreciated that there may be three different phases, and therefore a total of nine different arms, with three arms per phase.

[0207] As can be seen in the figure, there is a first upper converter arm ua connected between the first DC terminal DC1 and the junction j, and a second lower converter arm la connected between the junction j and the second DC terminal DC2, as shown in FIG. Figure 1 Moreover, this converter comprises a series of capacitors C1 and C2 connected between the first DC terminal DC1 and the second DC terminal DC2 and the first AC terminal AC1 at the junction j. In this case, the midpoint of the series of capacitors C1 and C2 is the neutral point np or the ground point. Figure 1 In contrast to the converter in , there is a third neutral converter arm na connected between junction j and the neutral point.

[0208] In the case of three phases, there will be three arm groups, where each group includes an upper arm, a lower arm, and a neutral arm connected to the corresponding AC terminal, where the upper arms of all groups are connected to the first DC terminal, all lower arms are connected to the second DC terminal, and all neutral arms are connected to the capacitor string midpoint. Therefore, the capacitor string midpoint will be common to all neutral arms.

[0209] At least one of the arms comprises a cell, and any arm lacking a cell comprises only a switch for connecting the junction to the corresponding voltage level. In the exemplary converter 10, the upper arm ua and the lower arm la comprise cells, which are advantageously connected in series or cascade in the arms, and thus the neutral arm comprises a switch.

[0210] The neutral arm na, which only includes switches, i.e., it has no cells, includes a first switch S1 and a second switch S2 with opposite orientations, wherein each switch is implemented as a combination of transistors, such as an IGBT with an anti-parallel diode on a suitable substrate such as S or Si. Therefore, the switch is a Si switch or a SiC switch. By providing two switches of opposite orientation, the junction j can be connected and disconnected from the neutral point np regardless of the direction of the current through the neutral arm. The SiC switch is an example of a type of wide bandgap device. It should be appreciated that other types of wide bandgap devices, such as gallium nitride (GaN) switches, may also be used.

[0211] This converter is controlled to provide two pulse trains between +Vdc / 2 and zero and between zero and -Vdc / 2 at the AC terminal AC1 of the converter. Here the cells in the upper arm are made to provide transitions between +Vdc / 2 and 0, while the lower arm is made to provide transitions between 0 and -Vdc / 2.

[0212] Therefore, in the positive half cycle, the additional switches S1 and S2 are turned on whenever all the upper arm cells are plugged in, so that the output voltage is clamped to zero. Similarly, in the negative half cycle, the switches S1 and S2 are turned on whenever all the cells of the lower arm 1a are plugged in during the negative half cycle, so that the output voltage is again clamped to zero.

[0213] Therefore, the zero level is obtained by connecting the junction j to the neutral point np. It follows that the cells in the upper arm will be connected in parallel with the first capacitor C1, and the cells in the lower arm will be connected in parallel with the second capacitor C2. This means that for Figure 6 In the converter of , the branch of capacitors for the transformations associated with the generation of one pulse train comprises half of the capacitor chain, in this case it is only the first capacitor C1, and the group of cells connected in parallel with this branch comprises only the cells in the upper arm ua. The branch of capacitors for the transformations associated with the generation of another pulse train comprises the other half of the chain, for example only the second capacitor C2, and the group of cells connected in parallel with this branch comprises only the cells in the lower arm la. In this case, the difference between the first capacitor C1 and the sum of the cell voltages of the upper arm ua when transforming between +Vdc / 2 and zero is used to handle the resonance, while the difference between the second capacitor C2 and the sum of the cell voltages of the lower arm la is used to handle the resonance when transforming between zero and -Vdc / 2.

[0214] Figure 7 A variation of the converter is that the neutral arm may instead comprise cells, while the upper and lower arms comprise switches, in which case the cell group comprises only cells of the neutral arm connected in parallel with the first DC link capacitor or the second DC link capacitor.

[0215] Another possible variant is to use a bipolar cell, ie a cell with bipolar voltage contribution capability and, as an example, with a full-bridge structure. One implementation of such a cell is Figure 82B . The cell Cna1 comprises a first main switch MSW1. The first end of this first main switch MSW1 is connected to the first end of the buffer capacitor Csn through the series connection of the first auxiliary switch ASW1 and the first optional damping resistor Rd1. There is also a second main switch MSW2, which has a first end connected to the same first end of the buffer capacitor Csn through the series connection of the second auxiliary switch ASW2 and the optional second damping resistor Rd2. In this case, there is also an optional first buffer diode Dsn1 connected between a first connection point and a second connection point, wherein the first connection point is the connection point between the two switches ASW1 and MSW1, and the second connection point is the connection point between the first damping resistor Rd1, the second damping resistor Rd2 and the buffer capacitor Csn. There is also an optional second buffer diode Dsn2 connected between a third connection point and a second connection point, wherein the third connection point is the connection point between the two switches ASW2 and MSW2. Both diodes Dsn1 and Dsn2 conduct current towards the buffer capacitor Csn. Finally, the second ends of the first main switch MSW1 and the second main switch MSW2 are also connected to the second end of the buffer capacitor Csn. The first connection terminal of the unit Cna1 is arranged at the first connection point, and the second connection terminal of the unit is arranged at the third connection point. The unit Cna1 can be switched to provide a voltage contribution corresponding to a positive voltage of the buffer capacitor Csn, a negative voltage corresponding to the buffer capacitor Csn, or a zero voltage. When providing a voltage corresponding to the voltage of the buffer capacitor Csn, the unit inserts the voltage of the buffer capacitor Csn. When the unit Cna1 does not provide a voltage or provides a zero voltage, the buffer capacitor Csn is bypassed. In this case, the buffer diode can also be connected in parallel only with the corresponding damping resistor. It is also possible to remove both the damping resistor and the buffer diode.

[0216] When such cells are used, they can be used to insert negative voltages, and thus they can be used for all of the above-mentioned transformations, regardless of which arm they are placed in. For example, it is thus possible to use a negative voltage when transforming from a first voltage level to a second voltage level. Figure 1 The unit is inserted into the lower arm of the converter in the figure, and this unit can also be the last unit to be inserted.

[0217] As mentioned previously, the control portion may be provided in the form of a processor with associated program memory containing computer program code for performing its functions, or in the form of a digital signal processor (DSP), application specific integrated circuit (ASIC) or field programmable gate array (FPGA).

[0218] The computer program may also be a computer program product, for example in the form of a computer-readable storage medium or a data carrier carrying a computer program with computer program code, which, when loaded into a processor, will implement the functions of the control unit described above. Fig. 9 One such computer program product in the form of a CD ROM disc 38 having the above-mentioned computer program code 40 is schematically shown in FIG.

[0219] It should be appreciated that it is possible that the neutral arm also comprises a unipolar cell, such as a half-bridge cell.

[0220] It will be appreciated that further variations are possible in addition to those already described. The switches are not limited to employing IGBTs and MOSFETs. For example, the switches may instead be based on junction field effect transistors (JFETs). Integrated gate commutated thyristors (IGCTs) may also be used.

[0221] From the foregoing discussion it is obvious that the present invention can be varied in many ways. Therefore, it should be realized that the present invention is limited only by the following claims.

Claims

1. A voltage source converter (10) for limiting resonance, the voltage source converter being configured to generate a pulse train using two voltage levels (+Vdc / 2, -Vdc / 2; +Vdc / 2, 0), the converter comprising: a first converter arm (ua) connected between a junction (j) and a first DC terminal (DC1) having a first voltage level (Vdc / 2); a second converter arm (la) connected between the junction (j) and a second DC terminal (DC2) having a second voltage level (-Vdc / 2); and a capacitor string (C1, C2) connected between the first DC terminal and the second DC terminal, wherein at least one of the converter arms (ua, la) comprises a cell (Cua1, Cua2, Cua3, Cua4, Cla1, Cla2, Cla3, Cla4); The voltage source converter (10) further comprises a control section (12) which controls a group of cells (Cua1, Cua2, Cua3, Cua4) used in the transformation between the two voltage levels for commutating a current passing through a corresponding one of the converter arms (ua) involved in the transformation, the group comprising the cells of the converter arms, The control unit (12) is configured to obtain a current (I) running between the capacitor string and the converter arm (ua) when controlling the cell group. DCL ) and processing the cell (Cua4) selected as the last one to be used in the group to reach one of the voltage levels, the processing comprising inserting or bypassing the cell when the current between the capacitor string and the converter arm is close to zero, has reached zero or is crossing zero.

2. A voltage source converter (10) according to claim 1, wherein the capacitors of the cell group are connected in parallel with a branch of capacitors during the commutation, the branch comprising at least one of the capacitors (C1, C2; C1) in the string, and the control unit (12) is also configured to determine the difference between the voltage of the branch of capacitors (+Vdc; +Vdc / 2) and the sum of the voltages provided by the cell group (Vua), wherein the cell is processed when the voltage difference is negative.

3. The voltage source converter (10) according to claim 1 or 2, wherein: While the conversion is in progress, the cell last used in a particular conversion between the two voltage levels is selected by the control section.

4. The voltage source converter (10) according to claim 2, wherein: The control section (12) is also configured to sort the cells according to a cell voltage balancing scheme so that the cell to be inserted or bypassed is the last cell of the cell sequence obtained by the sorting.

5. The voltage source converter according to claim 4, wherein: The cell last used in a particular transition between two of the voltage levels is selected by the control section before the transition has been initiated.

6. The voltage source converter according to claim 5, wherein: The current between the capacitor string and the cell group is obtained before the conversion has been turned on, and the control section can also be configured to predict the current (I) running between the DC capacitor string and the converter arm (ua) based on the measurements performed and the cell sequence according to the cell voltage balancing scheme. DCL ) will reach zero, and the selected cell is processed at the predicted zero level.

7. The voltage source converter (10) according to claim 1 or 2, wherein: The first and second converter arms (ua, la) comprise cells, and a last processed cell comprises a last cell (Cua4) inserted in the first converter arm (ua).

8. The voltage source converter (10) according to claim 1 or 2, wherein: The first converter arm and the second converter arm (ua, la) comprise cells, and the last processed cell comprises the last bypassed cell in the second converter arm (la).

9. The voltage source converter (10) according to claim 2, wherein: Said branch of capacitors comprises a complete chain of capacitors (C1, C2).

10. The voltage source converter (10) according to claim 1 or 2, wherein: Each cell comprises a first main switch (MSW; MSW1), a first auxiliary switch (ASW; ASW1) and a snubber capacitor (Csn), wherein the first main switch (MSW; MSW1) is configured to switch between the two voltage levels, and the first auxiliary switch (ASW; ASW1) is configured to connect the buffer capacitor (Csn) to introduce a positive slope or a negative slope in the transition between the two voltage levels.

11. The voltage source converter (10) according to claim 10, wherein: The unit comprises a first damping resistor (Rd; Rd1) between the first auxiliary switch (ASW; ASW1) and the snubber capacitor (Csn).

12. A method of limiting resonance in a voltage source converter (10) using two voltage levels (+Vdc / 2, -Vdc / 2; +Vdc / 2, 0) to generate a pulse train, the converter comprising: a first converter arm (ua) connected between a junction (j) and a first DC terminal (DC1) having a first voltage level (Vdc / 2); a second converter arm (la) connected between the junction and a second DC terminal (DC2) having a second voltage level (-Vdc / 2); and a capacitor string (C1, C2) connected between the first DC terminal and the second DC terminal (DC1, DC2), wherein at least one of the converter arms (ua, la) comprises cells (Cua1, Cua2, Cua3, Cua4, Cla1, Cla2, Cla3, Cla4), the method comprising controlling a group of cells (Cua1, Cua2, Cua3, Cua4) used in a transformation between the two voltage levels for commutating a current passing through a corresponding one of the converter arms (ua) involved in the transformation, the group comprising the cells of the converter arms, Wherein, controlling the unit group comprises: obtaining (14; 26) a value of a current (IDCL) running between said capacitor string and said converter arm (ua), and Processing (22; 36) a cell (Cua4) in the group selected as last used to reach one of the voltage levels, the processing comprising inserting or bypassing the cell when the current between the capacitor string and the converter arm is close to zero, has reached zero or is crossing zero.

13. The method according to claim 12, wherein: The capacitors of the cell group are connected in parallel with a branch of capacitors (C1, C2; C1) during the commutation, the branch comprising at least one of the capacitors (C1, C2; C2) in the string, and the method further comprises determining (20) the difference between the voltage of the branch of capacitors (+Vdc, +Vdc / 2) and the sum (Vua) of the voltages provided by the cell group, wherein the last cell is processed when the voltage difference is negative.

14. The method according to claim 12 or 13, further comprising sorting (32) the cells according to a cell voltage balancing scheme such that the last cell to be inserted or bypassed is the last cell of the sequence of cells obtained by the sorting.

15. A computer program product for limiting resonance in a voltage source converter (10) generating a pulse train using two voltage levels (+Vdc / 2, -Vdc / 2; +Vdc / 2, 0), the converter comprising: a first converter arm (ua) connected between a junction (j) and a first DC terminal (DC1) having a first voltage level (Vdc / 2); a second converter arm (la) connected between the junction and a second DC terminal (DC2) having a second voltage level (-Vdc / 2); and a capacitor string (C1, C2) connected between the first DC terminal and the second DC terminal (DC1, DC2), wherein at least one of the converter arms (ua, la) comprises cells (Cua1, Cua2, Cua3, Cua4, Cla1, Cla2, Cla3, Cla4), the converter comprising a control section (12) controlling a group of cells (Cua1, Cua2, Cua3, Cua4) used in the transformation between the two voltage levels for commutating a current passing through a corresponding one of the arms (ua) involved in the transformation, the group comprising the cells of the converter arms, The computer program product comprises a data carrier (38) carrying computer program code (40) which causes the control unit (12) to control the group of units to: Obtain the current (I) traveling between the capacitor string and the converter arm (ua) DCL ), and A cell (Cua4) selected as last used in the group is processed to reach one of the voltage levels, the processing comprising inserting or bypassing the cell when the current between the capacitor string and the converter arm is close to zero, has reached zero or is crossing zero.

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