A high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit

Abstract

The present invention belongs to the field of circuit technology, and relates to a high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit, including an external input terminal, the external input terminal is electrically connected to one end of a first capacitor, and the other end of the first capacitor is grounded; an external output terminal, the external output terminal is electrically connected to one end of a second capacitor, and the other end of the second capacitor is grounded; a clamping circuit is connected in series between the external input terminal and the external output terminal. The present invention greatly improves the linear overvoltage surge suppression power and overvoltage level by clamping MOSFET tubes for multi-tube series current equalization and multi-tube parallel voltage equalization circuits, and expands the scope of use of surge suppression. At the same time, multi-stage series-parallel power MOSFET tubes can be used according to actual needs to achieve higher voltage levels and greater power levels. It is highly practical and worthy of promotion.

Description

Technical Field

[0001] The invention belongs to the technical field of circuits, and in particular relates to a high-power multi-channel series-parallel voltage-equalizing voltage surge suppression circuit. Background Art

[0002] With the improvement of various semiconductor performances, the requirements for system power supply are getting higher and higher. Stable power front-end voltage is the mainstream direction of existing system power supply. Linear overvoltage surge suppression circuit has become the first choice for front-end preprocessing modules due to its good electromagnetic compatibility.

[0003] As the power of power supply is getting higher and higher, the traditional linear overvoltage surge suppression circuit, the clamping power MOSFET tube is mainly a single MOSFET tube. Due to process limitations, the overcurrent capability of a single clamping power MOSFET tube is limited, resulting in limited output power, which seriously restricts the scope of use of linear overvoltage surge suppression circuits. Summary of the invention

[0004] In view of this, the present invention provides a high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit to solve the above-mentioned technical problems.

[0005] The technical solution of the present invention is:

[0006] A high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit, comprising:

[0007] an external input terminal, the external input terminal being electrically connected to one end of a first capacitor CA, the other end of the first capacitor CA being grounded;

[0008] an external output terminal, the external output terminal being electrically connected to one end of a second capacitor CB, the other end of the second capacitor CB being grounded;

[0009] A clamping circuit is connected in series between the external input terminal and the external output terminal, wherein the clamping circuit comprises at least two stages of clamping modules connected in series in sequence, wherein the clamping module comprises at least two clamping units connected in parallel, and wherein the clamping unit comprises:

[0010] A MOSFET tube, wherein the source of the MOSFET tube is electrically connected to the external input terminal, the drain of the MOSFET tube is electrically connected to the post-stage clamping module, the gate of the MOSFET tube is electrically connected to one end of a third capacitor C2, the other end of the third capacitor C2 is grounded, the end of the third capacitor C2 away from the ground end is electrically connected to one end of a first resistor R2, and the other end of the first resistor R2 is electrically connected to the drain of the MOSFET tube;

[0011] Also includes:

[0012] A power supply circuit, used to ensure normal power supply of the subsequent circuit, the input end of the power supply circuit being connected to the external input end;

[0013] An oscillating circuit, used for providing a square wave of a set frequency to a subsequent circuit, wherein an input end of the oscillating circuit is connected to an output end of the power supply circuit;

[0014] A bootstrap circuit, used for providing a gate driving voltage for the clamping unit, wherein the output end of the oscillation circuit is connected to the input end of the bootstrap circuit;

[0015] A voltage balancing circuit, used for balancing the clamping voltage of the MOSFET tube of the clamping unit;

[0016] The output voltage regulating circuit is used to set the output voltage, the input end of the output voltage regulating circuit is electrically connected to the external input end, and the output end of the output voltage regulating circuit is electrically connected to the external output end.

[0017] Preferably, the power supply circuit includes a second resistor R1, a first transistor VT1, a first diode D1, a first voltage regulator DZ1 and a fourth capacitor C1, one end of the second resistor R1 is electrically connected to the external input terminal, the other end of the second resistor R1 is electrically connected to the anode of the first diode D1, the cathode of the first diode D1 is electrically connected to the cathode of the first voltage regulator DZ1, and the anode of the first voltage regulator DZ1 is grounded; the anode of the first diode D1 is electrically connected to the base of the first transistor VT1, the emitter of the first transistor VT1 is electrically connected to one end of the fourth capacitor C1, the other end of the fourth capacitor C1 is grounded, and the collector of the first transistor VT1 is electrically connected to the external input terminal.

[0018] Preferably, the oscillation circuit comprises:

[0019] A triangular wave generating circuit and a square wave output circuit for converting the triangular wave generating circuit into a square wave, wherein the triangular wave generating circuit comprises a pulse width modulator IC1, wherein the pulse width modulator IC1 is UCC2813-5, wherein the FB port, the CS port, and the GND port of the UCC2813-5 are all grounded, the COMP port is electrically connected to one end of a fifth capacitor C11, wherein the other end of the fifth capacitor C11 is grounded, the R / C port is electrically connected to one end of a sixth capacitor C10, wherein the other end of the sixth capacitor C10 is grounded, and V cc Port is electrically connected to the power supply, V ref The port is electrically connected to an end of the fifth capacitor C11 away from the ground, and an end of the sixth capacitor C10 away from the ground is electrically connected to one end of the third resistor R10;

[0020] The square wave output circuit includes a comparator IC2, wherein the non-inverting input terminal of the comparator IC2 is electrically connected to the end of the sixth capacitor C10 away from the ground, the inverting input terminal of the comparator IC2 is electrically connected to one end of the fourth resistor R11 and the fifth resistor R12 respectively, the other end of the fourth resistor R11 is electrically connected to the other end of the third resistor R10, the other end of the fifth resistor R12 is grounded, the positive power supply port of the comparator IC2 is electrically connected to the power supply and one end of the seventh capacitor C12 respectively, and the other end of the seventh capacitor C12 is connected to the The negative power supply port of the comparator IC2 is grounded, the output end of the comparator IC2 is electrically connected to one end of the sixth resistor R13 and the seventh resistor R14 respectively, the other end of the sixth resistor R13 is electrically connected to the power supply, the other end of the seventh resistor R14 is electrically connected to the base of the second triode VT2 and the third triode VT3 respectively, the emitter of the second triode VT2 is electrically connected to the emitter of the third triode VT3, the collector of the second triode VT2 is grounded, and the collector of the third triode VT3 is electrically connected to the power supply.

[0021] Preferably, the bootstrap circuit includes at least two bootstrap units, and the bootstrap unit includes a seventh capacitor C13 having one end electrically connected to the emitter of the third triode VT3, and the other end of the seventh capacitor C13 is respectively electrically connected to the anode of the second diode D2 and the cathode of the third diode D3, the anode of the third diode D3 is electrically connected to one end of the eighth capacitor C14, and the other end of the eighth capacitor C14 is electrically connected to the cathode of the second diode D2, and the cathode of the second diode D2 is also electrically connected to one end of the eighth resistor R15, and the other end of the eighth resistor R15 is electrically connected to the cathode of the second voltage regulator tube DZ2, and the anode of the second voltage regulator tube DZ2 is electrically connected to the anode of the third diode D3; the cathode of the second voltage regulator tube DZ2 is electrically connected to the gate of the MOSFET tube, and the anode of the second voltage regulator tube DZ2 is electrically connected to the drain of the MOSFET tube.

[0022] Preferably, the voltage equalizing circuit includes at least two voltage equalizing units connected in series in sequence, and the voltage equalizing unit includes a ninth resistor R24 ​​having one end electrically connected to the external input end, the other end of the ninth resistor R24 ​​is electrically connected to one end of the tenth resistor R17, the other end of the tenth resistor R17 is electrically connected to the gate of the MOSFET tube, the external input end is electrically connected to the cathode of the fifth voltage-regulating tube DZ5, and the anode of the fifth voltage-regulating tube DZ5 is electrically connected to the end of the ninth resistor R24 ​​facing away from the external input end.

[0023] Preferably, a fourth diode D7 is further included, wherein an anode of the fourth diode D7 is electrically connected to the external input terminal, and a cathode of the fourth diode D7 is electrically connected to a cathode of the fifth voltage regulator tube DZ5.

[0024] Preferably, the output voltage regulating circuit includes an eleventh resistor R19, a twelfth resistor R20 and a thirteenth resistor R21 connected in series in sequence, the eleventh resistor R19 is electrically connected to the external output terminal, the thirteenth resistor R21 is grounded, the end of the thirteenth resistor R21 away from the ground end is electrically connected to the base of the fourth transistor VT4, the collector of the fourth transistor VT4 is electrically connected to the external output terminal, the emitter of the fourth transistor VT4 is electrically connected to the emitter of the fifth transistor VT5, the collector of the fifth transistor VT5 is electrically connected to the power supply, and the base of the fifth transistor VT5 is electrically connected to the V of UCC2813-5 ref Port, the emitter of the fifth transistor VT5 is electrically connected to one end of the fourteenth resistor R18, and the other end of the fourteenth resistor R18 is grounded.

[0025] The present invention provides a high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit. Under normal power supply conditions, the MOSFET tube in the clamping circuit is fully turned on, and the circuit is in a micro-power consumption working state. When the input voltage is higher than the limiting voltage or an overvoltage surge occurs, the clamping circuit limits the output voltage to within a set voltage range. At this time, the module is in a linear voltage regulation working mode to ensure that the subsequent circuit is not affected by voltage transients.

[0026] Compared with the prior art, the present invention greatly improves the linear overvoltage surge suppression power and overvoltage level by clamping multiple MOSFET tubes in series for current equalization and multiple tubes in parallel for voltage equalization, and expands the scope of use of surge suppression. At the same time, multiple stages of power MOSFET tubes can be connected in series and parallel according to actual needs to achieve the use of higher voltage levels and greater power levels. The invention has strong practicality and is worthy of promotion. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is the overall circuit diagram of the present invention;

[0028] Figure 2 A power supply circuit of the present invention;

[0029] Figure 3 The oscillating circuit of the present invention;

[0030] Figure 4 The square wave output circuit of the present invention;

[0031] Figure 5 A clamping circuit according to the present invention;

[0032] Figure 6 A bootstrap circuit of the present invention;

[0033] Figure 7 The voltage equalizing circuit of the present invention;

[0034] Figure 8 This is the output voltage regulating circuit of the present invention. DETAILED DESCRIPTION

[0035] The present invention provides a high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit. Figures 1 to 8 The present invention is described with reference to the structural schematic diagram of FIG.

[0036] Example 1

[0037] A high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit, the circuit diagram is shown in Figure 1 As shown, it includes an external input terminal, the external input terminal is electrically connected to one end of a first capacitor CA, and the other end of the first capacitor CA is grounded;

[0038] an external output terminal, the external output terminal being electrically connected to one end of a second capacitor CB, the other end of the second capacitor CB being grounded;

[0039] A clamping circuit, used to suppress voltage surges, is connected in series between the external input terminal and the external output terminal, wherein the clamping circuit comprises at least two stages of clamping modules connected in series in sequence, wherein the clamping module comprises at least two clamping units connected in parallel, and wherein the clamping unit comprises:

[0040] A MOSFET tube, wherein the source of the MOSFET tube is electrically connected to the external input terminal, the drain of the MOSFET tube is electrically connected to the post-stage clamping module, the gate of the MOSFET tube is electrically connected to one end of a third capacitor C2, the other end of the third capacitor C2 is grounded, the end of the third capacitor C2 away from the ground end is electrically connected to one end of a first resistor R2, and the other end of the first resistor R2 is electrically connected to the drain of the MOSFET tube; wherein the first resistor R2 is a discharge resistor between the gate of the MOSFET tube and the drain of the MOSFET tube, and the third capacitor C2 is used to temporarily suppress a peak voltage when a voltage surge comes.

[0041] Also includes:

[0042] A power supply circuit, used to ensure normal power supply of the subsequent circuit, the input end of the power supply circuit being connected to the external input end;

[0043] An oscillating circuit, used for providing a square wave of a set frequency to a subsequent circuit, wherein an input end of the oscillating circuit is connected to an output end of the power supply circuit;

[0044] A bootstrap circuit, used for providing a gate driving voltage for the clamping unit, wherein the output end of the oscillation circuit is connected to the input end of the bootstrap circuit;

[0045] A voltage balancing circuit, used for balancing the clamping voltage of the MOSFET tube of the clamping unit;

[0046] The output voltage regulating circuit is used to set the output voltage, the input end of the output voltage regulating circuit is electrically connected to the external input end, and the output end of the output voltage regulating circuit is electrically connected to the external output end.

[0047] Under normal power supply conditions, the MOSFET in the clamping circuit is fully turned on, and the circuit is in a micro-power working state. When the input voltage exceeds the limiting voltage or an overvoltage surge occurs, the clamping circuit limits the output voltage to within the set voltage range. At this time, the module is in a linear voltage regulation working mode to ensure that the subsequent circuit is not affected by voltage transients.

[0048] Among them, Figure 2 As shown, the function of the power supply circuit is to provide a stable voltage for the subsequent circuit to ensure the normal power supply of the subsequent circuit. The power supply circuit is composed of a second resistor R1, a first transistor VT1, a first diode D1, a first voltage regulator DZ1 and a fourth capacitor C1. Among them, the second resistor R1 is the base current limiting resistor of the first transistor VT1, the first voltage regulator DZ1 is used to limit the output voltage of the base of the first transistor VT1, and the first diode D1 is used for high and low temperature compensation.

[0049] The power supply circuit includes a second resistor R1, a first transistor VT1, a first diode D1, a first voltage regulator DZ1 and a fourth capacitor C1, one end of the second resistor R1 is electrically connected to the external input end, the other end of the second resistor R1 is electrically connected to the anode of the first diode D1, the cathode of the first diode D1 is electrically connected to the cathode of the first voltage regulator DZ1, and the anode of the first voltage regulator DZ1 is grounded; the anode of the first diode D1 is electrically connected to the base of the first transistor VT1, the emitter of the first transistor VT1 is electrically connected to one end of the fourth capacitor C1, the other end of the fourth capacitor C1 is grounded, and the collector of the first transistor VT1 is electrically connected to the external input end.

[0050] The oscillation circuit includes a triangle wave generating circuit and a square wave output circuit for converting the triangle wave generating circuit into a square wave.

[0051] Among them, the triangle wave generating circuit is as follows Figure 3 As shown, the function is to generate a triangular wave. In the figure, IC1 is an integrated circuit chip, whose model is UCC2813-5, which provides a triangular wave. The output frequency can be changed by changing the sixth capacitor C10 and the third resistor R10. The fifth capacitor C11 is the energy storage capacitor of the reference VREF.

[0052] The triangle wave generating circuit includes a pulse width modulator IC1, wherein the pulse width modulator IC1 is UCC2813-5, wherein the FB port, the CS port, and the GND port of the UCC2813-5 are all grounded, the COMP port is electrically connected to one end of the fifth capacitor C11, and the other end of the fifth capacitor C11 is grounded, the R / C port is electrically connected to one end of the sixth capacitor C10, and the other end of the sixth capacitor C10 is grounded, and V cc Port is electrically connected to the power supply, V ref The port is electrically connected to an end of the fifth capacitor C11 away from the ground, and an end of the sixth capacitor C10 away from the ground is electrically connected to one end of the third resistor R10;

[0053] Among them, Figure 4 In the square wave output circuit shown in the figure, the fourth resistor R11 and the fifth resistor R12 divide the reference voltage and compare it with the triangle wave (RT), and output the square wave through the comparator IC2. The comparator IC2 is a comparator power supply energy storage capacitor. The sixth resistor R13, the seventh resistor R14, the second transistor VT2, and the third transistor VT3 form a power amplifier circuit to enhance the driving ability of the square wave and output the square wave through FB.

[0054] The square wave output circuit includes a comparator IC2, wherein the non-inverting input terminal of the comparator IC2 is electrically connected to the end of the sixth capacitor C10 away from the ground, the inverting input terminal of the comparator IC2 is electrically connected to one end of the fourth resistor R11 and the fifth resistor R12 respectively, the other end of the fourth resistor R11 is electrically connected to the other end of the third resistor R10, the other end of the fifth resistor R12 is grounded, the positive power supply port of the comparator IC2 is electrically connected to the power supply and one end of the seventh capacitor C12 respectively, and the other end of the seventh capacitor C12 is connected to the The negative power supply port of the comparator IC2 is grounded, the output end of the comparator IC2 is electrically connected to one end of the sixth resistor R13 and the seventh resistor R14 respectively, the other end of the sixth resistor R13 is electrically connected to the power supply, the other end of the seventh resistor R14 is electrically connected to the base of the second triode VT2 and the third triode VT3 respectively, the emitter of the second triode VT2 is electrically connected to the emitter of the third triode VT3, the collector of the second triode VT2 is grounded, and the collector of the third triode VT3 is electrically connected to the power supply.

[0055] Among them, Figure 5 The clamping circuit shown is a non-isolated linear suppression circuit. The function of the clamping circuit is to suppress voltage surges and clamp the output voltage to a set voltage. The excess voltage is evenly distributed in the multi-stage series-parallel MOSFET tubes of the clamping circuit and is ultimately consumed in the form of heat.

[0056] Figure 5It includes two levels of clamping, and 4 clamping units are connected in parallel in each level.

[0057] Under normal power supply conditions, the MOSFET tubes of the first stage Q1A~Q4A and the second stage Q2B~Q4B are fully turned on. Since the internal resistance of the MOSFET tube is very low, the power consumption is very small.

[0058] When a surge voltage comes, assuming that the input surge voltage is 80V / 50ms, the output voltage is set at 38V. At this time, the first-stage output voltage is 59V, the second-stage output voltage is 38V, and the voltage on the two-stage MOSFET tubes is 21V. The two-stage clamping circuit can effectively reduce the voltage between the source (D) and drain (S) on the MOSFET tube, enhance the overcurrent capability of the MOSFET tube, and improve the reliability of the MOSFET tube.

[0059] Among them, Figure 6 The bootstrap circuit shown in FIG. 1 is used to provide a gate drive voltage for the clamping circuit. The square wave output circuit sends the square wave to the seventh capacitor C13 and the ninth capacitor C15 through FB. VTH2 and VO1 in the figure are the gate and drain of the MOSFET tube in the second-stage clamping circuit, and VTH1 and VS1 are the gate and drain of the MOSFET tube in the first-stage clamping circuit. The square wave passes through the seventh capacitor C13 and the ninth capacitor C15, using the unidirectional conduction principle of the diode to increase the voltage to the voltage of turning on the clamping MOSFET tube, wherein the eighth capacitor C14 and the tenth capacitor C16 are filter capacitors, the eighth resistor R15 and the fifteenth resistor R16 are current limiting resistors, and the second voltage regulator DZ2 and the fourth voltage regulator DZ4 are voltage regulator diodes between the gate and drain of the MOSFET tube to prevent the clamping MOSFET tube from being damaged by excessive voltage.

[0060] The bootstrap circuit includes at least two bootstrap units, and the bootstrap unit includes a seventh capacitor C13 having one end electrically connected to the emitter of the third triode VT3, and the other end of the seventh capacitor C13 is respectively electrically connected to the anode of the second diode D2 and the cathode of the third diode D3, the anode of the third diode D3 is electrically connected to one end of the eighth capacitor C14, and the other end of the eighth capacitor C14 is electrically connected to the cathode of the second diode D2, and the cathode of the second diode D2 is also electrically connected to one end of the eighth resistor R15, and the other end of the eighth resistor R15 is electrically connected to the cathode of the second voltage regulator tube DZ2, and the anode of the second voltage regulator tube DZ2 is electrically connected to the anode of the third diode D3; the cathode of the second voltage regulator tube DZ2 is electrically connected to the gate of the MOSFET tube, and the anode of the second voltage regulator tube DZ2 is electrically connected to the drain of the MOSFET tube.

[0061] Among them, Figure 7The voltage balancing circuit shown has the function of balancing the clamping voltages of the multi-stage main power MOSFET tubes of the clamping circuit, thereby effectively improving the power level of the clamping circuit and the reliability of the MOSFET tubes.

[0062] The voltage equalizing circuit includes at least two voltage equalizing units connected in series in sequence, and the voltage equalizing unit includes a ninth resistor R24 ​​at one end electrically connected to the external input end, the other end of the ninth resistor R24 ​​is electrically connected to one end of the tenth resistor R17, the other end of the tenth resistor R17 is electrically connected to the gate of the MOSFET tube, the external input end is electrically connected to the cathode of the fifth voltage regulator tube DZ5, and the anode of the fifth voltage regulator tube DZ5 is electrically connected to the end of the ninth resistor R24 ​​away from the external input end.

[0063] VTH2 in the voltage balancing circuit is the second-stage gate (G), VTH1 is the first-stage gate (G), the third voltage regulator DZ3 is the second-stage clamping diode, the fifth diode D4 is the temperature drift suppression diode, the fifth voltage regulator DZ5 is the first-stage clamping diode, and the fourth diode D7 is the temperature drift suppression diode. The sixteenth resistor R22 and the tenth resistor R17 are current limiting resistors, and the seventeenth resistor R23 and the ninth resistor R24 ​​are voltage dividing resistors.

[0064] If multiple MOSFETs are connected in series, you can add more on this basis. In actual applications, depending on the power situation, it can be divided into 6-8 levels at most, and four MOSFETs can be connected in series.

[0065] Among them, Figure 8 The output voltage regulating circuit shown in the figure has the function of setting the output voltage. The eleventh resistor R19, the twelfth resistor R20 and the thirteenth resistor R21 are voltage-dividing resistors for setting the output voltage, the fourth transistor VT4 and the fifth transistor VT5 form a constant current source, and the fourteenth resistor R18 is a current-limiting resistor.

[0066] When the output voltage is less than the set voltage, the fourth transistor VT4 is not turned on and the Vo1 output is not clamped. When the output voltage is greater than the set voltage, the fourth transistor VT4 is turned on and the Vo1 voltage is clamped to the set voltage. Since Vo1 is the drain of the second-stage clamping MOSFET tube, the voltage surge suppression function is achieved.

[0067] The output voltage regulating circuit includes an eleventh resistor R19, a twelfth resistor R20 and a thirteenth resistor R21 which are connected in series in sequence, the eleventh resistor R19 is electrically connected to the external output terminal, the thirteenth resistor R21 is grounded, the end of the thirteenth resistor R21 away from the ground end is electrically connected to the base of the fourth triode VT4, the collector of the fourth triode VT4 is electrically connected to the external output terminal, the emitter of the fourth triode VT4 is electrically connected to the emitter of the fifth triode VT5, the collector of the fifth triode VT5 is electrically connected to the power supply, and the base of the fifth triode VT5 is electrically connected to the V of UCC2813-5 ref Port, the emitter of the fifth transistor VT5 is electrically connected to one end of the fourteenth resistor R18, and the other end of the fourteenth resistor R18 is grounded.

[0068] Example 2

[0069] In order to improve the pressure equalization accuracy, Figure 7 On the basis of using resistor voltage balancing, a diode is added, specifically, a fourth diode D7 is included, the anode of the fourth diode D7 is electrically connected to the external input terminal, and the cathode of the fourth diode D7 is electrically connected to the cathode of the fifth voltage regulator tube DZ5.

[0070] The invention provides a high-power multi-channel series-parallel voltage-equalizing voltage surge suppression circuit, which has low power consumption, high precision, long working time, strong practicability and is worthy of promotion.

[0071] What is disclosed above is only a preferred specific embodiment of the present invention; however, the embodiments of the present invention are not limited thereto, and any changes that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit, characterized in that: include: an external input terminal, the external input terminal being electrically connected to one end of a first capacitor CA, the other end of the first capacitor CA being grounded; an external output terminal, the external output terminal being electrically connected to one end of a second capacitor CB, the other end of the second capacitor CB being grounded; A clamping circuit is connected in series between the external input terminal and the external output terminal, wherein the clamping circuit comprises at least two stages of clamping modules connected in series in sequence, wherein the clamping module comprises at least two clamping units connected in parallel, and wherein the clamping unit comprises: A MOSFET tube, wherein the source of the MOSFET tube is electrically connected to the external input terminal, the drain of the MOSFET tube is electrically connected to the post-stage clamping module, the gate of the MOSFET tube is electrically connected to one end of a third capacitor C2, the other end of the third capacitor C2 is grounded, the end of the third capacitor C2 away from the ground end is electrically connected to one end of a first resistor R2, and the other end of the first resistor R2 is electrically connected to the drain of the MOSFET tube; Also includes: A power supply circuit, used to ensure normal power supply of the subsequent circuit, the input end of the power supply circuit being connected to the external input end; An oscillating circuit, used for providing a square wave of a set frequency to a subsequent circuit, wherein an input end of the oscillating circuit is connected to an output end of the power supply circuit; A bootstrap circuit, used for providing a gate driving voltage for the clamping unit, wherein the output end of the oscillation circuit is connected to the input end of the bootstrap circuit; A voltage balancing circuit, used for balancing the clamping voltage of the MOSFET tube of the clamping unit; An output voltage regulating circuit, used for setting an output voltage, wherein an input terminal of the output voltage regulating circuit is electrically connected to an external input terminal, and an output terminal of the output voltage regulating circuit is electrically connected to an external output terminal; The power supply circuit includes a second resistor R1, a first transistor VT1, a first diode D1, a first voltage regulator DZ1 and a fourth capacitor C1, one end of the second resistor R1 is electrically connected to the external input end, the other end of the second resistor R1 is electrically connected to the anode of the first diode D1, the cathode of the first diode D1 is electrically connected to the cathode of the first voltage regulator DZ1, and the anode of the first voltage regulator DZ1 is grounded; the anode of the first diode D1 is electrically connected to the base of the first transistor VT1, the emitter of the first transistor VT1 is electrically connected to one end of the fourth capacitor C1, the other end of the fourth capacitor C1 is grounded, and the collector of the first transistor VT1 is electrically connected to the external input end; The oscillation circuit comprises: A triangular wave generating circuit and a square wave output circuit for converting the triangular wave generating circuit into a square wave, wherein the triangular wave generating circuit comprises a pulse width modulator IC1, wherein the pulse width modulator IC1 is UCC2813-5, wherein the FB port, the CS port and the GND port of the UCC2813-5 are all grounded, The COMP port is electrically connected to one end of the fifth capacitor C11, the other end of the fifth capacitor C11 is grounded, the R / C port is electrically connected to one end of the sixth capacitor C10, the other end of the sixth capacitor C10 is grounded, and the V cc Port is electrically connected to the power supply, V ref The port is electrically connected to an end of the fifth capacitor C11 away from the ground, and an end of the sixth capacitor C10 away from the ground is electrically connected to one end of the third resistor R10; The square wave output circuit includes a comparator IC2, wherein the non-inverting input terminal of the comparator IC2 is electrically connected to the end of the sixth capacitor C10 away from the ground, the inverting input terminal of the comparator IC2 is electrically connected to one end of the fourth resistor R11 and the fifth resistor R12 respectively, the other end of the fourth resistor R11 is electrically connected to the other end of the third resistor R10, the other end of the fifth resistor R12 is grounded, the positive power supply port of the comparator IC2 is electrically connected to the power supply and one end of the seventh capacitor C12 respectively, and the other end of the seventh capacitor C12 is connected to the The negative power supply port of the comparator IC2 is grounded, the output end of the comparator IC2 is electrically connected to one end of the sixth resistor R13 and the seventh resistor R14 respectively, the other end of the sixth resistor R13 is electrically connected to the power supply, the other end of the seventh resistor R14 is electrically connected to the base of the second triode VT2 and the third triode VT3 respectively, the emitter of the second triode VT2 is electrically connected to the emitter of the third triode VT3, the collector of the second triode VT2 is grounded, and the collector of the third triode VT3 is electrically connected to the power supply.

2. A high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit according to claim 1, characterized in that: The bootstrap circuit includes at least two bootstrap units, and the bootstrap unit includes a seventh capacitor C13 having one end electrically connected to the emitter of the third triode VT3, and the other end of the seventh capacitor C13 is respectively electrically connected to the anode of the second diode D2 and the cathode of the third diode D3, the anode of the third diode D3 is electrically connected to one end of the eighth capacitor C14, and the other end of the eighth capacitor C14 is electrically connected to the cathode of the second diode D2, and the cathode of the second diode D2 is also electrically connected to one end of the eighth resistor R15, and the other end of the eighth resistor R15 is electrically connected to the cathode of the second voltage regulator tube DZ2, and the anode of the second voltage regulator tube DZ2 is electrically connected to the anode of the third diode D3; the cathode of the second voltage regulator tube DZ2 is electrically connected to the gate of the MOSFET tube, and the anode of the second voltage regulator tube DZ2 is electrically connected to the drain of the MOSFET tube.

3. A high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit according to claim 2, characterized in that: The voltage balancing circuit includes at least two voltage balancing units connected in series in sequence, and the voltage balancing unit includes a ninth resistor R24 ​​having one end electrically connected to the external input end, the other end of the ninth resistor R24 ​​is electrically connected to one end of the tenth resistor R17, the other end of the tenth resistor R17 is electrically connected to the gate of the MOSFET tube, the external input end is electrically connected to the cathode of the fifth voltage stabilizing tube DZ5, and the anode of the fifth voltage stabilizing tube DZ5 is electrically connected to the end of the ninth resistor R24 ​​away from the external input end.

4. A high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit according to claim 3, characterized in that: It also includes a fourth diode D7, an anode of the fourth diode D7 is electrically connected to the external input terminal, and a cathode of the fourth diode D7 is electrically connected to a cathode of the fifth voltage-stabilizing tube DZ5.

5. A high-power multi-channel series-parallel voltage equalization voltage surge suppression circuit according to claim 1, characterized in that: The output voltage regulating circuit includes an eleventh resistor R19, a twelfth resistor R20 and a thirteenth resistor R21 which are connected in series in sequence, the eleventh resistor R19 is electrically connected to the external output terminal, the thirteenth resistor R21 is grounded, the end of the thirteenth resistor R21 away from the ground end is electrically connected to the base of the fourth transistor VT4, the collector of the fourth transistor VT4 is electrically connected to the external output terminal, the emitter of the fourth transistor VT4 is electrically connected to the emitter of the fifth transistor VT5, the collector of the fifth transistor VT5 is electrically connected to the power supply, and the base of the fifth transistor VT5 is electrically connected to V of UCC2813-5 ref Port, the emitter of the fifth transistor VT5 is electrically connected to one end of the fourteenth resistor R18, and the other end of the fourteenth resistor R18 is grounded.

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