Interface conversion circuit, chip, chip testing system and method

Abstract

The present invention discloses an interface conversion circuit, a chip, a chip testing system and a method. The interface conversion circuit is placed inside the chip under test, and includes: a data module, a write module, a read module and a comparison output module. The input end of the data module is connected to the main control device; the data module is used to obtain test stimulus data and expected response data according to the test vector sent by the main control device; the input end of the write module is connected to the first output end of the data module, and the output end is connected to the input end of the test access port of the chip under test; the input end of the read module is connected to the output end of the test access port, and is used to collect the read data fed back by the chip under test; the first input end of the comparison output module is connected to the second output end of the data module, and the second input end is connected to the output end of the read module; the comparison output module is used to obtain and output an error signal according to the read data and the expected response data. The embodiment of the present invention can improve the flexibility and efficiency of chip testing.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of chip testing technology, and in particular to an interface conversion circuit, a chip, a chip testing system and a method. Background Art

[0002] In order to ensure that the chip can work properly, the chip must be strictly tested during and after the chip manufacturing process. Usually, chip testing is performed through the Joint Test Action Group (JTAG) test pin. The test method of the standard JTAG protocol is to inject the test vector into the chip at the test data input port, and then obtain the response signal of the chip at the test data output port to detect whether the chip functions normally. The test circuit inside the chip is responsible for receiving and executing the test vector sent by the external test system, and then feeding the result vector back to the external chip test system. With the high development of computing needs, software has higher and higher requirements for computing power, resulting in larger and larger chip scales, more and more complex test vectors, and longer and longer time required for chip testing. Therefore, the existing chip testing methods have the problems of poor flexibility and low efficiency. Summary of the invention

[0003] The embodiments of the present invention provide an interface conversion circuit, a chip, a chip testing system and a method to improve the flexibility and efficiency of chip testing.

[0004] In a first aspect, an embodiment of the present invention provides an interface conversion circuit, which is placed inside a chip under test and used for chip testing. The interface conversion circuit includes:

[0005] A data module, comprising an input end, a first output end and a second output end; the input end of the data module is used to connect to an external main control device; the data module is used to obtain test stimulus data and expected response data according to a test vector sent by the main control device; wherein the test vector matches the interface conversion circuit;

[0006] A write module, comprising an input end and an output end, wherein the input end of the write module is connected to the first output end of the data module, and the output end of the write module is connected to the input end of the test access port of the chip under test, so as to output the test stimulus data to the chip under test;

[0007] A reading module, comprising an input end and an output end; the input end of the reading module is connected to the output end of the test access port of the chip under test; the reading module is used to collect the reading data fed back by the chip under test;

[0008] A comparison output module comprises a first input terminal, a second input terminal and an output terminal; the first input terminal of the comparison output module is connected to the second output terminal of the data module, and the second input terminal of the comparison output module is connected to the output terminal of the reading module; the comparison output module is used to obtain an error signal according to the read data and the expected response data and output it through the output terminal.

[0009] Optionally, the data module further includes a third output terminal, and the data module is further used to obtain mask data according to the test vector sent by the main control device; the comparison output module further includes a third input terminal, and the third input terminal of the comparison output module is connected to the third output terminal of the data module;

[0010] The comparison output module includes: an AND unit, an XOR unit and an error register;

[0011] The AND unit comprises a first input terminal, a second input terminal and an output terminal; the first input terminal of the AND unit is connected to the third output terminal of the data module; the second input terminal of the AND unit is connected to the output terminal of the reading module; the AND unit is used to obtain the actual concerned data according to the mask data and the read data, and filter the irrelevant data;

[0012] The XOR unit comprises a first input terminal, a second input terminal and an output terminal; the first input terminal of the XOR unit is connected to the second output terminal of the data module; the second input terminal of the XOR unit is connected to the output terminal of the AND unit; the XOR unit is used to obtain a comparison result according to the actual concerned data and the expected response data;

[0013] The error register includes a first input end and a first output end, the first input end of the error register is connected to the output end of the XOR unit, and the first output end of the error register is the output end of the comparison output module; the error register is used to obtain the error signal according to the comparison result, and store and output the error signal.

[0014] Optionally, the error register further includes a second output terminal;

[0015] The comparison output module also includes an adder;

[0016] The adder comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the adder is connected to the output terminal of the XOR unit; the second input terminal of the adder is connected to the second output terminal of the error register; the output terminal of the adder is connected to the first input terminal of the error register; the adder is used to increase the error signal by one when the comparison result indicates that the actual concerned data is wrong, and transmit the error signal to the error register;

[0017] The error signal includes the accumulated number of errors in the comparison result.

[0018] Optionally, the data module includes: an instruction decoding unit, including an input end, a first output end, and a second output end; the input end of the instruction decoding unit is the input end of the data module, the first output end of the instruction decoding unit is the first output end of the data module, and the second output end of the instruction decoding unit is the second output end of the data module;

[0019] The instruction decoding unit is configured with an instruction set, and the instruction decoding unit is used to obtain a test instruction according to the test vector, and the test instruction matches the corresponding instruction in the instruction set; the test instruction includes original test data; the original test data includes the test stimulus data and the expected response data.

[0020] Optionally, the interface conversion circuit further comprises: a control module; the control module comprises a sequence control unit; the sequence control unit is respectively connected to the instruction decoding unit and the writing module; the sequence control unit is used to control the test sequence.

[0021] Optionally, the interface conversion circuit further includes: a control module;

[0022] The control module includes an enabling control unit; the enabling control unit is connected to the writing module and the reading module, and is used to control the start or end of a test.

[0023] Optionally, the interface conversion circuit further includes:

[0024] A data selection module; the data selection module is connected to the comparison output module and the reading module respectively; the data selection module outputs a test result; the test result includes the error signal or the read data;

[0025] Control module; the control module includes a mode control unit; the mode control unit is connected to the data selection module, and is used to control the test result output by the data selection module to be the error signal or the read data.

[0026] In a second aspect, an embodiment of the present invention further provides a chip, comprising: an interface conversion circuit as provided in any embodiment of the present invention.

[0027] In a third aspect, an embodiment of the present invention further provides a chip testing system, comprising: a main control device and a chip provided by any embodiment of the present invention;

[0028] The main control device is connected to the chip; the main control device is used to transmit the test vector to the chip.

[0029] In a fourth aspect, an embodiment of the present invention further provides a chip testing method of a chip provided by any embodiment of the present invention, comprising:

[0030] The main control device transmits the test vector matching the interface conversion circuit in the chip to the interface conversion circuit in the chip;

[0031] The data module receives the test vector and obtains test stimulus data and expected response data according to the test vector;

[0032] The writing module transmits the test stimulus data to the chip through the test access port;

[0033] The reading module collects the reading data fed back by the chip through the test access port;

[0034] The comparison output module obtains and outputs an error signal according to the read data and the expected response data.

[0035] The interface conversion circuit provided by the embodiment of the present invention is provided with a data module, a write module and a read module. Through the processing of the test vector by the data module, the test stimulus data can be directly transmitted to the test access port of the chip under test through the write module, and the read module can directly extract the read data from the test access port. With such a configuration, the chip test can be separated from the JTAG test pin, thereby improving the flexibility of the chip test. In addition, a comparison output module is provided in the interface conversion circuit, which can compare the read data and the expected response data inside the chip. The test system can directly obtain the error signal output by the comparison output module to know whether the chip is normal, and it is not necessary to obtain all the read data for processing outside the chip, thereby reducing data transmission and improving the test efficiency. Therefore, compared with the prior art, the embodiment of the present invention can improve the flexibility and efficiency of chip testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a structural schematic diagram of an interface conversion circuit provided by an embodiment of the present invention;

[0037] Figure 2 is a structural schematic diagram of another interface conversion circuit provided by an embodiment of the present invention;

[0038] Figure 3 is a structural diagram of a comparison output module provided by an embodiment of the present invention;

[0039] Figure 4 is a structural diagram of another comparison output module provided by an embodiment of the present invention;

[0040] Figure 5It is a flowchart of a chip testing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0042] An embodiment of the present invention provides an interface conversion circuit, which is placed inside a chip under test and is used for chip testing. Figure 1 Schematic diagram of an interface conversion circuit provided by an embodiment of the present invention. Figure 1 The interface conversion circuit 10 includes: a data module 110, a writing module 120, a reading module 130 and a comparison output module 140.

[0043] The interface conversion circuit 10 is placed in the chip under test 1, and the chip under test 1 also includes a test access port (TAP) 20. The data module 110 includes an input end, a first output end, and a second output end; the input end of the data module 110 is used to connect to the external main control device 2; the data module 110 is used to obtain test stimulus data and expected response data according to the test vector sent by the main control device 2; wherein the test vector matches the interface conversion circuit 10; the write module 120 includes an input end and an output end, the input end of the write module 120 is connected to the first output end of the data module 110, and the output end of the write module 120 is connected to the input end of the test access port 20 of the chip under test 1, so as to output the test stimulus data to the chip under test 1; The reading module 130 includes an input end and an output end; the input end of the reading module 130 is connected to the output end of the test access port 20 of the chip under test 1; the reading module 130 is used to collect the reading data fed back by the chip under test 1; the comparison output module 140 includes a first input end, a second input end and an output end; the first input end of the comparison output module 140 is connected to the second output end of the data module 110, and the second input end of the comparison output module 140 is connected to the output end of the reading module 130; the comparison output module 140 is used to obtain an error signal based on the read data and the expected response data and output it through the output end.

[0044] Optionally, the test vector sent by the main control device 2 includes at least test stimulus data and expected response data; wherein, the test stimulus data is used to test the chip under test 1, and the expected response data corresponds one-to-one with the test stimulus data, and is used to detect whether the read data fed back by the chip under test 1 is correct.

[0045] Exemplarily, the working process of the interface conversion circuit 10 is as follows: the data module 110 parses the received test vector, and then transmits the test stimulus data to the write module 120, and transmits the expected response data to the comparison output module 140; the write module 120 outputs the received test stimulus data to the chip under test 1 through the test access port 20; after waiting for the chip under test 1 to process the test stimulus data, the read module 130 collects the read data fed back by the chip under test 1 through the test access port 20, and transmits it to the comparison output module 140; the comparison output module 140 compares the read data with the expected response data received previously, generates an error signal and outputs it to the main control device 2.

[0046] Optionally, the interface conversion circuit 10 is suitable for various commonly used buses, interfaces and protocol types such as serial peripheral interface (SPI), I2C (Inter-Integrated Circuit), universal asynchronous receiver / transmitter (UART), controller area network (CAN), universal serial bus (USB), and peripheral component interconnect express (PCIE). It can unify the different test environments of the chip under test 1 at different stages and test all vectors with a consistent setting environment.

[0047] Optionally, there are multiple ways for the comparison output module 140 to output an error signal, which can be set according to needs in actual applications. For example, when the chip under test 1 needs to process multiple test vectors, the comparison output module 140 can transmit an identification signal representing whether the result is correct or wrong to the main control device each time; or, when the result is correct, no signal is output until an error result occurs or the test is completed; or, the result corresponding to each test vector is stored, and after the test is completed, the number of correct results and error results and their corresponding instruction positions are output together. In short, the comparison between the read data and the expected response data is completed inside the chip under test 1, and the interface conversion circuit only outputs an error signal that identifies the test result.

[0048] The interface conversion circuit 10 provided by the embodiment of the present invention is provided with a data module 110, a write module 120 and a read module 130. Through the processing of the test vector by the data module 110, the test stimulus data can be directly transmitted to the test access port 20 of the chip under test 1 through the write module 120, and the read module 130 can directly extract the read data from the test access port 20. In this way, the chip test can be separated from the JTAG pin, which improves the flexibility of the chip test. In addition, the interface conversion circuit 10 is provided with a comparison output module 140, and by writing the expected response data and the test stimulus data into the inside of the chip under test 1 together, the read data and the expected response data can be compared inside the chip, and the test system can directly obtain the error signal output by the comparison output module 140 to know whether the chip under test 1 is normal, and it is not necessary to obtain all the read data for processing outside the chip under test 1, thereby reducing data transmission and improving test efficiency. Therefore, the embodiment of the present invention can improve the flexibility and efficiency of chip testing.

[0049] Figure 2 FIG. 1 is a schematic diagram of another interface conversion circuit provided by an embodiment of the present invention. Figure 2 , based on the above embodiments, optionally, the interface conversion circuit 10 further includes a cache module 170 and a control module 150. The cache module 170 is connected to the master device 2, the data module 110, the comparison output module 140 and the control module 150, and is used for data transmission between the master device 2 and the chip under test 1. Specifically, the cache module 170 reads the test vector in the master device 2 and transmits it to the data module 110; the comparison output module 140 outputs an error signal to the cache module 170, which is transmitted to the master device 2 by the cache module 170. The way in which the cache module 170 transmits the test vector and the error signal can be controlled by the control module 150. Exemplarily, at the beginning of the test, the cache module 170 can cache all test vectors and transmit them one by one to the data module 110; and during the test, the cache module 170 can store the test results of multiple test vectors and finally transmit them together to the master device 2.

[0050] Continue to see Figure 2On the basis of the above embodiments, the interface conversion circuit 10 may optionally further include a parallel-serial conversion module 180 and a serial-parallel conversion module 190. The parallel-serial conversion module 180 is connected between the write module 120 and the test access port 20; the serial-parallel conversion module 190 is connected between the read module 130 and the test access port 20. In this configuration, the test stimulus data is input from the test data input terminal (referred to as TDI) in the test access port 20 through parallel-serial conversion; and the feedback data (i.e., read data) of the chip under test 1 is output from the test data output terminal (referred to as TDO) in the test access port 20, and then converted from serial to parallel data to be read by the read module 130, which can reduce the test time and improve the test efficiency.

[0051] Continue to see Figure 2 On the basis of the above-mentioned embodiments, optionally, since in some test processes, only some bits in the data fed back by the chip under test 1 are concerned about whether they are correct, it is not necessary to judge each bit in the read data. In order to simplify the comparison process, the data module 110 also includes a third output terminal, and the data module 110 is also used to obtain mask data according to the test vector sent by the main control device; the comparison output module 140 also includes a third input terminal, and the third input terminal of the comparison output module 140 is connected to the third output terminal of the data module 110. On this basis, exemplarily, the working process of the comparison output module 140 is: first, the actual concerned data is obtained according to the read data and the mask data, and the unconcerned data is filtered; then the actual concerned data is compared with the expected response data to determine whether the read data fed back by the chip under test 1 is correct. Among them, the format of the expected response data parsed by the data module 110 according to the test vector corresponds to the format of the actual concerned data.

[0052] The above embodiments exemplarily illustrate the working principle of the interface conversion circuit 10 . Several possible structures of the comparison output module 140 are described below, but are not intended to limit the present invention.

[0053] Figure 3 is a schematic diagram of the structure of a comparison output module provided by an embodiment of the present invention. Figure 3 In one implementation, optionally, the comparison output module 140 includes: an AND unit 141 , an XOR unit 142 and an error register 143 .

[0054] The AND unit 141 includes a first input terminal, a second input terminal and an output terminal; the first input terminal of the AND unit 141 is connected to the third output terminal of the data module 110 for receiving the mask data Dmask; the second input terminal of the AND unit 141 is connected to the output terminal of the read module 130 for receiving the read data Dread; the AND unit 141 is used to obtain the actual concerned data according to the mask data Dmask and the read data Dread (the mask data Dmask and the read data Dread are ANDed), and filter the unconcerned data. The XOR unit 142 includes a first input terminal, a second input terminal and an output terminal; the first input terminal of the XOR unit 142 is connected to the second output terminal of the data module 110 for receiving the expected response data Dexp; the second input terminal of the XOR unit 142 is connected to the output terminal of the AND unit 141 for receiving the actual concerned data; the XOR unit 142 is used to obtain the comparison result according to the actual concerned data and the expected response data Dexp (the actual concerned data and the expected response data Dexp are XORed). The error register 143 includes a first input terminal and a first output terminal. The first input terminal of the error register 143 is connected to the output terminal of the XOR unit 142, and the first output terminal of the error register 143 is the output terminal of the comparison output module 140. The error register 143 is used to obtain an error signal Serror according to the comparison result, and store and output the error signal Serror.

[0055] Optionally, the error register 143 can be an addition register (or accumulation register). When there are multiple test vectors, each comparison result is temporarily stored in the error register 143, and when the comparison result of the error register 143 indicates that the actual data of concern is incorrect, the error register 143 automatically accumulates. Finally, the error register can output the number of errors, error data, error data bits and other contents as an error signal Serror.

[0056] Figure 4 FIG. 1 is a schematic diagram of another comparison output module provided by an embodiment of the present invention. Figure 4 On the basis of the above embodiments, optionally, the error register 143 further includes a second output terminal; the comparison output module 140 further includes an adder 144 .

[0057] Among them, the adder 144 includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the adder 144 is connected to the output terminal of the XOR unit 142; the second input terminal of the adder 144 is connected to the second output terminal of the error register 143; the output terminal of the adder 144 is connected to the first input terminal of the error register 143; the adder 144 is used to increase the error signal Serror by one and transmit it to the error register 143 when the comparison result indicates that the actual data of concern is wrong (for example, the XOR unit 142 outputs 1, that is, the comparison result is 1).

[0058] Exemplarily, the working principle of the comparison output module 140 is as follows: the initial value recorded in the error register 143 is set to 0, and the value recorded in the error register 143 is transmitted to the adder 144 through its second output terminal; the AND unit 141 performs an AND operation on the mask data Dmask and the read data Dread to obtain the actual concerned data, and filters the unconcerned data; the XOR unit 142 performs an XOR operation on the actual concerned data and the expected response data Dexp to obtain a comparison result; the adder 144 determines whether to add 1 based on the data transmitted by the error register 143 according to the value of the comparison result, and outputs the result to the error register 143, and the error register 143 updates and stores the recorded value and then outputs it. Among them, when there are multiple test vectors to be tested, each time the comparison result indicates that the actual concerned data does not match the expected response data (that is, the comparison result is 1), the adder 143 adds 1, and finally, the error signal Serror output by the error register 143 includes the accumulated number of errors of the comparison result. In other words, as long as the error signal Serror is not 0, it means that the chip 1 under test is unqualified and the test fails.

[0059] Continue to see Figure 2 On the basis of the above embodiments, optionally, the data module 110 includes: an instruction decoding unit 111. The instruction decoding unit 111 includes an input end, a first output end, and a second output end; the input end of the instruction decoding unit 111 is the input end of the data module 110, the first output end of the instruction decoding unit 111 is the first output end of the data module 110, and the second output end of the instruction decoding unit 111 is the second output end of the data module 110. Optionally, the instruction decoding unit 111 also includes a third output end, which is the third output end of the data module 110.

[0060] Optionally, the instruction decoding unit 111 is configured with an instruction set, and the instruction decoding unit 111 is used to obtain a test instruction according to a test vector, and the test instruction matches a corresponding instruction in the instruction set; the test instruction includes original test data; the original test data includes test stimulus data and expected response data. Optionally, the original test data also includes mask data.

[0061] Exemplarily, the instruction decoding unit 111 decodes the received test vector according to the rule of the instruction set to obtain a test instruction. The structure of the test instruction is shown in Table 1.

[0062] Table 1

[0063]

[0064] Referring to Table 1, the test instruction includes instruction data and original test data. The length of the test instruction can vary according to the length of the configuration instruction and data. Exemplarily, the instruction data includes data that abstractly describes the encoding method, encoding structure, etc., such as instruction type, loop length, and data length, which can identify the test vector, and can all be identified in the form of binary encoding; the original test data contains data related to the actual detection of the chip, such as test stimulus data, expected response data, and mask data. Among them, each test instruction may contain multiple test stimulus data, expected response data, and mask data, which are reflected in Table 1 with ellipsis.

[0065] Continue to see Figure 2 On the basis of the above-mentioned embodiments, optionally, the control module 150 in the interface conversion circuit 10 is connected to the data module 110, and is used to analyze the instruction data parsed by the instruction decoding unit 111 and execute the corresponding instruction. The data module 110 transmits the instruction data to the control module 150, transmits the test stimulus data to the writing module 120, and transmits the expected response data and the mask data to the comparison output module 140. Among them, different instructions correspond to different modules in the interface conversion circuit. Several possible implementations are described below, but they are not intended to limit the present invention.

[0066] In one embodiment, the instruction is a normal read / write instruction; the control module 150 includes an enable control unit 152; the enable control unit 152 is connected to the write module 120 and the read module 130, and is used to control the normal start or end of the test. In this way, the chip test process is controllable, for example, when the comparison result in the comparison output module 140 is wrong for the first time, the chip is determined to be unqualified and the test is stopped, so as to shorten the test time and improve the test efficiency.

[0067] In another embodiment, the instruction includes a loop instruction, that is, repeatedly executing the test process included in the same original test data, and the instruction includes the number of loops. The control module 150 includes a sequence control unit 151; the sequence control unit 151 is respectively connected to the instruction decoding unit 111 and the writing module 120, and is used to control the test sequence. For example, the sequence control unit 151 includes an instruction counter, which records the number of loops while controlling the test loop, and stops testing the test stimulus data when the number of loops reaches a specified value. In this way, during the loop test, the data module 110 does not need to read and parse the test vector and transmit the test instruction every time the test is performed, which simplifies the test logic, saves test time, and improves test efficiency.

[0068] Continue to see Figure 2In another embodiment, optionally, the instruction is a debugging instruction, and the interface conversion circuit 10 further includes: a data selection module 160. The data selection module 160 is connected to the comparison output module 140 and the reading module 130 respectively; the data selection module 160 outputs the test result; the test result includes an error signal or the original read data fed back by the chip under test 1 through the test access port 20. The control module 150 includes a mode control unit 153; the mode control unit 153 is connected to the data selection module 160, and is used to control the test result output by the data selection module 160 to be an error signal or read data.

[0069] Exemplarily, the mode control unit 153 controls the chip test to be in debug mode or normal mode under the control of the debug instruction. Among them, in debug mode, it is compatible with the traditional test scheme, that is, after the reading module 130 reads the data fed back by the chip under test 1 each time, the data selection module 160 returns it to the main control device 2, or stops at a specific test vector and returns the read data to the main control device 2. This mode is very useful in the early chip testing stage, and can quickly locate the problem location in the chip under test 1. After the test vector and the test environment are stable, the chip test can adopt the normal mode. In normal mode, the mode control unit 153 controls the data selection module 160 to read the error signal in the comparison output module 140 and output it. If the error signal is greater than 0, it means that an error has occurred in the chip under test 1, which is conducive to improving the test efficiency.

[0070] An embodiment of the present invention further provides a chip, comprising: an interface conversion circuit as provided in any embodiment of the present invention, having corresponding beneficial effects.

[0071] The embodiment of the present invention also provides a chip testing system, comprising: a main control device and a chip provided by any embodiment of the present invention, which has corresponding beneficial effects. The main control device is connected to the chip; the main control device is used to transmit the test vector to the chip.

[0072] An embodiment of the present invention further provides a chip testing method, which is applied to the chip testing system provided by any embodiment of the present invention, and is used to test the chip provided by any embodiment of the present invention, and has corresponding beneficial effects. Figure 5 FIG. 1 is a flow chart of a chip testing method provided by an embodiment of the present invention. Figure 5 , the chip testing method comprises the following steps:

[0073] S110 , the main control device transmits a test vector matching the interface conversion circuit in the chip to the interface conversion circuit in the chip.

[0074] The main control device may transmit the test vector to the data module through the cache module.

[0075] S120, the data module receives the test vector, and obtains test stimulus data and expected response data according to the test vector.

[0076] S130 , the writing module transmits the test stimulus data to the chip through the test access port.

[0077] The writing module may transmit the test stimulus data to the input end of the test access port through the parallel-to-serial conversion module.

[0078] S140: The reading module collects the reading data fed back by the chip through the test access port.

[0079] The reading module can read the reading data fed back by the chip from the output end of the test access port through the serial-to-parallel conversion module.

[0080] S150, the comparison output module obtains an error signal according to the read data and the expected response data and outputs it.

[0081] Among them, there are many ways for the comparison output module to output error signals, which can be set according to needs in actual applications. For example, when the chip needs to process multiple test vectors, the comparison output module can transmit the identification signal representing the correct or incorrect result to the main control device each time; or, when the result is correct, no signal is output until an incorrect result occurs or the test is completed; or, the result corresponding to each test vector is stored, and after the test is completed, the number of correct and incorrect results and their corresponding instruction positions are output together. In short, the comparison between the read data and the expected response data is completed inside the chip, and the interface conversion circuit only outputs an error signal that identifies the test result.

[0082] Optionally, in some test processes, only some bits of the data fed back by the chip are concerned with whether they are correct, so it is not necessary to judge every bit of the read data. In order to simplify the comparison process, the test method further includes:

[0083] The data module obtains mask data according to the test vector;

[0084] The comparison output module first obtains the actual concerned data based on the read data and mask data, and filters the unconcerned data; then compares the actual concerned data with the expected response data to determine whether the read data fed back by the chip is correct. Among them, the format of the expected response data parsed by the data module based on the test vector corresponds to the format of the actual concerned data.

[0085] Optionally, when it is necessary to locate the problem in the chip during the test process, the test method may further include: the data module obtains a test instruction according to the test vector;

[0086] The control module controls the chip test to be in debugging mode according to the test instruction;

[0087] The data selection module reads data from the reading module under the control of the control module, and outputs the read data as a test result.

[0088] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An interface conversion circuit, placed inside a chip under test, for chip testing, characterized in that: include: A data module, comprising an input end, a first output end and a second output end; the input end of the data module is used to connect to an external main control device; The data module is used to obtain test stimulus data and expected response data according to the test vector sent by the main control device; wherein the test vector matches the interface conversion circuit; A write module, comprising an input end and an output end, wherein the input end of the write module is connected to the first output end of the data module, and the output end of the write module is connected to the input end of the test access port of the chip under test, so as to output the test stimulus data to the chip under test; A reading module, comprising an input end and an output end; the input end of the reading module is connected to the output end of the test access port of the chip under test; the reading module is used to collect the reading data fed back by the chip under test; A comparison output module, comprising a first input terminal, a second input terminal and an output terminal; the first input terminal of the comparison output module is connected to the second output terminal of the data module, and the second input terminal of the comparison output module is connected to the output terminal of the reading module; the comparison output module is used to obtain an error signal according to the read data and the expected response data, and output it through the output terminal; Wherein, the data module includes: An instruction decoding unit, comprising an input end, a first output end, and a second output end; the input end of the instruction decoding unit is the input end of the data module, the first output end of the instruction decoding unit is the first output end of the data module, and the second output end of the instruction decoding unit is the second output end of the data module; The instruction decoding unit is configured with an instruction set, and the instruction decoding unit is used to obtain a test instruction according to the test vector, and the test instruction matches a corresponding instruction in the instruction set; the test instruction includes original test data; the original test data includes the test stimulus data and the expected response data; wherein the original test data also includes mask data; Wherein, the test instructions include debugging instructions; The interface conversion circuit also includes: A data selection module; the data selection module is connected to the comparison output module and the reading module respectively; the data selection module outputs a test result; the test result includes the error signal or the read data; A control module; the control module includes a mode control unit; the mode control unit is connected to the data selection module, and is used to control the test result output by the data selection module to be the error signal or the read data; The mode control unit controls the test result output by the data selection module to be the error signal or the read data, including: The mode control unit controls the chip test to be in debug mode or normal mode under the control of the debug instruction; In the debugging mode, after the reading module reads the data fed back by the chip under test each time, the data selection module returns the data to the main control device; or stops at a specific test vector and returns the read data to the main control device; In the normal mode, the mode control unit controls the data selection module to read and output the error signal in the comparison output module; The interface conversion circuit also includes: A parallel-to-serial conversion module, the parallel-to-serial conversion module is connected between the writing module and the test access port of the chip under test, so as to input the test stimulus data from the input end of the test access port of the chip under test to the chip under test; A serial-to-parallel conversion module is connected between the read module and the test access port of the chip under test, and after the read data fed back by the chip under test is output from the output end of the test access port of the chip under test, the serial-to-parallel conversion module converts the read data fed back by the chip under test into parallel data so as to be read by the read module.

2. The interface conversion circuit according to claim 1, characterized in that: The data module further includes a third output terminal, and the data module is further used to obtain mask data according to the test vector sent by the main control device; the comparison output module further includes a third input terminal, and the third input terminal of the comparison output module is connected to the third output terminal of the data module; The comparison output module includes: an AND unit, an XOR unit and an error register; The AND unit comprises a first input terminal, a second input terminal and an output terminal; the first input terminal of the AND unit is connected to the third output terminal of the data module; the second input terminal of the AND unit is connected to the output terminal of the reading module; the AND unit is used to obtain the actual concerned data according to the mask data and the read data, and filter the irrelevant data; The XOR unit comprises a first input terminal, a second input terminal and an output terminal; the first input terminal of the XOR unit is connected to the second output terminal of the data module; the second input terminal of the XOR unit is connected to the output terminal of the AND unit; the XOR unit is used to obtain a comparison result according to the actual concerned data and the expected response data; The error register includes a first input end and a first output end, the first input end of the error register is connected to the output end of the XOR unit, and the first output end of the error register is the output end of the comparison output module; the error register is used to obtain the error signal according to the comparison result, and store and output the error signal.

3. The interface conversion circuit according to claim 2, characterized in that: The error register also includes a second output terminal; The comparison output module also includes an adder; The adder comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the adder is connected to the output terminal of the XOR unit; the second input terminal of the adder is connected to the second output terminal of the error register; and the output terminal of the adder is connected to the first input terminal of the error register; The adder is used to increase the error signal by one when the comparison result indicates that the actual concerned data is wrong, and transmit it to the error register; The error signal includes the accumulated number of errors in the comparison result.

4. The interface conversion circuit according to claim 1, characterized in that: Also includes: Control module; the control module includes a sequence control unit; the sequence control unit is connected to the instruction decoding unit and the writing module respectively; the sequence control unit is used to control the test sequence.

5. The interface conversion circuit according to claim 1, characterized in that: Also includes: Control module; The control module includes an enabling control unit; the enabling control unit is connected to the writing module and the reading module, and is used to control the start or end of a test.

6. A chip, characterized in that: include: An interface conversion circuit as described in any one of claims 1 to 5.

7. A chip testing system, characterized in that: include: A main control device and a chip as claimed in claim 6; The main control device is connected to the chip; the main control device is used to transmit the test vector to the chip.

8. A chip testing method for a chip as claimed in claim 6, characterized in that: include: The main control device transmits the test vector matching the interface conversion circuit in the chip to the interface conversion circuit in the chip; The data module receives the test vector and obtains test stimulus data and expected response data according to the test vector; The writing module transmits the test stimulus data to the chip through the test access port; The reading module collects the reading data fed back by the chip through the test access port; The comparison output module obtains and outputs an error signal according to the read data and the expected response data.

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