Chip aging test circuit and chip aging test system

Abstract

The present application discloses a chip aging test circuit, including a power module, a processing module and at least one test module electrically connected to the processing module, the processing module having a test signal interface group and a signal output interface for connecting to a host computer; the test module includes a chip test socket for placing a chip to be tested, the power supply input pin of the chip test socket is electrically connected to the power module, the signal output pin of the chip test socket is electrically connected to a test signal pin of the test signal interface group, and the chip test signal of the chip to be tested on the chip test socket is output to the processing module; the processing module analyzes the chip test signals output by each chip test socket received by the test signal interface group, and sends the test results obtained by the analysis to the host computer from the signal output interface. The present application also discloses a chip aging test system. The present application improves the efficiency and accuracy of chip testing.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip aging test circuit and a chip aging test system. Background Art

[0002] Since EMMC chips have the problem of newly added bad blocks, EMMC chips need to be tested for aging before leaving the factory. At present, the aging test method for EMMC chips is: install multiple metal sockets on a aging board, start aging after the motherboard is powered on, and judge the pass and fail of the chip test by manually observing the flashing of the LED light. Using this kind of motherboard testing method, the test efficiency is low and it is easy to make misjudgments, which affects the accuracy of the test. Summary of the invention

[0003] The present application provides a chip aging test circuit and a chip aging test system, which improve the efficiency and accuracy of the chip aging test.

[0004] The present application proposes a chip aging test circuit, comprising a power module, a processing module and at least one test module electrically connected to the processing module, wherein the processing module has a test signal interface group and a signal output interface for connecting to a host computer;

[0005] The test module comprises a chip test seat for placing the chip to be tested, a power supply input pin of the chip test seat is electrically connected to the power supply module, a signal output pin of the chip test seat is electrically connected to a test signal pin of the test signal interface group, and a chip test signal of the chip to be tested on the chip test seat is output to the processing module;

[0006] The processing module analyzes the chip test signals output by each of the chip test sockets received by the test signal interface group, and sends the test results obtained by the analysis to the host computer through the signal output interface.

[0007] Preferably, the test module further comprises a switch unit, and the processing module further comprises a detection signal interface group and a switch enable interface group;

[0008] The input end of the switch unit is electrically connected to the power module, the output end of the switch unit is electrically connected to the power input pin of the chip test socket, and the enable end of the switch unit is electrically connected to a switch enable pin of the switch enable interface group; the chip test socket has a placement status pin for feeding back the placement status of the chip to be tested, and the placement status pin is electrically connected to a detection signal pin of the detection signal interface group;

[0009] The processing module controls the on-off of the switch unit connected to each chip test socket according to the level signal fed back by the placement status pin of each chip test socket.

[0010] Preferably, the placement status pin of the chip test socket is pulled up to a high level; when the chip to be tested is correctly placed, the potential of the placement status pin of the chip test socket is pulled down by the chip to be tested, and the processing module outputs a first level signal to the enable end of the corresponding switch unit according to the low level fed back by the placement status pin of the chip test socket, so that the corresponding switch unit is turned on; when the chip to be tested is reversed, the placement status pin of the chip test socket maintains a high level, and the processing module outputs a second level signal to the enable end of the corresponding switch unit according to the high level fed back by the placement status pin of the chip test socket, so that the corresponding switch unit is disconnected; the first level signal is opposite to the second level signal in potential.

[0011] Preferably, the test module further includes a first buffer and a second buffer, the placement status pin is electrically connected to the detection signal pin via the first buffer, and the signal output pin is electrically connected to the test signal pin via the second buffer.

[0012] Preferably, the processing module further comprises a buffer enable interface group, and the enable end of the first buffer is electrically connected to a buffer enable pin of the buffer enable interface group.

[0013] Preferably, the test module also includes a step-down unit, and the output end of the switch unit is electrically connected to the power supply input pin of the chip test socket via the step-down unit; the step-down unit steps down the voltage output by the output end of the switch unit, and outputs it to the power supply input pin of the chip test socket to power the chip to be tested placed on the chip test socket.

[0014] Preferably, the chip test socket has a first power supply input pin and a second power supply input pin, the step-down unit includes a first step-down sub-unit and a second step-down sub-unit, the output end of the switch unit is electrically connected to the first power supply input pin via the first step-down sub-unit, and the output end of the switch unit is also electrically connected to the second power supply input pin via the second step-down sub-unit; the first step-down sub-unit steps down the voltage output by the output end of the switch unit to a first power supply voltage, and the second step-down sub-unit steps down the voltage output by the output end of the switch unit to a second power supply voltage.

[0015] Preferably, the test module further comprises an LED unit, wherein the LED unit is electrically connected to the signal output pin of the chip test socket and is used for displaying the change of the chip test signal output by the signal output pin through the LED.

[0016] Preferably, it also includes a signal conversion module, which is connected to the signal output interface and is used to convert the TTL signal output by the signal output interface into an RS232 signal and send it to the host computer.

[0017] The present application also proposes a chip aging test system, comprising a host computer and a chip aging test circuit, wherein the chip aging test circuit comprises a power module, a processing module and at least one test module electrically connected to the processing module, wherein the processing module has a test signal interface group and a signal output interface connected to the host computer;

[0018] The test module comprises a chip test seat for placing the chip to be tested, a power supply input pin of the chip test seat is electrically connected to the power supply module, a signal output pin of the chip test seat is electrically connected to a test signal pin of the test signal interface group, and a chip test signal of the chip to be tested on the chip test seat is output to the processing module;

[0019] The processing module analyzes the chip test signals output by each of the chip test sockets received by the test signal interface group, and sends the test results obtained by the analysis to the host computer through the signal output interface.

[0020] The technical solution of the present application adopts the chip test signal of the chip to be tested on the chip test socket of each test module to be output to the processing module for analysis and processing. The processing module analyzes and determines whether the test of the chip to be tested on the chip test socket of each test module is qualified, and sends the analysis result to the host computer for display. Therefore, the user can clearly and intuitively know which chips to be tested on the chip test socket are unqualified through the host computer, without having to judge the test results of each chip through manual observation one by one, which greatly improves the chip testing efficiency and avoids the occurrence of misjudgment caused by manual observation and judgment, thereby ensuring the accuracy of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the circuit module structure of an embodiment of a chip aging test circuit of the present application;

[0022] Figure 2 This is a schematic diagram of the circuit module structure of the second embodiment of the chip aging test circuit of the present application;

[0023] Figure 3 This is a schematic diagram of the circuit module structure of the third embodiment of the chip aging test circuit of the present application;

[0024] Figure 4 This is a schematic diagram of the circuit module structure of the fourth embodiment of the chip aging test circuit of the present application;

[0025] Figure 5This is a schematic diagram of the circuit module structure of the fifth embodiment of the chip aging test circuit of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0027] The present application provides a chip aging test circuit, which is mainly used for aging test of chips, for example, aging test of EMMC (Embedded Multi Media Card) chips before leaving the factory.

[0028] like Figure 1 As shown, the chip aging test circuit of this embodiment includes a power module 10, a processing module 20 and at least one test module 30 electrically connected to the processing module 20. The processing module 20 has a test signal interface group 21 and a signal output interface 22 for connecting to a host computer. The test module 30 of this embodiment can be one or more. Figure 1 In the example, multiple test modules 30 are taken as an example.

[0029] The test module 30 includes a chip test socket 31 for placing the chip to be tested, the power input pin V of the chip test socket 31 is electrically connected to the power module 10, and the signal output pin A of the chip test socket 31 is electrically connected to a test signal pin of the test signal interface group 21, and the chip test signal of the chip to be tested on the chip test socket 31 is output to the processing module 20; when the chip to be tested is placed on the chip test socket 31, the power input pin V of the chip test socket 31 connected to the power module 10 is used to power the chip to be tested, and the internal aging software automatically runs when the chip to be tested is powered on, and the chip test signal of the chip to be tested is output to the processing module 20 via the signal output pin A of the chip test socket 31. In this embodiment, the test signal interface group 21 of the processing module 20 includes one or more test signal pins, and each test signal pin is electrically connected to the signal output pin A of a chip test socket 31.

[0030] The processing module 20 analyzes the chip test signals output by each chip test socket 31 received by the test signal interface group 21, and sends the test results obtained by the analysis to the host computer from the signal output interface 22. The processing module 20 analyzes the chip test signals output by each chip test socket 31 to determine whether the test of the chip to be tested on each chip test socket 31 is qualified (i.e., the test result), and sends the qualified status of the chip to be tested on each chip test socket 31 to the host computer for display.

[0031] The chip aging test circuit of this embodiment adopts the chip test signal of the chip to be tested on the chip test socket 31 of each test module 30 to be output to the processing module 20 for analysis and processing. The processing module 20 analyzes whether the test of the chip to be tested on the chip test socket 31 of each test module 30 is qualified, and sends the analysis result to the host computer for display, so that the user can clearly and intuitively know which chips to be tested on the chip test socket 31 are unqualified through the host computer, without having to judge the test results of each chip through manual observation one by one, which greatly improves the chip testing efficiency and avoids the occurrence of misjudgment caused by manual observation and judgment, thereby ensuring the accuracy of the test.

[0032] Furthermore, the chip aging test circuit of this embodiment also includes a signal conversion module 40, which is connected to the signal output interface 22 and is used to convert the TTL signal output by the signal output interface 22 into an RS232 signal and send it to the host computer.

[0033] Furthermore, if Figure 2 As shown, Figure 2Two test modules 30 are taken as an example. Of course, in other embodiments, the test module 30 can also be one or more. The test module 30 of this embodiment also includes a switch unit 32, and the processing module 20 also has a detection signal interface group 23 and a switch enable interface group 24. The input end of the switch unit 32 is electrically connected to the power module 10, and the output end of the switch unit 32 is electrically connected to the power input pin V of the chip test socket 31, that is, the power input pin V of the chip test socket 31 is connected to the power module 10 via the switch unit 32; the enable end E of the switch unit 32 is electrically connected to a switch enable pin of the switch enable interface group 24. The chip test socket 31 has a placement status pin B for feedback of the placement status of the chip to be tested, and the placement status pin B is electrically connected to a detection signal pin of the detection signal interface group 23. The chip test socket 31 outputs level signals with opposite potentials when the chip to be tested is placed correctly or reversely. In this embodiment, the switch enable interface group 24 of the processing module 20 includes one or more switch enable pins, and the detection signal interface group 23 of the processing module 20 includes one or more detection signal pins, each switch enable pin is electrically connected to the enable end E of the switch unit 32 of a test module 30, and each detection signal pin is electrically connected to the placement state pin B of a chip test socket 31. The processing module 20 controls the on and off of the switch unit 32 connected to each chip test socket 31 according to the level signal fed back by the placement state pin B of each chip test socket 31.

[0034] In the chip aging test circuit of the present embodiment, the placement status pin B of the chip test socket 31 of each test module 30 corresponds to a detection signal pin of the detection signal interface group 23 electrically connected to the processing module 20, so that the processing module 20 can determine whether there is a chip to be tested that is placed upside down according to the level signal fed back by the placement status pin B of each chip test socket 31 before the chip to be tested of each test module 30 is powered on for testing, and control the switch unit 32 connected to the chip test socket 31 where the chip to be tested is placed correctly to be turned on, and control the switch unit 32 connected to the chip test socket 31 where the chip to be tested is placed upside down to be turned off, so as to ensure that each correctly placed chip to be tested can be powered on for testing normally, and to cut off the power of the chip test socket 31 where the chip to be tested is placed upside down, so as to avoid damage to the chip to be tested or the overall circuit due to powering on of the chip to be tested being placed upside down, and to avoid the situation where the chip to be tested that is placed upside down is mistakenly judged as a substandard product.

[0035] Furthermore, in this embodiment, the placement state pin B of the chip test socket 31 is pulled up to a high level; when the chip to be tested is correctly placed, the potential of the placement state pin B of the chip test socket 31 is pulled down by the chip to be tested, and the processing module 20 outputs a first level signal to the enable end E of the corresponding switch unit 32 according to the low level fed back by the placement state pin B of the chip test socket 31, so that the corresponding switch unit 32 is turned on; when the chip to be tested is reversed, the placement state pin B of the chip test socket 31 maintains a high level, and the processing module 20 outputs a second level signal to the enable end E of the corresponding switch unit 32 according to the high level fed back by the placement state pin B of the chip test socket 31, so that the corresponding switch unit 32 is turned off. Among them, the first level signal is opposite to the second level signal potential; for example, when the switch unit 32 is turned on by high level enable, the first level signal is a high level, and the second level signal is a low level.

[0036] Furthermore, if Figure 3 As shown, in this embodiment, the test module 30 also includes a first buffer 33 and a second buffer 34, the placement state pin B is electrically connected to the detection signal pin via the first buffer 33, and the signal output pin A is electrically connected to the test signal pin via the second buffer 34. In this embodiment, the placement state pin B of the chip test socket 31 is isolated from the detection signal pin of the processing module 20 by the first buffer 33, and the signal output pin A of the chip test socket 31 is isolated from the test signal pin of the processing module 20 by the second buffer 34, thereby preventing abnormal conditions such as static electricity and overcurrent on the test module 30 from affecting the processing module 20, and effectively realizing the protection of the processing module 20. In this embodiment, both the first buffer 33 and the second buffer 34 can use 16-input and 16-output buffers.

[0037] Furthermore, the processing module 20 of the present embodiment also has a buffer enable interface group 25, and the enable end of the first buffer 33 is electrically connected to a buffer enable pin of the buffer enable interface group 25. The buffer enable interface group 25 of the processing module 20 includes one or more buffer enable pins, each of which is electrically connected to the enable end of a first buffer 33. The first buffer 33 is normally in a high impedance state. The processing module 20 simultaneously sends a low-level enable signal to the first buffer 33 of each test module 30 through each buffer enable pin of the buffer enable interface group 25, so that the first buffer 33 of each test module 30 is turned on at the same time. The processing module 20 simultaneously receives the level signal fed back by the placement state pin B of each chip test socket 31, so as to control the conduction state of the switch unit 32 of each test module 30 according to the level signal fed back by each chip test socket 31, thereby testing the chips to be tested of each chip test socket 31 at the same time to achieve unified timing control.

[0038] Furthermore, if Figure 4As shown, in this embodiment, the test module 30 also includes a step-down unit 35, and the output end of the switch unit 32 is electrically connected to the power supply input pin V of the chip test socket 31 through the step-down unit 35; the step-down unit 35 steps down the voltage output from the output end of the switch unit 32, and outputs it to the power supply input pin V of the chip test socket 31, so as to supply power to the chip to be tested placed on the chip test socket 31. The voltage provided by the power supply module 10 is usually higher than the voltage required for powering on the chip. Therefore, the step-down unit 35 is used to step down the voltage output by the power supply module 10 to the power supply voltage required by the chip to be tested, and then outputs it to the power supply input pin V of the chip test socket 31, so as to supply power to the chip to be tested on the chip test socket 31.

[0039] Furthermore, if Figure 5 As shown, the chip test socket 31 of this embodiment has a first power supply input pin V1 and a second power supply input pin V2, the step-down unit 35 includes a first step-down sub-unit 351 and a second step-down sub-unit 352, the output end of the switch unit 32 is electrically connected to the first power supply input pin V1 via the first step-down sub-unit 351, and the output end of the switch unit 32 is also electrically connected to the second power supply input pin V2 via the second step-down sub-unit 352; the first step-down sub-unit 351 steps down the voltage output from the output end of the switch unit 32 to the first power supply voltage, and the second step-down sub-unit 352 steps down the voltage output from the output end of the switch unit 32 to the second power supply voltage. The chip under test usually needs two power supply voltages of different sizes when it is powered on (for example, the two power supply voltages required by the EMMC chip are 3.3v and 1.8v respectively). The first power supply input pin V1 and the second power supply input pin V2 of the chip test socket 31 respectively provide two power supply voltages of different sizes to the chip under test, and the voltage provided by the power module 10 is respectively stepped down by the first step-down subunit 351 and the second step-down subunit 352 to obtain the two power supply voltages required by the chip under test. In this embodiment, the first step-down subunit 351 and the second step-down subunit 352 can use low-voltage differential linear regulators, and of course, other step-down circuits or devices can also be used.

[0040] Furthermore, in this embodiment, the test module 30 also includes an LED unit, which is electrically connected to the signal output pin A of the chip test socket 31, and is used to display the change of the chip test signal output by the signal output pin A through the LED. The chip test signal output by the signal output pin A of the chip test socket 31 is reflected by the LED light of the LED unit flashing to show the pulse change, and the user can also manually judge whether the test of the chip to be tested is qualified according to the flashing law of the LED light.

[0041] In the present application, the processing module 20 may use an FPGA chip. The test signal interface group 21 is composed of the first part (e.g., 128) I / O pins of the FPGA chip, and each I / O pin of the first part is a test signal pin; the detection signal interface group 23 is composed of the second part (e.g., 128) I / O pins of the FPGA chip, and each I / O pin of the second part is a detection signal pin; the switch enable interface group 24 is composed of the third part (e.g., 128) I / O pins of the FPGA chip, and each I / O pin of the third part is a switch enable pin; the buffer enable interface group 25 is composed of the fourth part (e.g., 128) I / O pins of the FPGA chip, and each I / O pin of the third part is a buffer enable pin. The switch unit 32 may use an IC-TPS22919 switch chip with short circuit protection and overheat protection functions.

[0042] The present application also provides a chip aging test system, including a host computer and a chip aging test circuit. The specific structure of the chip aging test circuit refers to the above embodiment, wherein the signal output interface of the chip aging test circuit is connected to the host computer. Since the chip aging test system adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here one by one.

[0043] The above description is only a partial or preferred embodiment of the present application. Neither the text nor the drawings can limit the scope of protection of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the overall concept of the present application, or direct / indirect application in other related technical fields are included in the scope of protection of the present application.

Claims

1. A chip aging test circuit, used for aging test of EMMC chip, characterized in that: It includes a power supply module, a processing module and at least one test module electrically connected to the processing module, wherein the processing module has a test signal interface group and a signal output interface for connecting to a host computer; The test module comprises a chip test seat for placing the chip to be tested, a power supply input pin of the chip test seat is electrically connected to the power supply module, a signal output pin of the chip test seat is electrically connected to a test signal pin of the test signal interface group, and a chip test signal of the chip to be tested on the chip test seat is output to the processing module; The processing module analyzes the chip test signals output by each chip test socket received by the test signal interface group, and sends the test results obtained by the analysis to the host computer from the signal output interface; The test module further comprises a switch unit, and the processing module further comprises a detection signal interface group and a switch enable interface group; The input end of the switch unit is electrically connected to the power module, the output end of the switch unit is electrically connected to the power input pin of the chip test socket, and the enable end of the switch unit is electrically connected to a switch enable pin of the switch enable interface group; the chip test socket has a placement status pin for feeding back the placement status of the chip to be tested, and the placement status pin is electrically connected to a detection signal pin of the detection signal interface group; The processing module controls the on-off of the switch unit connected to each chip test socket according to the level signal fed back by the placement status pin of each chip test socket; The placement status pin of the chip test socket is pulled up to a high level; when the chip to be tested is correctly placed, the potential of the placement status pin of the chip test socket is pulled down by the chip to be tested, and the processing module outputs a first level signal to the enable end of the corresponding switch unit according to the low level fed back by the placement status pin of the chip test socket, so that the corresponding switch unit is turned on; when the chip to be tested is reversed, the placement status pin of the chip test socket maintains a high level, and the processing module outputs a second level signal to the enable end of the corresponding switch unit according to the high level fed back by the placement status pin of the chip test socket, so that the corresponding switch unit is turned off; the first level signal is opposite to the second level signal in potential; The test module further includes a first buffer and a second buffer, the placement status pin is electrically connected to the detection signal pin via the first buffer, and the signal output pin is electrically connected to the test signal pin via the second buffer.

2. The chip aging test circuit according to claim 1, characterized in that: The processing module further comprises a buffer enable interface group, and an enable end of the first buffer is electrically connected to a buffer enable pin of the buffer enable interface group.

3. The chip aging test circuit according to claim 1, characterized in that: The test module also includes a step-down unit, and the output end of the switch unit is electrically connected to the power supply input pin of the chip test socket via the step-down unit; the step-down unit steps down the voltage output by the output end of the switch unit, and outputs it to the power supply input pin of the chip test socket to supply power to the chip to be tested placed on the chip test socket.

4. The chip aging test circuit according to claim 3, characterized in that: The chip test socket has a first power supply input pin and a second power supply input pin, the step-down unit includes a first step-down sub-unit and a second step-down sub-unit, the output end of the switch unit is electrically connected to the first power supply input pin via the first step-down sub-unit, and the output end of the switch unit is also electrically connected to the second power supply input pin via the second step-down sub-unit; the first step-down sub-unit steps down the voltage output by the output end of the switch unit to a first power supply voltage, and the second step-down sub-unit steps down the voltage output by the output end of the switch unit to a second power supply voltage.

5. The chip aging test circuit according to claim 1, characterized in that: The test module also includes an LED unit, which is electrically connected to the signal output pin of the chip test socket and is used to display the change of the chip test signal output by the signal output pin through the LED.

6. The chip aging test circuit according to claim 1, characterized in that: It also includes a signal conversion module, which is connected to the signal output interface and is used to convert the TTL signal output by the signal output interface into an RS232 signal and send it to the host computer.

7. A chip aging test system, characterized in that: It comprises a host computer and the chip aging test circuit according to any one of claims 1 to 6, and the signal output interface is connected to the host computer.

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