Semiconductor package and method of forming the same

Abstract

The semiconductor package includes: a substrate; a first dielectric layer located above the substrate; a first bonding pad and a second bonding pad located above the first dielectric layer, the first bonding pad having a first sidewall facing the second bonding pad; a second dielectric layer located above the first bonding pad and the second bonding pad; and an opening passing through the second dielectric layer and extending from the first bonding pad to the second bonding pad, the opening including a first region located above the first bonding pad and exposing the first bonding pad, wherein in a top view, the opening exposes a first segment of the first sidewall disposed between a first edge and a second edge of the first region intersecting the first sidewall, wherein the first segment of the first sidewall is located between the second segment and the third segment of the first sidewall, and the second segment is covered by the second dielectric layer. Embodiments of the present application also relate to a method of forming a semiconductor package.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor packages and methods of forming the same. Background Art

[0002] As an example, semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras and other electronic devices. Semiconductor devices are usually manufactured by sequentially depositing insulating layers or dielectric layers, conductive layers and semiconductor material layers over a semiconductor substrate and using photolithography to pattern each material layer to form circuit components and elements thereon. Tens or hundreds of integrated circuits are usually manufactured on a single semiconductor wafer. Individual dies are separated by sawing the integrated circuit along the scribe line. For example, the individual dies are then packaged separately in a multi-chip module or other type of package.

[0003] The semiconductor industry continues to increase the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. As feature sizes continue to shrink in advanced semiconductor manufacturing nodes, new challenges emerge that must be addressed. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor package, comprising: a substrate; a first dielectric layer located above the substrate; a first bonding pad and a second bonding pad arranged above the first dielectric layer, the first bonding pad having a first sidewall facing the second bonding pad; a second dielectric layer located above the first bonding pad, the second bonding pad and the first dielectric layer; and an opening located in the second dielectric layer, wherein, in a top view, the opening comprises: a first region located above a first portion of the first bonding pad and exposing a first portion of the first bonding pad; a second region located above a second portion of the second bonding pad and exposing a second portion of the second bonding pad; and a third region located between the first region and the second region, the third region exposing a portion of the first dielectric layer, wherein a third length of the third region measured along a first direction parallel to the first sidewall of the first bonding pad is greater than a first length of the first region measured along the first direction, wherein a first portion of the first sidewall of the first bonding pad is exposed by the opening, and a second portion of the first sidewall is covered by the second dielectric layer.

[0005] Some other embodiments of the present application provide a semiconductor package, comprising: a substrate; a first dielectric layer located above the substrate; a first bonding pad and a second bonding pad located above the first dielectric layer, wherein the first bonding pad has a first sidewall facing the second bonding pad; a second dielectric layer located above the first bonding pad and the second bonding pad; and an opening passing through the second dielectric layer, wherein the opening extends from the first bonding pad to the second bonding pad, wherein the opening comprises a first region located above the first bonding pad and exposing the first bonding pad, wherein in a top view, the opening exposes a first segment of the first sidewall of the first bonding pad, the first segment of the first sidewall is located between a first edge of the first region and a second edge of the first region, the first edge and the second edge intersecting with the first sidewall, wherein the first segment of the first sidewall is located between the second segment of the first sidewall and a third segment of the first sidewall, wherein the second segment of the first sidewall is covered by the second dielectric layer.

[0006] Some other embodiments of the present application provide a method for forming a semiconductor package, the method comprising: forming a first dielectric layer over a substrate; forming a first bonding pad and a second bonding pad over the first dielectric layer; forming a second dielectric layer over the first bonding pad, the second bonding pad and the first dielectric layer; and forming an opening in the second dielectric layer to partially expose the first bonding pad and the second bonding pad, wherein the opening is formed to include: a first region located over the first bonding pad and partially exposing the first bonding pad; a second region located over the second bonding pad and partially exposing the second bonding pad; and a third region located between the first region and the second region, the third region exposing a portion of the first dielectric layer, wherein the opening exposes a first portion of a first side wall of the first bonding pad facing the second bonding pad, and a second portion of the first side wall is covered by the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 A top view of a package substrate in an embodiment is shown.

[0009] Figures 2 to 4 , FIG. 5A to FIG. 5G , Fig. 6A , Figure 6B , Figure 7 and Figure 8 Various views of a semiconductor package at various stages of fabrication in an embodiment are shown.

[0010] Fig. 9 A cross-sectional view of a semiconductor package according to an embodiment is shown.

[0011] Fig.10 A cross-sectional view of a semiconductor package according to another embodiment is shown.

[0012] Fig.11 A cross-sectional view of a semiconductor package according to another embodiment is shown.

[0013] Fig.12 A cross-sectional view of a semiconductor package according to another embodiment is shown.

[0014] Fig.13 A cross-sectional view of a semiconductor package according to yet another embodiment is shown.

[0015] Fig.14 A flow chart of a method of forming a semiconductor package in some embodiments is shown. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0017] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Throughout the discussion herein, unless otherwise indicated, the same or similar reference numerals in different figures refer to the same or similar components formed by the same or similar processes using the same or similar materials.

[0018] In some embodiments, a semiconductor package substrate includes a substrate, a first dielectric layer located above the substrate, and a first bonding pad and a second bonding pad located above the first dielectric layer. The semiconductor package substrate also includes a second dielectric layer located above the first bonding pad, the second bonding pad, and the first dielectric layer, and an opening in the second dielectric layer that partially exposes the first bonding pad and the second bonding pad. In an embodiment, the first bonding pad has a first sidewall facing the second bonding pad, a first portion of the first sidewall of the first bonding pad is exposed by the opening, and a second portion of the first sidewall is covered by the second dielectric layer. By covering the second portion of the first sidewall with the second dielectric layer, defects caused by bridging problems are reduced or avoided.

[0019] Figure 1 A top view of a package substrate 50 in an embodiment is shown. The package substrate 50 may also be a semiconductor package substrate, and may be used to package semiconductor dies to form a semiconductor package. For example, in semiconductor manufacturing, a plurality of semiconductor dies (also referred to as dies or integrated circuit dies (IC dies)) are manufactured on a semiconductor wafer. The semiconductor wafer is then segmented to form a plurality of individual dies. After segmentation, the dies are tested, and a known good die (KGD) is attached to the package substrate to form a semiconductor package. The semiconductor package may include a metal, plastic, glass, or ceramic sleeve containing one or more semiconductor dies. The semiconductor package provides a device (such as a printed circuit board (PCB)) that electrically connects the die inside the semiconductor package to the external environment through the leads (such as pads, bonding pads, solder balls, or pins) of the semiconductor package. The semiconductor package may also provide protection of the die from adverse environmental factors (such as mechanical shock, chemical contamination, and exposure).

[0020] like Figure 1 As shown, the package substrate 50 includes a substrate 101 (eg, a dielectric core), conductive lines 113 (eg, copper wires), and conductive pads 115 (eg, copper pads) located on a surface of the substrate 101 . Figure 1 Also shown is an area 117 for attaching a semiconductor die to package substrate 50. In addition, along the periphery of package substrate 50 (e.g., Figure 1 ), a plurality of bonding pads 105 are formed over a dielectric layer 103 (e.g., solder resist) formed over the substrate 101. In some embodiments, the bonding pads 105 are used to attach (e.g., bond) a surface mount device (SMD) to the package substrate 50. For example, in the region 119 of the package substrate 50, two bonding pads 105 are formed, which can be used to bond a two-terminal SMD device, such as a resistor, a capacitor, etc.

[0021] Figures 2 to 4 , FIG. 5A to FIG. 5G , Fig. 6A , Figure 6B , Figure 7 and Figure 8 Various views (eg, cross-sectional views, top views) of the semiconductor package 100 at various stages of manufacture in an embodiment are shown. In particular, Figures 2 to 4 and FIG. 5A to FIG. 5G Processing steps of a packaging substrate are shown, and subsequent figures show devices (eg, SMDs and / or semiconductor dies) being bonded to the packaging substrate to form a semiconductor package 100 . Figures 2 to 4 , Figure 5A , Figure 5B and Fig. 6A A top view of semiconductor package 100 is shown. FIG. 5C to FIG. 5F The Figure 5A 2 is a cross-sectional view of the semiconductor package 100 at sections AA′, BB′, CC′, and DD′. Figure 5D Shows Figure 5A An enlarged view of area 150 in FIG. Figure 6B , Figure 7 and Figure 8 Shown along Fig. 6A FIG. 1 is a cross-sectional view of the semiconductor package 100 at the section EE' in FIG. 1 . It should be noted that for simplicity, Figures 2 to 4 , FIG. 5A to FIG. 5G , Fig. 6A , Figure 6B , Figure 7 and Figure 8 Only a portion of the semiconductor package 100 is shown, and not all components of the semiconductor package 100 are shown in the figure. For example, Figures 2 to 4 , FIG. 5A to FIG. 5G , Fig. 6A , Figure 6B , Figure 7 and Figure 8 The portion of the package substrate shown in FIG. 1 may correspond to Figure 1 The portion of the package substrate 50 in the region 119 .

[0022] refer to Figure 2 , on the substrate 101( Figure 2 Not shown, but in FIG. 5C to FIG. 5F1 ). A dielectric layer 103 is formed on the substrate 101 (shown in FIG). The substrate 101 may be or include a dielectric core formed of a dielectric material such as a resin or glass fiber. For example, the dielectric core may include bismaleimide triazine (BT) resin, FR-4 (a composite material composed of glass fiber woven cloth and a flame retardant epoxy resin adhesive), ceramic, glass, plastic, tape, film, or other supporting material. In some embodiments, conductive components (such as copper wires and / or copper pads) are formed on opposite sides of the dielectric core and may be used as a redistribution layer to reroute electrical signals from a first location on the substrate 101 to a second location on the substrate 101. Conductive vias are formed to extend through the dielectric core and electrically coupled to conductive components of the redistribution layer. The dielectric layer 103 may be a suitable dielectric material, such as solder resist, Ajinomoto accumulated film (ABF), PREPREG, polyimide, etc., formed by a suitable formation method such as physical vapor deposition (PVD), chemical vapor deposition (CVD), spin coating, lamination, etc. A planarization process such as chemical and mechanical planarization (CMP) may be performed as a next step to achieve a flush upper surface for the dielectric layer 103 .

[0023] Next, in Figure 2 In the present invention, a bonding pad 105 and a conductive line 107 are formed above the dielectric layer 103. The bonding pad 105 and the conductive line 107 are formed of a conductive material such as copper, but other suitable materials such as tungsten, cobalt, gold, alloys thereof, etc. may also be used. In some embodiments, in order to form the bonding pad 105 and the conductive line 107, a seed layer is formed above the dielectric layer 103 (e.g., by PVD or CVD), and then a patterned photoresist layer is formed above the seed layer, wherein the position of the pattern (e.g., opening) of the patterned photoresist layer corresponds to the position of the bonding pad 105 and the conductive line 107. Next, a conductive material such as copper is formed in the opening of the patterned photoresist layer, for example, by a plating process. Next, the patterned photoresist layer is removed, and the portion above the seed layer where no conductive material is formed is removed. In addition to the formation method described above, other methods for forming the bonding pad 105 and the conductive line 107 are also possible and are fully intended to be included within the scope of the present invention.

[0024] exist Figure 3 In the example of , the bonding pad 105 (eg, 105A or 105B) includes a rectangular region of conductive material. The bonding pad 105A has a sidewall 105SA facing the bonding pad 105B, and the bonding pad 105B has a sidewall 105SB facing the bonding pad 105A. Figure 3In the example of , sidewalls 105SA and 105SB are parallel to each other. A distance D2 between sidewalls 105SA and 105SB may be greater than 100 μm and less than about 1000 μm (eg, 100 μm < D2 < 1000 μm). Bonding pads 105A and 105B are horizontally aligned so that Figure 3 The horizontal sidewalls of the bonding pad 105A and the corresponding horizontal sidewalls of the bonding pad 105B are aligned along the same horizontal line.

[0025] The conductive line 107 extends along the sidewall of the bonding pad 105A (or 105B) intersecting the sidewall 105SA (or 105SB), such as in a direction perpendicular to the sidewall 105A / 105B. The distance D1 (e.g., the shortest distance) between the bonding pad 105 and the conductive line 107 is less than about 40 μm (e.g., 0 μm < D1 < 40 μm). It should be noted that the portion of the conductive line 107 disposed laterally between the bonding pads 105 is moved away from the bonding pads 105, thereby forming an obtuse angle α (e.g., 90 degrees < α < 180 degrees) between the segments of the conductive line 107. Figure 3 This pattern of the wire 107 shown can be referred to as having a bevel design. As will be discussed later in the present invention, the bevel design of the wire 107 and the bevel design of the opening 111 formed subsequently help reduce defects caused by bridging (e.g., electrical shorts) in the manufacture of semiconductor packages. In some embodiments, the angle α is 120 degrees or 135 degrees. In some embodiments, the angle α is selected to match the angle θ of the bevel design of the opening 111 (see Figure 5B ).

[0026] Next, in Figure 4 In the embodiment, a dielectric layer 109 is formed over the bonding pad 105, the conductive line 107 and the dielectric layer 103. The dielectric layer 109 may be a suitable dielectric layer, such as solder resist, ABF, PREPREG, polyimide, etc., formed by a suitable formation method such as PVD, CVD, spin coating, lamination, etc. A planarization process such as CMP may be performed next to achieve a flush upper surface for the dielectric layer 109. It should be noted that in Figure 4 The bonding pad 105 and the conductive line 107 are shown in dashed lines because they are Figure 4 Not visible in the top view.

[0027] Next, in Figure 5AIn the process, for example, using photolithography and etching techniques, an opening 111 is formed in the dielectric layer 109 to expose a portion of the bonding pad 105A, a portion of the bonding pad 105B, and a portion of the dielectric layer 103 located between the bonding pads 105A and 105B. For example, a patterned photoresist layer can be formed over the dielectric layer 109, and an etching process (e.g., an anisotropic etching process) is performed in the next step to form the opening 111. The patterned photoresist layer is then removed by a suitable removal process (such as ashing). To avoid confusion, Figure 5B Only the dielectric layer 109 and the opening 111 are shown.

[0028] refer to Figure 5A and Figure 5B , the opening 111 includes a region 111A located above (eg, directly above) the bonding pad 105A, a region 111B located above (eg, directly above) the bonding pad 105B, and a region 111C located between the regions 111A and 111B. Figure 5A and Figure 5B In the example of , the opening 111 extends continuously from the bonding pad 105A to the bonding pad 105B. Each of the regions 111A and 111B has a rectangular shape and is smaller than the area of ​​the corresponding underlying bonding pad 105. Each of the regions 111A and 111B is placed so that all sidewalls except one sidewall of the underlying bonding pad 105 are covered by the dielectric layer 109, and only one sidewall of the underlying bonding pad 105 is exposed by the opening 111. In particular, the opening 111 exposes the sidewall 105SA of the bonding pad 105A (see Figure 3 ), and exposes the sidewall 105SB of the bonding pad 105B (see Figure 3 ).

[0029] like Figure 5B As shown, the length L1 of the region 111C is greater than the length L2 of the region 111A (or 111B). Figure 5A and Figure 5B In the top view of FIG. 111 , the region 111C includes a rectangular region and a trapezoidal region. The trapezoidal region faces the conductive line 107 (see FIG. 111 ). Figure 5A ) protrudes, and therefore, may also be referred to as a protruding portion of region 111C. In the illustrated embodiment, the width W1 of the rectangular region is about the distance D2 between the bonding pads 105 (see Figure 3 ) and may remain substantially constant within the rectangular region. In an embodiment, width W1 is greater than about 100 μm, so that width W1 is large enough for a subsequently formed underfill material (or molding material) to flow into and fill the space between the bonding pads 105. Width W2 measured between the two legs of the trapezoidal region increases as the trapezoidal region (the protruding portion of region 111C) increases toward the conductive line 107 (see FIG. Figure 5A ) is extended and reduced. In some embodiments, width W1 is greater than width W2.

[0030] exist Figure 5B In the embodiment, the angle θ measured between the side wall 111S3 (e.g., the leg of the trapezoidal region) and the side wall 111S4 of the region 111A intersecting the side wall 111S3 is an obtuse angle, for example, greater than 90 degrees and less than 180 degrees, such as 120 degrees or 135 degrees. Since the angle θ is an obtuse angle, the opening 111 is said to have a chamfered design. It should be noted that in Figure 5B In some embodiments, the side wall 111S2 of the rectangular region and the side wall 111S1 of the region 111A intersecting with the side wall 111S2 form a right angle. Figure 5B In the top view of , the opening 111 is symmetrical about the central axis of the opening 111 extending along the L1 direction.

[0031] Reference again Figure 5A , the side wall 105SA of the bonding pad 105A (see Figure 3 The mark in (in) includes a first portion 105S1 (also referred to as a first segment), a second portion 105S2 (also referred to as a second segment), and a third portion 105S3 (also referred to as a third segment). Figure 5A In the top view of FIG. 1 , the first portion 105S1 is disposed between the sidewalls 111S1 and 111S4 of the opening 111. The second portion 105S2 and the third portion 105S3 are disposed on opposite sides of the first portion 105S1. In the discussion herein, the sidewalls of the opening 111 (e.g., 111S1, 111S4) may also be referred to as the edges of the opening.

[0032] It should be noted that a first portion 105S1 of the sidewall of the bonding pad 105A is exposed by the opening 111 (eg, not covered by the dielectric layer 109 ), and a second portion 105S2 of the sidewall of the bonding pad 105A is covered by the dielectric layer 109 . Figure 5C and Figure 5D The cross-sectional views shown (which are respectively through Figure 5A The above description is further illustrated by the cross-sectional views of sections A-A' and BB' in FIG. Figure 5A In the embodiment, the third portion 105S3 of the sidewall of the bonding pad 105 is exposed by the opening 111 .

[0033] Figure 5D Shows Figure 5A An enlarged view of area 150. Figure 5D As shown, the distance D3 measured between the second portion 105S2 of the sidewall of the bonding pad 105A and the sidewall 109S of the dielectric layer 109 increases as the second portion 105S2 moves toward the conductive line 107 (see FIG. Figure 5A) extends and increases. In some embodiments, at the side wall 105SL (eg, the side wall closest to the conductive line 107), Figure 5G A maximum value D3max of the distance D3 measured in the horizontal direction is at least 5 μm (eg, D3max>5 μm).

[0034] In some embodiments, after forming the opening 111, a surface finish layer (such as an electroless nickel electroless palladium immersion gold (ENEPIG) layer) is formed over the exposed surface of the bonding pad 105 (e.g., a copper pad) to protect the bonding pad from oxidation and improve the solderability of the bonding pad 105. During the etching process of forming the opening 111, undesirable undercutting of the dielectric layer 109 may occur. The presently disclosed embodiments can advantageously prevent or reduce bridging problems caused by undercutting of the dielectric layer 109.

[0035] To understand the advantages of the present invention, consider a reference design for opening 111, in which a second portion 105S2 of the sidewall of bonding pad 105 (e.g., a portion close to conductive line 107) is exposed by opening 111 (e.g., not covered by dielectric layer 109). When undercutting of dielectric layer 109 occurs, the undercut can extend to conductive line 107, and can expose a portion of the sidewall of bonding pad 105 facing conductive line 107, and can expose a portion of the sidewall of conductive line 107 facing bonding pad 105. During the formation of a surface finish layer (e.g., ENEPIG layer), the conductive material of the surface finish layer can be formed along the exposed portion of the sidewall of bonding pad 105 and along the exposed portion of the sidewall of conductive line 107. Due to the short distance D1 between the bonding pad 105 and the conductive line 107, if the material of the surface finish layer along the sidewall of the bonding pad 105 and along the sidewall of the conductive line 107 merges together, a bridge (e.g., an electrical short) between the bonding pad 105 and the conductive line 107 may occur. The present invention reduces the possibility of the undercut of the dielectric layer 109 exposing the sidewall of the bonding pad 105 facing the conductive line 107 by forming an opening 111 with a bevel design, thereby reducing the possibility of the undercut extending to (and thus exposing) the conductive line 107. Therefore, the possibility of bridging is greatly reduced. It should be noted that the bevel design for the conductive line 107 also helps to reduce the possibility of the undercut reaching the conductive line 107, thereby reducing the possibility of bridging.

[0036] Next, in Fig. 6A In FIG. 1 , SMD 121 is bonded to bonding pad 105 . Figure 6B Shows Fig. 6A The semiconductor package 100, but along Fig. 6A Section EE in. Figure 6BAs shown, terminals 123 of SMD 121 (which may be or include solder joints) are attached to bonding pads 105 by, for example, solder paste 125, and a reflow process may be performed to bond SMD 121 to bonding pads 105. Although not shown, one or more semiconductor dies may be bonded to corresponding conductive pads of a package substrate, for example, in a substrate such as Figure 1 region 117 in the die attach region.

[0037] Next, in Figure 7 In the embodiment of the present invention, an underfill material 131 is formed in the space below the SMD 121 (such as between the bonding pads 105 and around the terminals 123 of the SMD 121). Exemplary materials of the underfill material 131 include, but are not limited to, polymers and other suitable non-conductive materials. The underfill material 131 can be dispensed in the gap between the SMD 121 and the dielectric layer 103 using, for example, a needle or a jet dispenser. A curing process can be performed to cure the underfill material 131.

[0038] Next, in Figure 8 In the embodiment of the present invention, a molding material 133 is formed above the SMD 121 and around the bottom fill material 131. As an example, the molding material 133 may include an epoxy resin, an organic polymer, a polymer or other material with or without an added silica-based filler or glass filler. In some embodiments, the molding material 133 includes a liquid molding compound (LMC) that is a gel-type liquid when applied. When applied, the molding material 133 may also include a liquid or a solid. Optionally, the molding material 133 may include other insulating and / or sealing materials. In some embodiments, the molding material 133 is applied using a wafer-level molding process. The molding material 133 may be molded using, for example, compression molding, transfer molding, or other methods.

[0039] Next, in some embodiments, the molding material 133 is cured using a curing process. The curing process may include heating the molding material 133 to a predetermined temperature for a predetermined period of time using an annealing process or other heating process. The curing process may also include an ultraviolet (UV) light exposure process, an infrared (IR) energy exposure process, a combination thereof, or a combination thereof with a heating process. Alternatively, other methods may be used to cure the molding material 133. In some embodiments, a curing process is not included.

[0040] Fig. 9 FIG. 1 is a cross-sectional view of a semiconductor package 100A according to an embodiment. The semiconductor package 100A is similar to Figure 8The semiconductor package 100 is shown in FIG. 1 , but without the underfill material 131. Instead, the molding material 133 fills the space between the SMD 121 and the dielectric layer 103 and seals the SMD 121. The underfill material 131 and / or the molding material 133 may be referred to as a sealing material.

[0041] Fig.10 FIG. 2 shows a cross-sectional view of a semiconductor package 100B according to another embodiment. The semiconductor package 100B is similar to Figure 5A The semiconductor package 100 is shown in FIG. 1 , but the region 111C of the opening 111 (eg, Fig.10 In some embodiments, the area between the bonding pads 105 in the top view of FIG. 1 includes a rectangular area and two trapezoidal areas located on opposite sides of the rectangular area. Fig.10 The shape and size of each of the trapezoidal areas in the reference Figure 5A The same or similar ones discussed above will not be repeated in detail. Fig.10 In FIG. 1 , the second portion 105S2 and the third portion 105S3 of the sidewall of the bonding pad 105 are covered by the dielectric layer 109. It should be noted that because Fig.10 The SMD 121 (and the semiconductor die) have not yet been attached in the processing step, so Fig.10 The semiconductor package 100B actually shows a package substrate of a semiconductor package to be formed later. Similarly, Figures 11 to 13 A package substrate of a corresponding semiconductor package is shown.

[0042] Fig.11 FIG. 2 shows a cross-sectional view of a semiconductor package 100C according to another embodiment. The semiconductor package 100C is similar to Figure 5A The semiconductor package 100 is shown in FIG. 1 , but the trapezoidal region of the region 111C of the opening 111 is replaced with a rectangular region having a width W2, wherein W2 is smaller than the width W1. In other words, Fig.11 In the top view of the opening 111, the region 111C includes a larger rectangular region having a width W1 and a smaller rectangular region having a width W2. It should be noted that due to the smaller width W2, the smaller rectangular region causes the second portion 105S2 of the sidewall of the bonding pad 105 to be covered by the dielectric layer 109. Due to the smaller rectangular region of the opening 111, the distance between the second portion 105S2 of the sidewall of the bonding pad 105 and the corresponding sidewall (e.g., the closest sidewall) of the dielectric layer 109 remains substantially constant. Fig.11 In the embodiment, the third portion 105S3 of the sidewall of the bonding pad 105 is exposed by the opening 111 .

[0043] Fig.12 FIG. 2 shows a cross-sectional view of a semiconductor package 100D according to another embodiment. The semiconductor package 100D is similar to Fig.11 The semiconductor package 100C of FIG. 100B is shown in FIG. 100C, but the region 111C (e.g., the region between the bonding pads 105) includes a larger rectangular region (having a width W1) and two smaller rectangular regions (having a width W1 and a width W3, respectively) located on opposite sides of the larger rectangular region. In some embodiments, the width W1 is greater than the widths W2 and W3, and W2 is different from W3. In some embodiments, the width W1 is greater than the widths W2 and W3, and W2 is the same as W3. Fig.12 In FIG. 1 , the second portion 105S2 and the third portion 105S3 of the sidewall of the bonding pad 105 are covered by the dielectric layer 109 .

[0044] Fig.13 FIG. 2 shows a cross-sectional view of a semiconductor package 100E according to yet another embodiment. The opening 111 of the semiconductor package 100E includes three separate regions, such as a region 111A located directly above the bonding pad 105A, a region 111B located directly above the bonding pad 105B, and a region 111C located between the regions 111A and 111B. Fig.13 In the top view of FIG. 1 , regions 111A and 111B are rectangular regions that are completely disposed together with the periphery (e.g., sidewalls) of the corresponding underlying bonding pad 105. Therefore, all sidewalls of the bonding pad 105 are completely covered by the dielectric layer 109. Region 111C exposes a portion of the underlying dielectric layer 103. Region 111C is a rectangular region having a substantially constant width W1 and having a length (measured in a direction parallel to the sidewall 105SA of the bonding pad 105A) greater than the length of region 111A (or 111B). In some embodiments, regions 111A and 111B have the same length that is less than the length of region 111C.

[0045] Embodiments can achieve advantages. For example, the disclosed embodiments form an opening 111 with a chamfer design that covers the second portion 105S2 of the sidewall of the bonding pad 105 adjacent to the wire 107. The chamfer design of the opening helps to reduce or avoid bridging problems, thereby improving the reliability of the formed semiconductor package and improving product yield.

[0046] Fig.14 1 is a flow chart of a method 1000 of forming a semiconductor package according to some embodiments. It should be understood that Fig.14 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and changes. For example, the following may be added, removed, replaced, rearranged, or repeated: Fig.14 The steps shown.

[0047] refer to Fig.14In frame 1010, a first dielectric layer is formed over a substrate. In frame 1020, a first bonding pad and a second bonding pad are formed over the first dielectric layer. In frame 1030, a second dielectric layer is formed over the first bonding pad, the second bonding pad, and the first dielectric layer. In frame 1040, an opening is formed in the second dielectric layer to partially expose the first bonding pad and the second bonding pad, wherein the opening is formed to include: a first region located over the first bonding pad and partially exposing the first bonding pad; a second region located over the second bonding pad and partially exposing the second bonding pad; and a third region located between the first region and the second region, the third region exposing a portion of the first dielectric layer, wherein the opening exposes a first portion of a first sidewall of the first bonding pad facing the second bonding pad, and a second portion of the first sidewall is covered by the second dielectric layer.

[0048] According to an embodiment, a semiconductor package includes: a substrate; a first dielectric layer located above the substrate; a first bonding pad and a second bonding pad disposed above the first dielectric layer, the first bonding pad having a first sidewall facing the second bonding pad; a second dielectric layer located above the first bonding pad, the second bonding pad, and the first dielectric layer; and an opening located in the second dielectric layer, wherein, in a top view, the opening includes: a first region located above a first portion of the first bonding pad and exposing the first portion of the first bonding pad; a second region located above a second portion of the second bonding pad and exposing the second portion of the second bonding pad; and a third region located between the first region and the second region, the third region exposing a portion of the first dielectric layer, wherein a third length of the third region measured along a first direction parallel to the first sidewall of the first bonding pad is greater than a first length of the first region measured along the first direction, wherein the first portion of the first sidewall of the first bonding pad is exposed by the opening, and the second portion of the first sidewall is covered by the second dielectric layer. In an embodiment, the third length is greater than the second length of the second region measured along the first direction. In an embodiment, in a top view, a first region of the opening has a first edge intersecting a first sidewall of the first bonding pad, and a first portion and a second portion of the first sidewall are disposed on opposite sides of the first edge, wherein a third region of the opening has a second edge intersecting the first edge of the first region, wherein an angle between the first edge and the second edge is greater than 90 degrees. In an embodiment, in a top view, the first region of the opening further has a third edge different from the first edge, the third edge intersecting the first sidewall of the first bonding pad, wherein the third region of the opening further has a fourth edge intersecting the third edge, wherein an angle between the third edge and the fourth edge is greater than 90 degrees. In an embodiment, in a top view, the first region of the opening further has a third edge different from the first edge, the third edge intersecting the first sidewall of the first bonding pad, wherein the third region of the opening further has a fourth edge intersecting the third edge, wherein the third edge is perpendicular to the fourth edge. In an embodiment, in a top view, a first region of the opening has a first edge intersecting a first sidewall of the first bonding pad, and a first portion and a second portion of the first sidewall are disposed on opposite sides of the first edge, wherein a third region of the opening has a second edge intersecting the first edge of the first region, wherein the first edge is perpendicular to the second edge. In an embodiment, the third region of the opening includes a first rectangular region, a second rectangular region, and a third rectangular region between the first rectangular region and the second rectangular region, wherein a third width of the third rectangular region is greater than a first width of the first rectangular region and a second width of the second rectangular region, wherein the first width, the second width, and the third width are measured along a second direction perpendicular to the first direction. In an embodiment, the third portion of the first sidewall is covered by a second dielectric layer, wherein the first portion of the first sidewall is disposed between the second portion of the first sidewall and the third portion of the first sidewall.In an embodiment, the second bonding pad has a second sidewall facing the first bonding pad, wherein the first sidewall and the second sidewall are parallel to each other. In an embodiment, the semiconductor package further comprises: a wire located between the first dielectric layer and the second dielectric layer, wherein the closest distance between the first bonding pad and the wire is less than about 25 μm. In an embodiment, the semiconductor package further comprises: a surface mount device bonded to the first bonding pad and the second bonding pad; and a sealing material filling the opening in the second dielectric layer. In an embodiment, the second dielectric layer is a solder resist.

[0049] According to an embodiment, a semiconductor package includes: a substrate; a first dielectric layer located above the substrate; a first bonding pad and a second bonding pad located above the first dielectric layer, wherein the first bonding pad has a first sidewall facing the second bonding pad; a second dielectric layer located above the first bonding pad and the second bonding pad; and an opening passing through the second dielectric layer, wherein the opening extends from the first bonding pad to the second bonding pad, wherein the opening includes a first region located above the first bonding pad and exposing the first bonding pad, wherein in a top view, the opening exposes a first segment of the first sidewall of the first bonding pad, the first segment of the first sidewall is located between a first edge of the first region and a second edge of the first region, the first edge and the second edge intersect with the first sidewall, wherein the first segment of the first sidewall is located between the second segment of the first sidewall and a third segment of the first sidewall, and wherein the second segment of the first sidewall is covered by the second dielectric layer. In an embodiment, the semiconductor package further comprises: a conductive line located above the first dielectric layer and adjacent to the first bonding pad and the second bonding pad, wherein the conductive line extends along the second side wall of the first bonding pad intersecting the first side wall, wherein the second segment of the first side wall is located between the first segment of the first side wall and the conductive line. In an embodiment, the opening further comprises a second region located between the first bonding pad and the second bonding pad, the second region exposing a portion of the first dielectric layer, wherein the second region has a protrusion extending toward the conductive line, wherein the shortest distance between the protrusion and the conductive line is less than the shortest distance between the first bonding pad and the conductive line. In an embodiment, the distance between the opposite side walls of the protrusion decreases as the protrusion extends toward the conductive line. In an embodiment, in a top view, the protrusion has a rectangular shape.

[0050] According to an embodiment, a method of forming a semiconductor package includes: forming a first dielectric layer over a substrate; forming a first bonding pad and a second bonding pad over the first dielectric layer; forming a second dielectric layer over the first bonding pad, the second bonding pad, and the first dielectric layer; and forming an opening in the second dielectric layer to partially expose the first bonding pad and the second bonding pad, wherein the opening is formed to include: a first region located over the first bonding pad and partially exposing the first bonding pad; a second region located over the second bonding pad and partially exposing the second bonding pad; and a third region located between the first region and the second region, the third region exposing a portion of the first dielectric layer, wherein the opening exposes a first portion of a first sidewall of the first bonding pad facing the second bonding pad, and the second portion of the first sidewall is covered by the second dielectric layer. In an embodiment, a third length of the third region is formed to be greater than a first length of the first region and a second length of the second region, wherein the first length, the second length, and the third length are measured along a first direction parallel to the first sidewall. In an embodiment, the method further includes forming a conductive line adjacent to the first bonding pad and the second bonding pad, wherein in top view, a width of the third region measured along a second direction perpendicular to the first direction decreases as the third region extends toward the conductive line.

[0051] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be interpreted in a limiting sense. Various changes and combinations of the exemplary embodiments and other embodiments of the present invention will be apparent to those skilled in the art with reference to the description. Therefore, it is intended that the appended claims cover any such changes or embodiments.

Claims

1. A semiconductor package, comprising: substrate; a first dielectric layer located above the substrate; A first bonding pad and a second bonding pad disposed above the first dielectric layer, the first bonding pad having a first sidewall facing the second bonding pad; a second dielectric layer over the first bonding pad, the second bonding pad, and the first dielectric layer; as well as An opening is located in the second dielectric layer, wherein, in a top view, the opening comprises: a first region located above a first portion of the first bonding pad and exposing a first portion of the first bonding pad; a second region overlying and exposing a second portion of the second bonding pad; and a third region located between the first region and the second region, the third region exposing a portion of the first dielectric layer, wherein a third length of the third region measured along a first direction parallel to the first side wall of the first bonding pad is greater than a first length of the first region measured along the first direction, wherein a first portion of the first side wall of the first bonding pad is exposed by the opening, and a second portion of the first side wall is covered by the second dielectric layer.

2. The semiconductor package according to claim 1, wherein: The third length is greater than a second length of the second region measured along the first direction.

3. The semiconductor package according to claim 1, wherein: In a top view, the first region of the opening has a first edge intersecting with the first side wall of the first bonding pad, and the first portion and the second portion of the first side wall are arranged on opposite sides of the first edge, wherein the third region of the opening has a second edge intersecting with the first edge of the first region, wherein an angle between the first edge and the second edge is greater than 90 degrees and less than 180 degrees.

4. The semiconductor package according to claim 3, wherein: In the top view, the first area of ​​the opening also has a third edge different from the first edge, and the third edge intersects with the first side wall of the first bonding pad, wherein the third area of ​​the opening also has a fourth edge intersecting with the third edge, wherein the angle between the third edge and the fourth edge is greater than 90 degrees and less than 180 degrees.

5. The semiconductor package according to claim 3, wherein: In the top view, the first area of ​​the opening also has a third edge different from the first edge, and the third edge intersects with the first side wall of the first bonding pad, wherein the third area of ​​the opening also has a fourth edge intersecting with the third edge, and wherein the third edge is perpendicular to the fourth edge.

6. The semiconductor package according to claim 1, wherein: In a top view, the first region of the opening has a first edge intersecting with the first side wall of the first bonding pad, and the first portion and the second portion of the first side wall are arranged on opposite sides of the first edge, wherein the third region of the opening has a second edge intersecting with the first edge of the first region, wherein the first edge is perpendicular to the second edge.

7. The semiconductor package according to claim 6, wherein: The third area of ​​the opening includes a first rectangular area, a second rectangular area, and a third rectangular area located between the first rectangular area and the second rectangular area, wherein a third width of the third rectangular area is greater than a first width of the first rectangular area and a second width of the second rectangular area, wherein the first width, the second width, and the third width are measured along a second direction perpendicular to the first direction.

8. The semiconductor package according to claim 1, wherein: The third portion of the first sidewall is covered by the second dielectric layer, wherein the first portion of the first sidewall is disposed between the second portion of the first sidewall and the third portion of the first sidewall.

9. The semiconductor package according to claim 1, wherein: The second bonding pad has a second sidewall facing the first bonding pad, wherein the first sidewall and the second sidewall are parallel to each other.

10. The semiconductor package according to claim 1, further comprising: The conductive line is located between the first dielectric layer and the second dielectric layer, wherein the closest distance between the first bonding pad and the conductive line is less than 25 μm.

11. The semiconductor package according to claim 1, further comprising: a surface mount device bonded to the first bonding pad and the second bonding pad; as well as A sealing material fills the opening in the second dielectric layer.

12. The semiconductor package according to claim 1, wherein The second dielectric layer is a solder resist.

13. A semiconductor package, comprising: substrate; a first dielectric layer located above the substrate; a first bonding pad and a second bonding pad located above the first dielectric layer, wherein the first bonding pad has a first sidewall facing the second bonding pad; a second dielectric layer over the first bonding pad and the second bonding pad; and An opening is formed through the second dielectric layer, wherein the opening extends from the first bonding pad to the second bonding pad, wherein the opening includes a first region located above the first bonding pad and exposing the first bonding pad, wherein, in a top view, the opening exposes a first segment of the first sidewall of the first bonding pad, the first segment of the first sidewall is located between a first edge of the first region and a second edge of the first region, the first edge and the second edge intersecting the first sidewall, wherein the first segment of the first sidewall is located between a second segment of the first sidewall and a third segment of the first sidewall, and wherein the second segment of the first sidewall is covered by the second dielectric layer.

14. The semiconductor package according to claim 13, further comprising: A conductive line is located above the first dielectric layer and adjacent to the first bonding pad and the second bonding pad, wherein the conductive line extends along the second side wall of the first bonding pad intersecting the first side wall, and wherein the second segment of the first side wall is located between the first segment of the first side wall and the conductive line.

15. The semiconductor package according to claim 14, wherein: The opening also includes a second region located between the first bonding pad and the second bonding pad, the second region exposing a portion of the first dielectric layer, wherein the second region has a protrusion extending toward the conductive line, wherein the shortest distance between the protrusion and the conductive line is smaller than the shortest distance between the first bonding pad and the conductive line.

16. The semiconductor package according to claim 15, wherein: A distance between opposite side walls of the protruding portion decreases as the protruding portion extends toward the conductive line.

17. The semiconductor package according to claim 15, wherein: In top view, the protruding portion has a rectangular shape.

18. A method of forming a semiconductor package, the method comprising: forming a first dielectric layer over the substrate; forming a first bonding pad and a second bonding pad over the first dielectric layer; forming a second dielectric layer over the first bonding pad, the second bonding pad, and the first dielectric layer; as well as forming an opening in the second dielectric layer to partially expose the first bonding pad and the second bonding pad, wherein the opening is formed to include: a first region located above the first bonding pad and partially exposing the first bonding pad; a second region located above the second bonding pad and partially exposing the second bonding pad; and A third region is located between the first region and the second region, and the third region exposes a portion of the first dielectric layer, wherein the opening exposes a first portion of the first side wall of the first bonding pad facing the second bonding pad, and a second portion of the first side wall is covered by the second dielectric layer.

19. The method according to claim 18, wherein: A third length of the third region is formed to be greater than a first length of the first region and a second length of the second region, wherein the first length, the second length, and the third length are measured along a first direction parallel to the first sidewall.

20. The method according to claim 19, further comprising: A conductive line is formed adjacent to the first bonding pad and the second bonding pad, wherein, in a top view, a width of the third region measured along a second direction perpendicular to the first direction decreases as the third region extends toward the conductive line.

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