Display device and method of manufacturing the same

Abstract

A display device may include: a substrate including a first pixel region on which a first pixel is arranged and a second pixel region on which a second pixel is arranged; a metal layer arranged between the first pixel region and the second pixel region on the substrate; an inorganic insulating layer arranged on the metal layer and having a groove exposing at least a portion of the metal layer; and an organic insulating layer filling the groove of the inorganic insulating layer.

Description

Technical Field

[0001] Embodiments relate to a display device, and more particularly, to a display device that is robust against external impact and a method of manufacturing the display device. Background Art

[0002] Generally, a display device may include a display element and an electronic element for controlling an electrical signal applied to the display element. The electronic element may include a transistor, a capacitor, and a plurality of lines.

[0003] In order to accurately control whether a display element emits light and the degree of light emission, the number of transistors electrically connected to a display element is increasing, and the number of lines transmitting electrical signals to the transistors is also increasing. Therefore, research on methods for implementing high integration of display devices and methods for reducing the occurrence of defects is being actively conducted. Summary of the invention

[0004] Technical issues

[0005] An object of the present invention is to provide a display device which is robust against external impact and prevents penetration of impurities.

[0006] The object of the present invention is to provide a method for manufacturing the display device.

[0007] However, the objects of the present invention are not limited to these objects, and various extensions can be made without departing from the spirit and scope of the present invention.

[0008] Technical Solution

[0009] In order to achieve the above-mentioned objectives of the present invention, a display device according to an embodiment may include: a substrate, including a first pixel region on which a first pixel is arranged and a second pixel region on which a second pixel is arranged; a metal layer, arranged on the substrate between the first pixel region and the second pixel region; an inorganic insulating layer, arranged on the metal layer and having a groove exposing at least a portion of the metal layer; and an organic insulating layer, filling the groove of the inorganic insulating layer.

[0010] In an embodiment, the groove may expose at least a portion of an upper surface of the metal layer, and the organic insulating layer may contact the upper surface of the metal layer.

[0011] In an embodiment, the display device may further include a barrier layer disposed between the substrate and the metal layer.

[0012] In an embodiment, each of the first pixel and the second pixel may include a lower gate electrode disposed on the same layer as the metal layer.

[0013] In an embodiment, each of the first pixel and the second pixel may further include a driving transistor including a driving gate electrode, a driving source electrode, and a driving drain electrode, and the lower gate electrode may overlap the driving transistor.

[0014] In an embodiment, the lower gate electrode may be electrically connected to the driving source electrode.

[0015] In an embodiment, the display device may further include a driving voltage line supplying a driving voltage to the driving transistor, and the lower gate electrode may be electrically connected to the driving voltage line.

[0016] In an embodiment, the organic insulating layer may extend to an upper surface of the inorganic insulating layer.

[0017] In an embodiment, the second pixel region may be disposed in a first direction from the first pixel region, and the groove of the inorganic insulation layer may extend along a second direction intersecting the first direction.

[0018] In an embodiment, the display device may further include a first connection line disposed on the organic insulating layer and extending along the first direction.

[0019] In an embodiment, the first pixel and the second pixel may further include a first scan line and a second scan line, respectively, arranged so that the organic insulating layer is located therebetween, and the first scan line and the second scan line may be connected by a first connection line.

[0020] In an embodiment, an extension rate of the first connection line may be greater than an extension rate of the first scan line and an extension rate of the second scan line.

[0021] In order to achieve the above-mentioned objectives of the present invention, a display device according to an embodiment may include: a substrate including a plurality of pixel regions; a metal layer arranged on the substrate between the plurality of pixel regions; an inorganic insulating layer arranged on the metal layer and having a groove exposing at least a portion of the metal layer; and an organic insulating layer filling the groove of the inorganic insulating layer.

[0022] In an embodiment, the organic insulating layer may surround at least a portion of the plurality of pixel regions.

[0023] In an embodiment, an organic insulating layer may surround each of the plurality of pixel regions.

[0024] In an embodiment, the display device may further include a first connection line disposed on the organic insulating layer, extending in the first direction and crossing the plurality of pixel regions.

[0025] In an embodiment, the display device may further include a second connection line insulated from the first connection line, extending in a second direction intersecting the first direction, and crossing the plurality of pixel regions.

[0026] In order to achieve the above-mentioned objectives of the present invention, a method for manufacturing a display device according to an embodiment may include: forming a metal layer on a substrate between a first pixel area and a second pixel area; forming an inorganic insulating layer on the metal layer; forming a groove in the inorganic insulating layer that exposes at least a portion of the metal layer; and forming an organic insulating layer that fills the groove of the inorganic insulating layer.

[0027] In an embodiment, the method may further include forming a first lower gate electrode and a second lower gate electrode in the first pixel region and the second pixel region, respectively, on the substrate, and the metal layer, the first lower gate electrode and the second lower gate electrode are formed simultaneously.

[0028] In an embodiment, the method may further include forming a first driving transistor and a second driving transistor respectively overlapping the first lower gate electrode and the second lower gate electrode.

[0029] In an embodiment, the method may further include forming a first connection line extending from the first pixel region to the second pixel region on the organic insulating layer.

[0030] In an embodiment, the method may further include forming a first scan line and a second scan line in a first pixel area and a second pixel area respectively on a substrate, the first scan line and the second scan line are arranged so that an organic insulating layer is located therebetween, and the first scan line and the second scan line may be connected by a first connecting line.

[0031] Beneficial Effects

[0032] In the display device according to the embodiment, the metal layer may be disposed under the groove of the inorganic insulating layer filled with the organic insulating layer so that the thickness of the insulating layer and the substrate under the metal layer may not be reduced. Therefore, impurities may not flow through the insulating layer and the substrate under the organic insulating layer.

[0033] In the method for manufacturing the display device according to the embodiment, before forming the groove of the inorganic insulating layer filled with the organic insulating layer, a metal layer serving as an etching stop layer can be formed under the groove of the inorganic insulating layer so that the insulating layer and the substrate under the metal layer can not be etched. Therefore, a groove with a uniform depth of the inorganic insulating layer can be formed. In addition, the metal layer can be formed substantially simultaneously with the lower gate electrode of the driving transistor. Therefore, an additional process for forming the metal layer may not be required.

[0034] However, the effects of the present invention are not limited to the above-described effects, and various extensions may be made without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a plan view showing a display device according to an embodiment.

[0036] Figure 2 It is shown Figure 1 Block diagram of a display device in FIG.

[0037] Figure 3 is a circuit diagram showing a pixel according to the embodiment.

[0038] Figure 4 is a layout diagram showing adjacent pixels according to an embodiment.

[0039] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 It shows the Figure 4 Layout diagram of the components in .

[0040] Fig.11 It is along Figure 4 A cross-sectional view taken along line XI-XI'.

[0041] Fig.12 It is along Figure 4 A cross-sectional view taken along line XII-XII'.

[0042] Fig.13 , Fig.14 , Fig.15 and Fig.16 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment.

[0043] Fig.17 is a circuit diagram showing a pixel according to the embodiment.

[0044] Fig.18 is a layout diagram showing adjacent pixels according to an embodiment.

[0045] Fig.19 It shows the Fig.18 Layout diagram of the components in .

[0046] Fig. 20 and Fig.21 is a plan view showing a part of a display device according to an embodiment.

[0047] Fig. 22 and Fig.23 is a diagram showing a display device according to an embodiment.

[0048] Fig.24 is a plan view showing a display device according to an embodiment. DETAILED DESCRIPTION

[0049] Hereinafter, a display device and a method of manufacturing the same according to an embodiment of the present invention will be explained in detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are used for the same components.

[0050] Figure 1 is a plan view showing a display device according to an embodiment.

[0051] Reference Figure 1 , a display device according to an embodiment may include a substrate 100, the substrate 100 including a display area DA and a peripheral area PA outside the display area DA. A plurality of pixels PX including a display element such as an organic light emitting diode (OLED) may be provided in the display area DA. A line for transmitting an electrical signal applied to the display area DA may be provided in the peripheral area PA. Hereinafter, a display device including an organic light emitting diode as a display element will be described. However, the present invention is not limited thereto, and may be applied to various types of display devices such as a liquid crystal display device, an electrophoretic display device, and the like.

[0052] Figure 2 It is shown Figure 1 Block diagram of a display device in FIG.

[0053] Reference Figure 2 , the display device according to the embodiment may include a display unit 10 including a plurality of pixels PX, a scan driver 20 , a data driver 30 , an emission control driver 40 , and a controller 50 .

[0054] The display unit 10 may be disposed in the display area DA. The display unit 10 may include a plurality of pixels PX disposed at intersections of a plurality of scan lines SL1 to SLn+1, a plurality of data lines DL1 to DLm, and a plurality of emission control lines EL1 to ELn. Thus, the plurality of pixels PX may be arranged in a substantially matrix form. The scan lines SL1 to SLn+1 and the emission control lines EL1 to ELn may extend in a first direction DR1 (i.e., a row direction), and the data lines DL1 to DLm and the drive voltage line ELVDDL may extend in a second direction DR2 (i.e., a column direction).

[0055] Each pixel PX may be connected to three scan lines among the scan lines SL1 to SLn+1. The scan driver 20 may transmit three scan signals to each pixel PX through the scan lines SL1 to SLn+1. In other words, the scan driver 20 may sequentially supply scan signals to the scan lines SL2 to SLn, the previous scan lines SL1 to SLn-1, and the next scan lines SL3 to SLn+1.

[0056] Each pixel PX may be connected to one of the data lines DL1 to DLm. The data driver 30 may transmit a data signal to each pixel PX through the data lines DL1 to DLm. When a scan signal is supplied to the scan lines SL2 to SLn, a data signal may be supplied to the pixel PX selected by the scan signal.

[0057] Each pixel PX may be connected to one of the emission control lines EL1 to ELn. The emission control driver 40 may transmit an emission control signal to each pixel PX through the emission control lines EL1 to ELn. The emission control signal may control the emission time of the pixel PX. The emission control driver 40 may be omitted according to the internal structure of the pixel PX.

[0058] The controller 50 may convert a plurality of image signals IR, IG, and IB transmitted from the outside into a plurality of image data signals DR, DG, and DB, and transmit the converted image data signals DR, DG, and DB to the data driver 30. In addition, the controller 50 may receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK, and may generate control signals for controlling the scan driver 20, the data driver 30, and the emission control driver 40. In other words, the controller 50 may generate a scan drive control signal SCS for controlling the scan driver 20, a data drive control signal DCS for controlling the data driver 30, and an emission drive control signal ECS for controlling the emission control driver 40.

[0059] Each pixel PX may receive a driving voltage ELVDD and a common voltage ELVSS from an external power source. The driving voltage ELVDD may be a predetermined high-level voltage, and the common voltage ELVSS may be a voltage lower than the driving voltage ELVDD or a ground voltage. The driving voltage ELVDD may be supplied to each pixel PX through a driving voltage line ELVDDL. The initialization voltage line IL may receive an initialization voltage VINT from an external power source, and supply the initialization voltage VINT to each pixel PX.

[0060] Each pixel PX may emit light having predetermined brightness by a driving current supplied to a light emitting element according to a data signal transmitted through the data lines DL1 to DLm.

[0061] Figure 3 is a circuit diagram showing a pixel according to the embodiment.

[0062] Reference Figure 3, each pixel PX may include signal lines 121 , 122 , 123 and 151 , a plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 and T7 connected to the signal lines 121 , 122 , 123 and 151 , a storage capacitor Cst, an initialization voltage line 131 , a driving voltage line 152 and an organic light emitting diode OLED.

[0063] Figure 3 The signal lines 121, 122, 123 and 151, the initialization voltage line 131 and the driving voltage line 152 provided for each pixel PX are shown, however, the present invention is not limited thereto. In another embodiment, at least one of the signal lines 121, 122, 123 and 151 and / or the initialization voltage line 131 may be shared by adjacent pixels PX.

[0064] The transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 may include a driving transistor T1 , a switching transistor T2 , a compensation transistor T3 , a first initialization transistor T4 , an operation control transistor T5 , an emission control transistor T6 , and a second initialization transistor T7 .

[0065] The signal lines 121, 122, 123, and 151 may include a scan line 121 that transmits a scan signal Sn, a previous scan line 122 that transmits a previous scan signal Sn-1 to the first initialization transistor T4 and the second initialization transistor T7, an emission control line 123 that transmits an emission control signal En to the operation control transistor T5 and the emission control transistor T6, and a data line 151 that intersects the scan line 121 and transmits a data signal Dm. The driving voltage line 152 may transmit a driving voltage ELVDD to the driving transistor T1, and the initialization voltage line 131 may transmit an initialization voltage VINT for initializing the driving transistor T1 and the anode of the organic light emitting diode OLED.

[0066] The driving gate electrode G1 of the driving transistor T1 may be connected to the first electrode C1 of the storage capacitor Cst, the driving source electrode S1 of the driving transistor T1 may be connected to the driving voltage line 152 via the operation control transistor T5, and the driving drain electrode D1 of the driving transistor T1 may be electrically connected to the anode of the organic light emitting diode OLED via the emission control transistor T6. The driving transistor T1 may receive the data signal Dm according to the switching operation of the switching transistor T2, and provide the driving current I to the organic light emitting diode OLED. OLED .

[0067] In an embodiment, the driving transistor T1 may be a dual-gate type transistor including two gate electrodes. For example, the driving transistor T1 may include a driving gate electrode G1 and a lower gate electrode BG as a gate electrode. When the driving transistor T1 further includes the lower gate electrode BG, the charge mobility of the driving transistor T1 may be increased because the current moving path of the driving transistor T1 is expanded. In an embodiment, the lower gate electrode BG may be electrically connected to the driving source electrode S1. In such an embodiment, the voltage of the driving source electrode S1 may be supplied to the lower gate electrode BG.

[0068] A switching gate electrode G2 of the switching transistor T2 may be connected to the scan line 121, a switching source electrode S2 of the switching transistor T2 may be connected to the data line 151, and a switching drain electrode D2 of the switching transistor T2 may be connected to the driving source electrode S1 of the driving transistor T1 and connected to the driving voltage line 152 via the operation control transistor T5. The switching transistor T2 may perform a switching operation in which the switching transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 121 and transmits the data signal Dm transmitted through the data line 151 to the driving source electrode S1 of the driving transistor T1.

[0069] The compensation gate electrode G3 of the compensation transistor T3 may be connected to the scan line 121, the compensation source electrode S3 of the compensation transistor T3 may be connected to the driving drain electrode D1 of the driving transistor T1 and connected to the anode of the organic light emitting diode OLED via the emission control transistor T6, and the compensation drain electrode D3 of the compensation transistor T3 may be connected to the first electrode C1 of the storage capacitor Cst, the first initialization source S4 of the first initialization transistor T4, and the driving gate electrode G1 of the driving transistor T1. The compensation transistor T3 may be turned on according to the scan signal Sn transmitted through the scan line 121, and electrically connects the driving gate electrode G1 and the driving drain electrode D1 of the driving transistor T1 to diode-connect the driving transistor T1.

[0070] The first initialization gate electrode G4 of the first initialization transistor T4 may be connected to the previous scan line 122, the first initialization drain electrode D4 of the first initialization transistor T4 may be connected to the second initialization drain electrode D7 of the second initialization transistor T7 and the initialization voltage line 131, and the first initialization source electrode S4 of the first initialization transistor T4 may be connected to the first electrode C1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation transistor T3, and the driving gate electrode G1 of the driving transistor T1. The first initialization transistor T4 may perform an initialization operation in which the first initialization transistor T4 is turned on according to the previous scan signal Sn-1 transmitted through the previous scan line 122, and transmits the initialization voltage VINT to the driving gate electrode G1 of the driving transistor T1 to initialize the voltage of the driving gate electrode G1 of the driving transistor T1.

[0071] The operation control gate electrode G5 of the operation control transistor T5 can be connected to the emission control line 123, the operation control source electrode S5 of the operation control transistor T5 can be connected to the driving voltage line 152, and the operation control drain electrode D5 of the operation control transistor T5 can be connected to the driving source electrode S1 of the driving transistor T1 and the switching drain electrode D2 of the switching transistor T2.

[0072] The emission control gate electrode G6 of the emission control transistor T6 can be connected to the emission control line 123, the emission control source electrode S6 of the emission control transistor T6 can be connected to the driving drain electrode D1 of the driving transistor T1 and the compensation source electrode S3 of the compensation transistor T3, and the emission control drain electrode D6 of the emission control transistor T6 can be connected to the second initialization source electrode S7 of the second initialization transistor T7 and the anode of the organic light emitting diode OLED.

[0073] The operation control transistor T5 and the emission control transistor T6 may be turned on at the same time according to the emission control signal En transmitted through the emission control line 123, and thus, the driving voltage ELVDD may be transmitted to the organic light emitting diode OLED so as to drive the current I OLED It can flow through an organic light emitting diode OLED.

[0074] The second initialization gate electrode G7 of the second initialization transistor T7 may be connected to the previous scan line 122, the second initialization source electrode S7 of the second initialization transistor T7 may be connected to the emission control drain electrode D6 of the emission control transistor T6 and the anode of the organic light emitting diode OLED, and the second initialization drain electrode D7 of the second initialization transistor T7 may be connected to the first initialization drain electrode D4 of the first initialization transistor T4 and the initialization voltage line 131. The second initialization transistor T7 may be turned on according to the previous scan signal Sn-1 transmitted through the previous scan line 122 to initialize the anode of the organic light emitting diode OLED.

[0075] Figure 3 The first initialization transistor T4 and the second initialization transistor T7 are shown to be connected to the previous scan line 122, however, the present invention is not limited thereto. In another embodiment, the first initialization transistor T4 can be connected to the previous scan line 122 and driven according to the previous scan signal Sn-1, and the second initialization transistor T7 can be connected to a separate signal line (e.g., a subsequent scan line) and driven according to a signal transmitted to the separate signal line. Figure 3 The positions of the source electrodes S1 to S7 and the drain electrodes D1 to D7 in the transistor may be changed according to the type (p-type or n-type) of the transistor.

[0076] A specific operation of each pixel PX according to the embodiment is as follows.

[0077] During initialization, when a previous scan signal Sn- 1 is supplied through the previous scan line 122 , the first initialization transistor T4 may be turned on in response to the previous scan signal Sn- 1 , and the driving transistor T1 may be initialized by the initialization voltage VINT supplied from the initialization voltage line 131 .

[0078] During data programming, when the scan signal Sn is supplied through the scan line 121, the switching transistor T2 and the compensation transistor T3 may be turned on in response to the scan signal Sn. In this case, the driving transistor T1 may be diode-connected through the turned-on compensation transistor T3 and biased in a forward direction.

[0079] Then, a compensation voltage (Dm+Vth, Vth is a negative value) by reducing the threshold voltage Vth of the driving transistor T1 from the data signal Dm supplied by the data line 151 may be applied to the driving gate electrode G1 of the driving transistor T1. In this case, the driving voltage ELVDD and the compensation voltage Dm+Vth may be applied to the opposite electrodes C1 and C2 of the storage capacitor Cst, and charges corresponding to the voltage difference between the opposite electrodes C1 and C2 may be stored in the storage capacitor Cst.

[0080] During emission, the operation control transistor T5 and the emission control transistor T6 may be turned on by the emission control signal En supplied from the emission control line 123. The driving current I may be generated according to the voltage difference between the voltage of the driving gate electrode G1 of the driving transistor T1 and the driving voltage ELVDD. OLED , and can supply a driving current I to the organic light emitting diode OLED through the emission control transistor T6 OLED .

[0081] Figure 4 is a layout diagram showing adjacent pixels according to an embodiment. Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 It shows the Figure 4 Layout diagram of the components in . Fig.11 It is along Figure 4 A cross-sectional view taken along line XI-XI'. Fig.12 It is along Figure 4 A cross-sectional view taken along line XII-XII'.

[0082] Reference Figures 4 to 11, the display device according to the embodiment may include: a metal layer ML disposed between a plurality of pixel areas PXA1, PXA2, and PXA3; an inorganic insulating layer 110 having a groove GR exposing at least a portion of the metal layer ML; and an organic insulating layer 160 filling the groove GR of the inorganic insulating layer 110. In addition, the display device may include a first connection line 140 disposed on the organic insulating layer 160 and extending in a first direction DR1, and a second connection line 150 insulated from the first connection line 140 and extending in a second direction DR2.

[0083] In the present embodiment, the buffer layer 111, the first insulating layer 112, the second insulating layer 113 and the third insulating layer 114 disposed under the first connection line 140 and including an inorganic insulating material may be collectively referred to as an inorganic insulating layer 110. The inorganic insulating layer 110 may have a groove GR between adjacent pixel regions.

[0084] Fig.11 The inorganic insulating layer 110 is shown to have a groove GR. In other words, the buffer layer 111 has an opening 111a between adjacent pixel regions, the first insulating layer 112 has an opening 112a between adjacent pixel regions, the second insulating layer 113 has an opening 113a between adjacent pixel regions, and the third insulating layer 114 has an opening 114a between adjacent pixel regions. Therefore, it can be understood that the inorganic insulating layer 110 including the buffer layer 111, the first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 has a groove GR between adjacent pixel regions PXA1, PXA2, and PXA3. The groove GR may mean a trench formed in the inorganic insulating layer 110.

[0085] The width GRW of the groove GR of the inorganic insulating layer 110 may be several micrometers (μm). For example, the width GRW of the groove GR of the inorganic insulating layer 110 may be about 5 μm to about 10 μm.

[0086] The organic insulating layer 160 may be filled in the groove GR of the inorganic insulating layer 110. The first and second connection lines 140 and 150 may be disposed on the organic insulating layer 160 between the pixel regions PXA1, PXA2, and PXA3 where the organic insulating layer 160 is disposed. A detailed description of the organic insulating layer 160 will be described below.

[0087] The groove GR of the inorganic insulating layer 110 and the organic insulating layer 160 may be disposed in at least a portion between the pixel regions PXA1, PXA2, and PXA3. Figure 4In the embodiment, the groove GR of the inorganic insulating layer 110 and the organic insulating layer 160 may be disposed to surround each of the pixel regions PXA1, PXA2, and PXA3. In other words, the organic insulating layer 160 may be disposed to surround the periphery of the first pixel PX1 and the periphery of the second pixel PX2. However, the present invention is not limited thereto.

[0088] For example, the groove GR of the inorganic insulating layer 110 and the organic insulating layer 160 may not surround each of the pixel regions PXA1, PXA2, and PXA3, and may be formed to extend in the second direction DR2 between the pixel regions PXA1, PXA2, and PXA3. In addition, the groove GR of the inorganic insulating layer 110 and the organic insulating layer 160 may be formed to extend in the first direction DR1 between the pixel regions PXA1, PXA2, and PXA3.

[0089] The groove GR of the inorganic insulating layer 110 and the organic insulating layer 160 can minimize the influence of the display device due to external impact. Since the inorganic insulating layer 110 has a higher hardness than the organic insulating layer 160, the possibility of breaking the inorganic insulating layer 110 due to external impact may be relatively high. When the inorganic insulating layer 110 breaks, cracks may also occur in the signal line disposed inside or on the inorganic insulating layer 110, and defects such as disconnection may occur.

[0090] However, in the display device according to the present embodiment, the inorganic insulating layer 110 may have a groove GR between the plurality of pixel regions PXA1, PXA2, and PXA3, and the organic insulating layer 160 may fill the groove GR of the inorganic insulating layer 110, so that the possibility of crack propagation may be reduced despite the occurrence of an external impact. In addition, since the organic insulating layer 160 has a lower hardness than that of the inorganic insulating layer 110, the organic insulating layer 160 may absorb stress caused by the external impact, and the concentration of stress on the first connection line 140 and the second connection line 150 provided on the organic insulating layer 160 may be effectively reduced.

[0091] In the present embodiment, the metal layer ML may be disposed under the organic insulating layer 160 filling the groove GR of the inorganic insulating layer 110. In the case where the groove GR is formed by etching the inorganic insulating layer 110, if the metal layer ML does not exist, only the inorganic insulating layer and the substrate 100 may exist between the pixel regions PXA1, PXA2, and PXA3. Therefore, the depth of the groove GR may not be constant according to the etching time. When the depth of the groove GR increases to exceed a predetermined depth, the thickness of the inorganic insulating layer and the substrate 100 disposed under the groove GR may be reduced to a predetermined thickness or less, and therefore, impurities such as moisture and oxygen from the outside may easily flow through the inorganic insulating layer and the substrate 100 having a relatively small thickness under the groove GR.

[0092] However, in the display device according to the present embodiment, the metal layer ML may be formed between the pixel regions PXA1, PXA2, and PXA3 before forming the groove GR of the inorganic insulating layer 110. The metal layer ML may serve as an etching stop layer when etching the inorganic insulating layer 110 to form the groove GR of the inorganic insulating layer 110. Therefore, the depth of the groove GR of the inorganic insulating layer 110 due to the metal layer ML may not increase to more than a predetermined depth, and the thickness of the inorganic insulating layer and the substrate 100 under the groove GR may be ensured in order to block the inflow of impurities from the outside.

[0093] The first connection line 140 and the second connection line 150 may be disposed on the organic insulating layer 160 to connect the plurality of pixels PX1, PX2, and PX3 to each other. The first connection line 140 and the second connection line 150 may be disposed on the inorganic insulating layer 110 where the organic insulating layer 160 does not exist. The first connection line 140 and the second connection line 150 may function as wiring for transmitting electrical signals to the pixels PX1, PX2, and PX3.

[0094] Since the first and second connection lines 140 and 150 may connect the pixels PX1, PX2, and PX3 to each other, the first and second connection lines 140 and 150 may be relatively long compared to other lines. Therefore, stress may be applied to the first and second connection lines 140 and 150 with a high probability.

[0095] Therefore, since the first connection line 140 and the second connection line 150 include a material having a high elongation, defects such as cracks or disconnections may not occur in the first connection line 140 and the second connection line 150. For example, the first connection line 140 and the second connection line 150 may include aluminum (Al). The first connection line 140 and the second connection line 150 may have a multilayer structure. In an embodiment, the first connection line 140 and the second connection line 150 may have a Ti / Al / Ti stacked structure. In an embodiment, the elongation of the first connection line 140 and the elongation of the second connection line 150 may be greater than the elongation of the line disposed thereunder.

[0096] In the following, reference will be made to Figures 4 to 12 A display device according to an embodiment is described in detail.

[0097] Figures 5 to 10 The arrangement of semiconductor layers, wires, electrodes, etc. arranged on the same layer is shown. The insulating layer can be placed Figures 5 to 10 For example, the buffer layer 111 may be placed between the layers shown in FIG. Figure 5 The layers shown in Figure 6 Between the layers shown in FIG. 1 , a first insulating layer 112 may be placed Figure 6 The layers shown in Figure 7 Between the layers shown in FIG. 1 , a second insulating layer 113 may be placed Figure 7 The layers shown in Figure 8 Between the layers shown in FIG. 1 , a third insulating layer 114 may be placed Figure 8 The layers shown in Fig. 9 Between the layers shown in FIG. 1 , a fourth insulating layer 115 may be placed Fig. 9 The layers shown in Fig.10 Between the layers shown. Figures 5 to 10 The layers shown in FIG. 4 may be electrically connected to each other through contact holes defined in at least some of the insulating layers described above.

[0098] Reference Figure 4 , Figure 5 and Fig.11 The metal layer ML and the lower gate electrode BG may be disposed on the same layer and may include the same material. For example, the metal layer ML and the lower gate electrode BG may include molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be formed of a single layer or multiple layers.

[0099] The metal layer ML and the lower gate electrode BG may be disposed on a barrier layer 101 disposed on the substrate 100. The substrate 100 may include glass, metal or plastic. In an embodiment, the substrate 100 may include a material having a flexible or bendable property. When the substrate 100 has a flexible or bendable property, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP). The substrate 100 may have a single-layer structure or a multi-layer structure of the above materials, and may also include an inorganic layer in the case of a multi-layer structure. In an embodiment, the substrate 100 may have an organic / inorganic / organic structure.

[0100] The substrate 100 may include a plurality of pixel regions PXA1, PXA2, and PXA3 on which pixels PX1, PX2, and PX3 are respectively disposed. The pixel regions PXA1, PXA2, and PXA3 may include a first pixel region PXA1 on which a first pixel PX1 is disposed, a second pixel region PXA2 on which a second pixel PX2 is disposed, and a third pixel region PXA3 on which a third pixel PX3 is disposed. The first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may be spaced apart from each other. The second pixel region PXA2 may be disposed in a first direction DR1 from the first pixel region PXA1, and the third pixel region PXA3 may be disposed in a second direction DR2 from the first pixel region PXA1.

[0101] The barrier layer 101 may prevent or minimize the upward penetration of impurities from the substrate 100. The barrier layer 101 may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may have a single-layer or multi-layer structure.

[0102] The metal layer ML may be disposed between the pixel regions PXA1, PXA2, and PXA3. In an embodiment, the metal layer ML may surround each of the pixel regions PXA1, PXA2, and PXA3. In other words, the metal layer ML may surround one pixel region.

[0103] The lower gate electrode BG may be an island type and disposed in each of the pixel regions PXA1, PXA2, and PXA3. In the present embodiment, the lower gate electrode BG of each of the pixels PX may be formed to be separated from each other. For example, the lower gate electrode BG of the first pixel PX1 may be formed to be spaced apart from the lower gate electrode BG of the second pixel PX2.

[0104] The buffer layer 111 may be disposed on the metal layer ML and the lower gate electrode BG. The buffer layer 111 may include an inorganic material including an oxide or a nitride. The buffer layer 111 may be used to increase the smoothness of the upper surface of the substrate 100 and may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0105] Reference Figure 4 , Figure 6 and Fig.11 , semiconductor layers AS1 to AS7 of the driving transistor T1, the switching transistor T2, the compensation transistor T3, the first initialization transistor T4, the operation control transistor T5, the emission control transistor T6, and the second initialization transistor T7 may be disposed on the buffer layer 111. The semiconductor layers AS1 to AS7 may be disposed on the same layer and may include the same material. For example, the semiconductor layers AS1 to AS7 may be formed of polycrystalline silicon.

[0106] The driving semiconductor layer AS1 of the driving transistor T1, the switching semiconductor layer AS2 of the switching transistor T2, the compensation semiconductor layer AS3 of the compensation transistor T3, the first initialization semiconductor layer AS4 of the first initialization transistor T4, the operation control semiconductor layer AS5 of the operation control transistor T5, the emission control semiconductor layer AS6 of the emission control transistor T6, and the second initialization semiconductor layer AS7 of the second initialization transistor T7 can be connected to each other and bent into various shapes.

[0107] Each of the semiconductor layers AS1 to AS7 may include a channel region and a source region and a drain region on opposite sides of the channel region. In an embodiment, the source region and the drain region may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The source region and the drain region correspond to a source electrode and a drain electrode, respectively. Hereinafter, the terms source region and drain region are used to replace the source electrode or the drain electrode.

[0108] The driving semiconductor layer AS1 may include a driving channel region A1 and a driving source region S1 and a driving drain region D1 on opposite sides of the driving channel region A1. The driving semiconductor layer AS1 may have a curved shape, and the driving channel region A1 may be formed to be longer than other channel regions A2 to A7. For example, when the driving semiconductor layer AS1 has a shape such as 'Ω' or 'S' that is curved multiple times, a long channel length may be formed in a narrow space. Because the driving channel region A1 is formed to be long, the driving range of the gate voltage applied to the driving gate electrode G1 may be widened, so that the grayscale of light emitted from the organic light emitting diode OLED may be more accurately controlled, and the display quality may be improved.

[0109] The driving semiconductor layer AS1 may overlap the lower gate electrode BG. Specifically, the driving channel region A1 of the driving semiconductor layer AS1 may overlap the lower gate electrode BG, and the lower gate electrode BG may function as a gate electrode of the driving transistor T1.

[0110] The switching semiconductor layer AS2 may include a switching channel region A2 and a switching source region S2 and a switching drain region D2 on opposite sides of the switching channel region A2. The switching drain region D2 may be connected to the driving source region S1.

[0111] The compensation semiconductor layer AS3 may include compensation channel regions A3a and A3c, and compensation source regions S3 and compensation drain regions D3 on opposite sides of the compensation channel regions A3a and A3c. The compensation transistor T3 is a dual transistor, and the compensation semiconductor layer AS3 may include two compensation channel regions A3a and A3c. A region A3b between the compensation channel regions A3a and A3c may be a region doped with impurities, and may correspond to a source region of one of the dual transistors and a drain region of the other of the dual transistors.

[0112] The first initialization semiconductor layer AS4 may include first initialization channel regions A4a and A4c, and first initialization source regions S4 and first initialization drain regions D4 on opposite sides of the first initialization channel regions A4a and A4c. The first initialization transistor T4 is a double transistor, and the first initialization semiconductor layer AS4 may include two first initialization channel regions A4a and A4c. A region A4b between the first initialization channel regions A4a and A4c may be a region doped with impurities, and may correspond to a source region of one of the double transistors and a drain region of the other of the double transistors.

[0113] The operation control semiconductor layer AS5 may include an operation control channel region A5 and an operation control source region S5 and an operation control drain region D5 on opposite sides of the operation control channel region A5. The operation control drain region D5 may be connected to the driving source region S1.

[0114] The emission control semiconductor layer AS6 may include an emission control channel region A6 and an emission control source region S6 and an emission control drain region D6 on opposite sides of the emission control channel region A6. The emission control source region S6 may be connected to the driving drain region D1.

[0115] The second initialization semiconductor layer AS7 may include a second initialization channel region A7 and a second initialization source region S7 and a second initialization drain region D7 on opposite sides of the second initialization channel region A7.

[0116] The first insulating layer 112 may be disposed on the semiconductor layers AS1 to AS7. The first insulating layer 112 may include an inorganic material including an oxide or a nitride. For example, the first insulating layer 112 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, etc.

[0117] In the present embodiment, the semiconductor layers AS1 to AS7 of each of the pixels PX may be formed to be separated from each other. For example, the semiconductor layers AS1 to AS7 of the first pixel PX1 may be formed to be spaced apart from the semiconductor layers AS1 to AS7 of the second pixel PX2.

[0118] Reference Figure 4 , Figure 7 and Fig.11 , the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 may be disposed on the first insulating layer 112. The scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 may be disposed on the same layer and may include the same material. For example, the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 may include molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be formed of a single layer or multiple layers.

[0119] The driving gate electrode G1 may be an island type and may overlap the driving channel region A1 of the driving semiconductor layer AS1. The driving gate electrode G1 may perform not only a gate electrode of the driving transistor T1 but also a first electrode C1 of the storage capacitor Cst.

[0120] Portions or protruding portions of the scan line 121 , the previous scan line 122 , and the emission control line 123 may correspond to gate electrodes of the transistors T2 to T7 .

[0121] The region of the scan line 121 overlapping the switch channel region A2 and the compensation channel region A3a and A3c may correspond to the switch gate electrode G2 and the compensation gate electrodes G3a and G3b, respectively. The region of the previous scan line 122 overlapping the first initialization channel region A4a and A4c and the second initialization channel region A7 may correspond to the first initialization gate electrodes G4a and G4b and the second initialization gate electrode G7, respectively. The region of the emission control line 123 overlapping the operation control channel region A5 and the emission control channel region A6 may correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0122] The compensation gate electrodes G3 a and G3 b may be a double gate electrode including a first compensation gate electrode G3 a and a second compensation gate electrode G3 b , and may be used to prevent or reduce the occurrence of leakage current.

[0123] In the present embodiment, the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 of each of the pixels PX may be formed to be separated from each other. For example, the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 of the first pixel PX1 may be formed to be spaced apart from the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 of the second pixel PX2.

[0124] The scan line 121 , the previous scan line 122 , and the emission control line 123 of the first pixel PX1 may be respectively connected to the scan line 121 , the previous scan line 122 , and the emission control line 123 of the second pixel PX2 through first connection lines 140 disposed on different layers.

[0125] The second insulating layer 113 may be disposed on the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1. The second insulating layer 113 may include an inorganic material, and the inorganic material includes an oxide or a nitride. For example, the second insulating layer 113 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, etc.

[0126] Reference Figure 4 , Figure 8 and Fig.11 , the second electrode C2 of the storage capacitor Cst and the initialization voltage line 131 may be disposed on the second insulating layer 113. The second electrode C2 of the storage capacitor Cst and the initialization voltage line 131 may be disposed on the same layer and may include the same material. For example, the second electrode C2 of the storage capacitor Cst and the initialization voltage line 131 may include a conductive material, the conductive material including molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be formed of a single layer or multiple layers.

[0127] In the present embodiment, the second electrode C2 of the storage capacitor Cst of each of the pixels PX and the initialization voltage line 131 may be formed to be separated from each other. For example, the second electrode C2 of the storage capacitor Cst of the first pixel PX1 and the second electrode C2 of the storage capacitor Cst of the second pixel PX2 may be disposed to be spaced apart from each other. In addition, the initialization voltage line 131 of the first pixel PX1 and the initialization voltage line 131 of the second pixel PX2 may be disposed to be spaced apart from each other.

[0128] The third insulating layer 114 may be disposed on the second electrode C2 of the storage capacitor Cst and the initialization voltage line 131. The third insulating layer 114 may include an inorganic material including an oxide or a nitride. For example, the third insulating layer 114 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, etc.

[0129] Reference Figure 4 , Fig. 9 and Fig.11 , the first connection lines 140 extending in the first direction DR1 may be disposed on the third insulating layer 114. The first connection lines 140 may include emission control connection lines 141, mesh connection lines 142, scan connection lines 143, previous scan connection lines 144, initialization voltage connection lines 145, and first node connection lines 146.

[0130] The emission control connection line 141 may connect the emission control line 123 of the first pixel PX1 and the emission control line 123 of the second pixel PX2 via contact holes CNT1a and CNT1b formed through the third insulating layer 114 and the second insulating layer 113. The emission control connection line 141 may extend along the first direction DR1 while overlapping the emission control line 123 of the first pixel PX1 and the emission control line 123 of the second pixel PX2.

[0131] The grid connection line 142 may connect the second electrode C2 of the first pixel PX1 and the second electrode C2 of the second pixel PX2 via the contact holes CNT3a and CNT2b formed to pass through the third insulating layer 114. Since the second electrode C2 of the storage capacitor Cst is connected to the driving voltage line 152 to receive the driving voltage ELVDD, the grid connection line 142 may be used to transmit the driving voltage ELVDD across the plurality of pixels PX arranged in the first direction DR1. In the case where a space for a separate driving voltage line extending in the first direction DR1 is not ensured, a driving voltage line having a grid structure may be formed by the grid connection line 142. Therefore, a space for the storage capacitor Cst may also be ensured so that a high-resolution display device may be implemented.

[0132] The scan connection line 143 may connect the scan line 121 of the first pixel PX1 and the scan line 121 of the second pixel PX2 via contact holes CNT4a and CNT4b formed through the third insulating layer 114 and the second insulating layer 113. The scan connection line 143 may extend in the first direction DR1 while overlapping the scan line 121 of the first pixel PX1 and the scan line 121 of the second pixel PX2.

[0133] The previous scan connection line 144 may connect the previous scan line 122 of the first pixel PX1 and the previous scan line 122 of the second pixel PX2 via contact holes CNT5a and CNT5b formed through the third insulating layer 114 and the second insulating layer 113. The previous scan connection line 144 may extend in the first direction DR1 while overlapping the previous scan line 122 of the first pixel PX1 and the previous scan line 122 of the second pixel PX2.

[0134] The initialization voltage connection line 145 may connect the initialization voltage line 131 of the first pixel PX1 and the initialization voltage line 131 of the second pixel PX2 via contact holes CNT6a and CNT6b formed through the third insulating layer 114. The initialization voltage connection line 145 may extend in the first direction DR1 while overlapping the initialization voltage line 131 of the first pixel PX1 and the initialization voltage line 131 of the second pixel PX2.

[0135] The first node connection line 146 may connect the lower gate electrode BG to the driving source region S1 of the driving transistor T1 via the contact holes CNTa and CNTb. The first node connection line 146 may be connected to the lower gate electrode BG via the contact hole CNTa passing through the third insulating layer 114, the second insulating layer 113, the first insulating layer 112, and the buffer layer 111, and may be connected to the driving source region S1 via the contact hole CNTb passing through the third insulating layer 114, the second insulating layer 113, and the first insulating layer 112.

[0136] The emission control connection line 141, the grid connection line 142, the scan connection line 143, the previous scan connection line 144, and the initialization voltage connection line 145 may connect the first pixel PX1 and the second pixel PX2 while extending from the first pixel area PXA1 to the second pixel area PXA2. The emission control connection line 141, the grid connection line 142, the scan connection line 143, the previous scan connection line 144, and the initialization voltage connection line 145 may connect a plurality of pixels PX arranged in the first direction DR1.

[0137] In the present embodiment, the semiconductor layers AS1 to AS7 disposed under the first connection line 140 and the conductive layers such as the signal lines 121, 122, 123, the initialization voltage line 131, and the first and second electrodes C1 and C2 of the storage capacitor Cst may be formed separately for each pixel PX. Therefore, it is possible to prevent the stress generated in one pixel PX from spreading to another pixel PX. The first connection line 140 may be formed of a material having a high elongation, thereby minimizing defects caused by stress.

[0138] As described above, the emission control connection line 141, the grid connection line 142, the scan connection line 143, the previous scan connection line 144 and the initialization voltage connection line 145 can connect the first pixel PX1 and the second pixel PX2 while crossing the upper portion of the organic insulating layer 160 disposed therebetween, thereby being used to supply electrical signals to the plurality of pixels PX.

[0139] A fourth insulating layer 115 having an opening 115a between pixels PX and a fifth insulating layer 116 disposed on the fourth insulating layer 115 and filling the opening 115a of the fourth insulating layer 115 may be disposed on the first connection line 140. The fourth insulating layer 115 may include an inorganic material, and the inorganic material includes an oxide or a nitride. For example, the fourth insulating layer 115 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, etc., and the fifth insulating layer 116 may include an organic material such as acryl, benzocyclobutene (BCB), polyimide (PI), hexamethyldisiloxane (HMDSO), etc. When the fourth insulating layer 115 includes an inorganic material, the opening 115a may be formed between the pixels PX so that the stress applied to the fourth insulating layer 115 may not be diffused. In addition, since the fifth insulating layer 116 including an organic material is formed in the opening 115a, the fifth insulating layer 116 may absorb the stress applied to the display device.

[0140] Reference Figure 4 , Fig.10 and Fig.11 , the second connection line 150 extending in the second direction DR2 may be disposed on the fifth insulating layer 116. The second connection line 150 may be insulated from the first connection line 140 by the fourth insulating layer 115 and the fifth insulating layer 116. The second connection line 150 may include a data line 151, a driving voltage line 152, a second node connection line 153, a third node connection line 154, and an intermediate connection line 155.

[0141] The data line 151, the driving voltage line 152, the second node connection line 153, the third node connection line 154 and the intermediate connection line 155 can be arranged on the same layer and can include the same material. For example, the data line 151, the driving voltage line 152, the second node connection line 153, the third node connection line 154 and the intermediate connection line 155 can be formed by a conductive material with high elongation. For example, the data line 151, the driving voltage line 152, the second node connection line 153, the third node connection line 154 and the intermediate connection line 155 can include aluminum (Al). In an embodiment, the data line 151, the driving voltage line 152, the second node connection line 153, the third node connection line 154 and the intermediate connection line 155 can be formed by a Ti / Al / Ti multilayer structure.

[0142] The data line 151 may be connected to the switching source region S2 of the switching transistor T2 via a contact hole CNT7 passing through the fifth insulating layer 116, the fourth insulating layer 115, the third insulating layer 114, the second insulating layer 113, and the first insulating layer 112. The data line 151 may connect a plurality of pixels PX arranged in the second direction DR2, for example, the first pixel PX1 and the third pixel PX3.

[0143] The driving voltage line 152 may be connected to the operation control source region S5 of the operation control transistor T5 via a contact hole CNT8 passing through the fifth insulating layer 116, the fourth insulating layer 115, the third insulating layer 114, the second insulating layer 113, and the first insulating layer 112. In addition, the driving voltage line 152 may be connected to the second electrode C2 of the storage capacitor Cst via a contact hole CNT9 passing through the fifth insulating layer 116, the fourth insulating layer 115, and the third insulating layer 114. The driving voltage line 152 may connect a plurality of pixels PX arranged in the second direction DR2, for example, the first pixel PX1 and the third pixel PX3.

[0144] The second node connection line 153 may transmit an initialization voltage VINT for initializing the driving transistor T1 and the pixel electrode 310. The second node connection line 153 may be connected to the first initialization transistor T4 and the second initialization transistor T7 via a contact hole CNT10 passing through the fifth insulating layer 116, the fourth insulating layer 115, the third insulating layer 114, the second insulating layer 113, and the first insulating layer 112, and may be connected to the initialization voltage line 131 via a contact hole CNT11 passing through the fifth insulating layer 116, the fourth insulating layer 115, and the third insulating layer 114.

[0145] The third node connection line 154 may connect the driving gate electrode G1 and the compensation drain region D3 of the compensation transistor T3 via the contact holes CNT12 and CNT13. The island type driving gate electrode G1 may be electrically connected to the compensation transistor T3 through the third node connection line 154.

[0146] The intermediate connection line 155 may be connected to the second initialization source region S7 of the second initialization transistor T7 via a contact hole CNT14 passing through the fifth insulating layer 116, the fourth insulating layer 115, the third insulating layer 114, the second insulating layer 113, and the first insulating layer 112. The intermediate connection line 155 may be connected to the emission control drain region D6 of the emission control transistor T6 via a contact hole CNT15 passing through the fifth insulating layer 116, the fourth insulating layer 115, the third insulating layer 114, the second insulating layer 113, and the first insulating layer 112.

[0147] The data line 151 , the driving voltage line 152 , and the intermediate connection line 155 may connect adjacent pixels, for example, the first pixel PX1 and the third pixel PX3 , in the second direction DR2 while passing through the organic insulating layer 160 between the adjacent pixels.

[0148] The planarization layer 117 may be disposed on the second connection line 150. The planarization layer 117 may include an organic material such as acryl, benzocyclobutene (BCB), polyimide (PI), hexamethyldisiloxane (HMDSO), etc. The planarization layer 117 may be used to substantially planarize the upper portion of the transistors T1 to T7. The planarization layer 117 may be provided as a single layer or multiple layers.

[0149] Reference Fig.11 , the organic insulating layer 160 may be disposed between the first pixel PX1 and the second pixel PX2 to fill at least a portion of the groove GR of the inorganic insulating layer 110. The organic insulating layer 160 may not completely fill the groove GR. In addition, the organic insulating layer 160 may not be filled in a portion of the groove GR.

[0150] However, in order for the organic insulating layer 160 to absorb external impact, it may be desirable to completely fill the groove GR. In an embodiment, the organic insulating layer 160 may be formed to extend to the upper surface of the inorganic insulating layer 110. In such an embodiment, due to the characteristics of the organic insulating layer 160, the upper surface of the organic insulating layer 160 may be set to a convex shape. In other words, the maximum height h of the organic insulating layer 160 may be greater than the depth d of the groove GR.

[0151] The angle between the upper surface of the organic insulating layer 160 and the upper surface of the inorganic insulating layer 110 may be smaller than about 45 degrees. If the slope of the boundary where the upper surface of the inorganic insulating layer 110 and the upper surface of the organic insulating layer 160 contact is not smooth, the conductive material used in the process of forming the first connection line 140 by patterning the conductor layer may remain on the boundary without being removed therefrom. In this case, a short circuit between the retained conductive material and other conductive layers may occur. Therefore, it may be desirable to form the upper surface of the organic insulating layer 160 to have a gentle slope relative to the upper surface of the inorganic insulating layer 110.

[0152] The organic insulating layer 160 may include acryl, methacrylic acid, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, or the like.

[0153] The organic insulating layer 160 may be disposed in the groove GR between the first pixel PX1 and the second pixel PX2 of the inorganic insulating layer 110 so that the first pixel PX1 and the second pixel PX2 may be separated under the first connection line 140. Therefore, it is possible to prevent stress or cracking from spreading from the first pixel PX1 to the second pixel PX2.

[0154] An organic light emitting diode OLED including a pixel electrode 310 , an opposing electrode 330 , and an intermediate layer 320 interposed therebetween and including an emission layer may be disposed on the planarization layer 117 .

[0155] The pixel electrode 310 may be connected to the intermediate connection line 155 through a contact hole defined in the planarization layer 117 , and may be connected to the emission control drain region D6 of the emission control transistor T6 through the intermediate connection line 155 .

[0156] The pixel defining layer 118 may be disposed on the planarization layer 117. The pixel defining layer 118 may be used to define pixels by having an opening corresponding to each pixel PX (i.e., an opening exposing at least a central portion of the pixel electrode 310). In addition, the pixel defining layer 118 may increase the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310, so that an arc may be prevented from being generated at the edge of the pixel electrode 310. For example, the pixel defining layer 118 may be formed of an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0157] The intermediate layer 320 of the organic light emitting diode OLED may include a low molecular weight material or a high molecular weight material. When the intermediate layer 320 includes a low molecular weight material, the intermediate layer 320 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc. are stacked in a single structure or a composite structure, and may include copper phthalocyanine (CuPc), N,N-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), tris-8-hydroxyquinoline aluminum (tris-8-hydroxyquinoline aluminum) (Alq3), etc.

[0158] When the intermediate layer 320 includes a high molecular weight material, the intermediate layer 320 may have a structure including a hole transport layer (HTL) and an emission layer (EML). In this case, the HTL may include PEDOT, and the EML may include a high molecular weight material such as polyparaphenylene vinylene (PPV) and polyfluorene. The intermediate layer 320 may include a layer integrally formed above the plurality of pixel electrodes 310, or may include a layer patterned to correspond to each of the plurality of pixel electrodes 310.

[0159] The counter electrode 330 may be disposed above the display area DA and may be disposed as follows. Fig.11 In other words, the counter electrode 330 may be integrally formed throughout the plurality of organic light emitting diodes OLED to correspond to the plurality of pixel electrodes 310 .

[0160] In an embodiment, the pixel electrode 310 and the counter electrode 330 may be the anode and cathode of the organic light emitting diode OLED, respectively. However, the present invention is not limited thereto, and in another embodiment, the pixel electrode 310 and the counter electrode 330 may be the cathode and anode of the organic light emitting diode OLED, respectively.

[0161] Since the organic light emitting diode OLED can be easily damaged by moisture or oxygen from the outside, the encapsulation layer 400 can cover and protect the organic light emitting diode OLED. The encapsulation layer 400 can cover the display area DA and extend outside the display area DA. The encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0162] The first inorganic encapsulation layer 410 may cover the counter electrode 330 and may include ceramic, metal oxide, metal nitride, metal carbide, metal oxynitride, indium oxide, tin oxide, indium tin oxide (ITO), silicon oxide, silicon nitride and / or silicon oxynitride. If necessary, other layers such as a capping layer may be placed between the first inorganic encapsulation layer 410 and the counter electrode 330. Because the first inorganic encapsulation layer 410 is formed along the lower structure, the upper surface of the first inorganic encapsulation layer 410 may not be planarized.

[0163] The organic encapsulation layer 420 may cover the first inorganic encapsulation layer 410, and unlike the first inorganic encapsulation layer 410, the upper surface of the organic encapsulation layer 420 may be substantially planarized. Specifically, the upper surface of the organic encapsulation layer 420 may be substantially planarized in a portion corresponding to the display area DA. The organic encapsulation layer 420 may include one or more materials selected from the group consisting of acrylic, methacrylic acid, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

[0164] The second inorganic encapsulating layer 430 may cover the organic encapsulating layer 420 and may include ceramic, metal oxide, metal nitride, metal carbide, metal oxynitride, indium oxide, tin oxide, indium tin oxide (ITO), silicon oxide, silicon nitride, and / or silicon oxynitride.

[0165] As described above, since the encapsulation layer 400 has a multi-layer structure including the first inorganic encapsulation layer 410, the organic encapsulation layer 420, and the second inorganic encapsulation layer 430, although cracks occur inside the encapsulation layer 400, the cracks may not be connected between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Therefore, a path through which moisture or oxygen from the outside penetrates into the display area DA can be prevented or minimized.

[0166] Reference Fig.12 , one end of the intermediate connection line 155 may be connected to the second initialization source region S7 of the second initialization transistor T7 of the first pixel PX1 via a contact hole CNT14 passing through the fifth insulating layer 116, the fourth insulating layer 115, the third insulating layer 114, the second insulating layer 113, and the first insulating layer 112. In addition, the other end of the intermediate connection line 155 may be connected to the emission control drain region D6 of the emission control transistor T6 of the third pixel PX3 via a contact hole CNT15 passing through the fifth insulating layer 116, the fourth insulating layer 115, the third insulating layer 114, the second insulating layer 113, and the first insulating layer 112.

[0167] The intermediate connection line 155 may cross the organic insulating layer 160 disposed between the first pixel PX1 and the third pixel PX3, and may connect the first pixel PX1 and the third pixel PX3 arranged in the second direction DR2. The organic insulating layer 160 may be disposed in the groove GR in the region between the first pixel PX1 and the third pixel PX3 of the inorganic insulating layer 110, and may separate the first pixel PX1 and the third pixel PX3 under the intermediate connection line 155. Therefore, the spread of stress or cracks may be prevented.

[0168] Fig.13 , Fig.14 , Fig.15 and Fig.16 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment. Fig.13 , Fig.14 , Fig.15 and Fig.16 Can show manufacturing Fig.11 A method for a display device in a display device.

[0169] Reference Fig.13 First, a barrier layer 101 may be formed on a substrate 100 by depositing an inorganic insulating material. Then, a conductive material such as a metal may be deposited on the barrier layer 101, and the conductive material may be patterned to form a metal layer ML and a lower gate electrode BG. The metal layer ML may be formed between pixel regions (e.g., between the first pixel region PXA1 and the second pixel region PXA2), and the lower gate electrode BG may be formed in each of the pixel regions. Therefore, the metal layer ML and the lower gate electrode BG may be formed substantially simultaneously.

[0170] Reference Fig.14 , transistors including the driving transistor T1 , the storage capacitor Cst, and the inorganic insulating layer 110 may be formed on the substrate 100 on which the metal layer ML and the lower gate electrode BG are formed.

[0171] First, a buffer layer 111 may be formed by depositing an inorganic insulating material on the barrier layer 101 on which the metal layer ML and the lower gate electrode BG are formed. Then, a semiconductor material may be deposited on the buffer layer 111, and the semiconductor material may be patterned to form a semiconductor layer including a driving semiconductor layer AS1 (including a driving channel region A1, a driving source region S1, and a driving drain region D1). Then, a first insulating layer 112 may be formed by depositing an inorganic insulating material on the buffer layer 111 on which the semiconductor layer is formed. Then, a conductive material such as a metal may be deposited on the first insulating layer 112, and the conductive material may be patterned to form a gate electrode including a driving gate electrode G1 serving as a first electrode C1 of a storage capacitor Cst. Thus, a transistor including a semiconductor layer and a gate electrode may be formed.

[0172] Then, the second insulating layer 113 may be formed by depositing an inorganic insulating material on the first insulating layer 112 on which the gate electrode is formed. Then, a conductive material such as a metal may be deposited on the second insulating layer 113 and patterned to form the second electrode C2 of the storage capacitor Cst. Thus, the storage capacitor Cst including the first electrode C1 and the second electrode C2 may be formed.

[0173] Then, the third insulating layer 114 may be formed by depositing an inorganic insulating material on the second insulating layer 113 on which the second electrode C2 of the storage capacitor Cst is formed. Thus, the inorganic insulating layer 110 including the buffer layer 111, the first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may be formed.

[0174] Reference Fig.15 , a groove GR may be formed in the inorganic insulating layer 110. In order to form the groove GR in the inorganic insulating layer 110, a photomask process and an etching process may be performed. An opening 111a of the buffer layer 111, an opening 112a of the first insulating layer 112, an opening 113a of the second insulating layer 113, and an opening 114a of the third insulating layer 114 may be formed by an etching process. For example, the etching process may be a dry etching process.

[0175] The groove GR of the inorganic insulating layer 110 may be formed on the metal layer ML disposed between the first pixel region PXA1 and the second pixel region PXA2. The groove GR of the inorganic insulating layer 110 may expose at least a portion of the metal layer ML. Specifically, the groove GR of the inorganic insulating layer 110 may expose a central portion of the upper surface of the metal layer ML.

[0176] The groove GR of the inorganic insulating layer 110 may be formed substantially simultaneously with the contact hole formed in the first pixel region PXA1 and / or the second pixel region PXA2. Alternatively, the groove GR of the inorganic insulating layer 110 may be formed after the contact hole is formed in the first pixel region PXA1 and / or the second pixel region PXA2.

[0177] Before forming the groove GR of the inorganic insulating layer 110, a metal layer ML may be formed between the first pixel region PXA1 and the second pixel region PXA2, and the metal layer ML may be used as an etching stop layer when etching the inorganic insulating layer 110 to form the groove GR of the inorganic insulating layer 110. Therefore, the barrier layer 101 disposed under the metal layer ML may not be etched due to the metal layer ML, and the thickness of the barrier layer 101 and the substrate 100 under the groove GR for blocking the inflow of impurities from the outside may be ensured.

[0178] Reference Fig.16, the organic insulating layer 160 filling the groove GR of the inorganic insulating layer 110 may be formed. For example, an organic insulating material may be deposited on the third insulating layer 114 and patterned to form the organic insulating layer 160 .

[0179] Reference Fig.11 , the first connection line 140 may be formed on the inorganic insulating layer 110 and the organic insulating layer 160. For example, a conductive material such as a metal may be deposited on the inorganic insulating layer 110 in which the groove GR is filled by the organic insulating layer 160, and the conductive material may be patterned to form the first connection line 140. The first connection line 140 may extend from the first pixel area PXA1 to the second pixel area PXA2, and thus, an element of the first pixel PX1 may be connected to an element of the second pixel PX2.

[0180] Fig.17 is a circuit diagram showing a pixel according to the embodiment. Fig.18 is a layout diagram showing adjacent pixels according to an embodiment. Fig.19 It shows the Fig.18 Layout diagram of the components in .

[0181] Reference Fig.17 In another embodiment, the lower gate electrode BG may be electrically connected to the driving voltage line 152. In such another embodiment, the driving voltage ELVDD may be supplied to the lower gate electrode BG.

[0182] Reference Fig.18 and Fig.19 In another embodiment, the first connection line 140 may include a Fig. 9 The fourth node connection line 147 of the first node connection line 146 is shown in FIG.

[0183] The fourth node connection line 147 may connect the lower gate electrode BG and the storage capacitor Cst via the contact holes CNTc and CNTd. Figure 8 The fourth node connection line 147 may be connected to the lower gate electrode BG via a contact hole CNTc passing through the third insulating layer 114, the second insulating layer 113, the first insulating layer 112, and the buffer layer 111, and may be connected to the second electrode C2 via a contact hole CNTd passing through the third insulating layer 114. Since the second electrode C2 of the storage capacitor Cst is connected to the driving voltage line 152 to receive the driving voltage ELVDD, the lower gate electrode BG may be electrically connected to the driving voltage line 152 via the contact hole CNTd and the second electrode C2 of the storage capacitor Cst.

[0184] Fig. 20 and Fig.21 is a plan view showing a part of a display device according to an embodiment.

[0185] Reference Fig. 20 and Fig.21 , the groove GR of the inorganic insulating layer 110 and the organic insulating layer 160 may be disposed to surround a plurality of pixels PX by grouping them. Fig. 20 In the case of , the groove GR of the inorganic insulating layer 110 and the organic insulating layer 160 may be disposed to surround two pixels, ie, the first pixel PX1 and the second pixel PX2. Fig.21 In this case, the groove GR of the inorganic insulating layer 110 and the organic insulating layer 160 may be disposed to surround the four pixels PX1, PX2, PX3, and PX4. However, the embodiments of the present invention are not limited thereto, and the number of pixels to be grouped may be variously modified.

[0186] The number of pixels to be grouped may be the same or different depending on the position in a display device. For example, the groove GR of the inorganic insulating layer 110 and the organic insulating layer 160 may be arranged to surround one pixel PX in an area with a high risk of being subjected to cracks or stress, and may be arranged to surround a plurality of pixels PX in another area.

[0187] Fig. 22 and Fig.23 is a diagram showing a display device according to an embodiment. Fig. 22 shows that the display area is collapsed, Fig.23 The display area is shown being curled.

[0188] The display device according to the embodiment may include the groove GR of the inorganic insulating layer 110 in the display area DA and the organic insulating layer 160 filling the groove GR, so that the display area DA can be displayed as shown. Fig. 22 and Fig.23 Although the display area DA is folded or curled, the occurrence of cracks can be minimized due to the groove GR of the inorganic insulating layer 110, and the organic insulating layer 160 filling the groove GR of the inorganic insulating layer 110 can absorb the tensile stress caused by bending.

[0189] Fig.24 is a plan view showing a display device according to an embodiment.

[0190] Reference Fig.24 The display device according to the embodiment may have a bending area BA bent around a bending axis BAX in the peripheral area PA, and may further include a bending groove GR' and a curved organic insulating layer 160' filling the bending groove GR'. The display device may further include a fan-out line 150' disposed on the curved organic insulating layer 160' and extending from the display area DA to cross the bending area BA.

[0191] The bending groove GR' may mean an opening formed in the inorganic insulating layer in the bending area BA. Fig.11 When the groove GR is formed in the middle, the curved groove GR' can be formed substantially at the same time.

[0192] The curved organic insulating layer 160' may fill the curved groove GR' and may be used to absorb the tensile stress applied during bending. The curved organic insulating layer 160' may be formed by Fig.11 The organic insulating layer 160 is formed of substantially the same material.

[0193] The fan-out line 150 ′ may mean a wiring that is disposed in the peripheral area PA and transmits an electrical signal provided from a driving driver IC or a flexible circuit board disposed in the peripheral area PA to the display area DA.

[0194] The fan-out line 150' may be formed of substantially the same material as the first connection line 140 or the second connection line 150 in the display area DA. In other words, the fan-out line 150' may include a material having a high elongation. For example, the fan-out line 150' may include aluminum (Al).

[0195] Industrial Applicability

[0196] The display device according to the embodiment of the present invention may be applied to display devices included in computers, notebooks, mobile phones, smart phones, smart tablets, PMPs, PDAs, MP3 players, and the like.

[0197] Although a display device and a method for manufacturing the display device according to an embodiment of the present invention have been described with reference to the accompanying drawings, the illustrated embodiments are examples and may be modified and changed by persons having ordinary knowledge in the relevant technical field without departing from the technical spirit of the present invention described in the claims.

[0198] Description of Reference Numerals

[0199] 100: Base 101: Barrier layer

[0200] 110: inorganic insulating layer 140: first connecting line

[0201] 150: second connection line 160: organic insulating layer

[0202] PXA1: first pixel area PXA2: second pixel area

[0203] PXA3: third pixel area ML: metal layer

[0204] BG: Lower gate electrode GR: Recess

Claims

1. A display device, comprising: a substrate including a first pixel region on which a first pixel is disposed and a second pixel region on which a second pixel is disposed; a metal layer, disposed on the substrate between the first pixel region and the second pixel region; an inorganic insulating layer disposed on the metal layer and having a groove exposing at least a portion of the metal layer; as well as an organic insulating layer filling the groove of the inorganic insulating layer, wherein the organic insulating layer contacts the upper surface of the metal layer, Wherein, the maximum height of the organic insulating layer is greater than the depth of the groove, and Wherein, an angle between an upper surface of the organic insulating layer and an upper surface of the inorganic insulating layer is less than 45 degrees.

2. The display device according to claim 1, wherein: The groove exposes at least a portion of an upper surface of the metal layer.

3. The display device according to claim 1, further comprising: The barrier layer is arranged between the substrate and the metal layer.

4. The display device according to claim 1, wherein: Each of the first pixel and the second pixel includes a lower gate electrode disposed on the same layer as the metal layer.

5. The display device according to claim 4, wherein: Each of the first pixel and the second pixel further includes a driving transistor including a driving gate electrode, a driving source electrode, and a driving drain electrode, and, Wherein, the lower gate electrode overlaps with the driving transistor.

6. The display device according to claim 5, wherein: The lower gate electrode is electrically connected to the driving source electrode.

7. The display device according to claim 5, further comprising: a driving voltage line for supplying a driving voltage to the driving transistor, Wherein, the lower gate electrode is electrically connected to the driving voltage line.

8. The display device according to claim 1, wherein: The organic insulating layer extends to an upper surface of the inorganic insulating layer.

9. The display device according to claim 1, wherein: The second pixel region is arranged in a first direction from the first pixel region, and The groove of the inorganic insulating layer extends along a second direction intersecting with the first direction.

10. The display device according to claim 9, further comprising: The first connecting line is disposed on the organic insulating layer and extends along the first direction.

11. The display device according to claim 10, wherein: The first pixel and the second pixel further include a first scan line and a second scan line respectively arranged so that the organic insulating layer is interposed therebetween, and, The first scanning line and the second scanning line are connected through the first connecting line.

12. The display device according to claim 11, wherein: An elongation rate of the first connection line is greater than an elongation rate of the first scanning line and an elongation rate of the second scanning line.

13. A display device, comprising: a substrate including a plurality of pixel regions; a metal layer, disposed on the substrate between the plurality of pixel regions; an inorganic insulating layer disposed on the metal layer and having a groove exposing at least a portion of the metal layer; as well as An organic insulating layer fills the groove of the inorganic insulating layer and contacts the upper surface of the metal layer, wherein the maximum height of the organic insulating layer is greater than the depth of the groove, and the angle between the upper surface of the organic insulating layer and the upper surface of the inorganic insulating layer is less than 45 degrees.

14. The display device according to claim 13, wherein: The organic insulating layer surrounds at least a portion of the plurality of pixel regions.

15. The display device according to claim 13, wherein: The organic insulating layer surrounds each of the plurality of pixel regions.

16. The display device according to claim 13, further comprising: The first connection line is disposed on the organic insulating layer, extends in a first direction, and crosses the plurality of pixel regions.

17. The display device according to claim 16, further comprising: The second connection line is insulated from the first connection line, extends in a second direction intersecting the first direction, and crosses the plurality of pixel regions.

18. A method for manufacturing a display device, the method comprising: forming a metal layer on the substrate between the first pixel region and the second pixel region; forming an inorganic insulating layer on the metal layer; forming a groove in the inorganic insulating layer to expose at least a portion of the metal layer; as well as An organic insulating layer is formed to fill the groove of the inorganic insulating layer and contact the upper surface of the metal layer, wherein the maximum height of the organic insulating layer is greater than the depth of the groove, and the angle between the upper surface of the organic insulating layer and the upper surface of the inorganic insulating layer is less than 45 degrees.

19. The method of claim 18, further comprising: forming a first lower gate electrode and a second lower gate electrode in the first pixel region and the second pixel region respectively on the substrate, Wherein, the metal layer, the first lower gate electrode and the second lower gate electrode are formed simultaneously.

20. The method of claim 19, further comprising: A first driving transistor and a second driving transistor are formed to overlap the first lower gate electrode and the second lower gate electrode, respectively.

21. The method of claim 18, further comprising: A first connection line extending from the first pixel region to the second pixel region is formed on the organic insulating layer.

22. The method of claim 21, further comprising: forming a first scan line and a second scan line in the first pixel region and the second pixel region respectively on the substrate, wherein the first scan line and the second scan line are arranged so that the organic insulating layer is located therebetween, The first scanning line and the second scanning line are connected through the first connecting line.

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