Deep groove silicon capacitor structure
By setting a trench structure with equal widths on the silicon substrate, the problem of sharp angles forming in the deep trench silicon capacitors during the etching process is solved, and the production quality and performance stability of the capacitor are improved.
Patent Information
- Application Number
- CN202411514168.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-07
AI Technical Summary
Existing deep-trench silicon capacitors are prone to sharp angles during trench etching, which affects the subsequent process quality and the reliability and service life of the capacitor.
A trench structure with equal width is provided on the silicon substrate to reduce or avoid the formation of sharp corners at the bottom of the trench structure and reduce electrical and mechanical stress concentration.
Through uniform groove depth and flat bottom morphology, the production quality and performance stability of the capacitor are improved, and the capacitance value accuracy and electric breakdown strength are controlled and improved.
Smart Images
Figure CN119403437A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor capacitors, and in particular to a deep trench silicon capacitor structure. Background Art
[0002] In the field of electronic circuits, capacitors are a key electronic component with wide applications and are indispensable. With the rapid development of electronic technology, the performance requirements for capacitors are also increasing, especially in terms of capacity, size and high-frequency applications. Traditional capacitors, such as multilayer ceramic capacitors (MLCCs), although they perform well in many occasions, are gradually showing their limitations in the face of higher capacity requirements, smaller size restrictions and high-frequency stability.
[0003] In order to meet the urgent demand for large-capacity capacitors in electronic circuits, the industry continues to explore new capacitor packaging technologies and integration methods. Among them, an effective method is to increase the total capacity by placing multiple capacitors in parallel, but this method is often accompanied by an increase in parasitic resistance, inductance and the impedance effect of the capacitor itself, which limits its application in high-frequency circuits.
[0004] To overcome these challenges, deep trench silicon capacitors were developed. Deep trench silicon capacitors achieve a significant increase in capacity (1 to 2 orders of magnitude) by introducing a third dimension into a single device while keeping the size of the device unchanged. This innovation not only significantly reduces parasitic effects, but also improves the temperature stability of the capacitor's capacity and high-frequency application performance, giving it a significant advantage over traditional MLCCs.
[0005] The manufacturing process of deep trench silicon capacitors involves a series of precise process steps, including etching trenches of specific shape and depth on the silicon substrate, covering the insulating dielectric layer to form a capacitor structure, filling the conductive dielectric layer, and preparing the metal connection layer. Among them, trench etching is the key link in the manufacturing process, which directly affects the capacity and size of the capacitor and the feasibility of subsequent processes.
[0006] In the trench etching process, the design pattern is transferred to the photoresist in proportion using the photolithography process, and then the reactive gas reacts with the silicon atoms on the surface of the silicon substrate to form a silicon deep trench of a specified depth. The depth and direction of etching are closely related to the energy and direction of the reactive gas particles hitting the substrate, and the size of the design pattern becomes a key factor affecting the etching effect.
[0007] However, in the actual etching process, due to the change in the design pattern size, sharp corners may be formed at the bottom of the deep trench, which in turn affects the quality of the subsequent deposition of dielectric film and conductive polysilicon processes. The presence of sharp corners will lead to the concentration of electrical and mechanical stress, becoming a potential failure point for the capacitor, thus affecting its reliability and service life. Summary of the invention
[0008] The purpose of the present invention is to provide a deep trench silicon capacitor structure to solve the problems existing in the above-mentioned prior art. By setting a trench structure with equal width on a silicon substrate, the formation of sharp corners at the bottom of the trench structure is reduced or avoided, and the concentration of electrical stress and mechanical stress is reduced, thereby improving the manufacturing quality and performance stability of the capacitor.
[0009] To achieve the above object, the present invention provides the following solutions:
[0010] The present invention provides a deep trench silicon capacitor structure, comprising a silicon substrate, an insulating dielectric layer, a conductive dielectric layer and a metal layer, wherein the silicon substrate is provided with a trench pattern, the trench pattern comprises at least one unit cell, and the unit cell comprises a trench structure with equal width; the insulating dielectric layer covers the bottom, sidewalls and the surface of the silicon substrate outside the trench structure; the conductive dielectric layer fills the trench structure covered with the insulating dielectric layer; and the metal layer connects the conductive dielectric layer.
[0011] In one embodiment, a ratio of the depth to the width of the trench structure is greater than 10:1.
[0012] In one embodiment, the insulating dielectric layer includes at least one layer of dielectric material with a dielectric constant of 3-20.
[0013] In one embodiment, the dielectric material includes silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide.
[0014] In one embodiment, the conductive medium layer is made of a conductive material having a resistivity of less than 0.003 Ω·cm.
[0015] In one embodiment, the conductive material is single crystal silicon or polycrystalline silicon doped with boron or phosphorus impurities.
[0016] In one embodiment, the metal material used for the metal layer includes at least one of Al, TiW, Ni, Au, AlSiCu and W.
[0017] In one embodiment, the unit cell is a first unit cell having a first groove structure, wherein the first groove structure includes transverse grooves and longitudinal grooves, wherein the transverse grooves are parallel to each other, and the longitudinal grooves are parallel to each other, and in the transverse direction, the length of the transverse grooves is consistent with the width of the longitudinal grooves, and in the longitudinal direction, the width of the transverse grooves is consistent with the length of the longitudinal grooves.
[0018] In one embodiment, the ends of adjacent transverse grooves are connected by a first arc transition, the width of the first arc is consistent with the width of the transverse groove, and the ends of adjacent longitudinal grooves are connected by a second arc transition, the width of the second arc is consistent with the width of the longitudinal groove.
[0019] In one embodiment, the unit cell is a second unit cell having a second groove structure, the second groove structure is distributed in the form of a regular polygon, and the second groove structure is an annular groove.
[0020] Compared with the prior art, the present invention has achieved the following technical effects:
[0021] The present invention arranges a groove structure on a silicon substrate, and the width of the groove structure is equal, so that the groove depth after etching is uniform and the bottom morphology is flat, the formation of sharp corners at the bottom of the groove structure is reduced or avoided, the electrical stress and mechanical stress concentration are reduced, the capacitance value accuracy and the electrical breakdown strength are effectively controlled and improved, and the manufacturing quality and performance stability of the capacitor are improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 A schematic diagram of a deep trench silicon capacitor structure in an embodiment of the present invention;
[0024] Figure 2 A top view of the silicon substrate of the deep trench silicon capacitor structure after etching according to the first embodiment of the present invention;
[0025] Figure 3 A top view of a silicon substrate of a deep trench silicon capacitor structure after etching according to a second embodiment of the present invention;
[0026] Figure 4 for Figure 3 Section II of the middle annular groove;
[0027] Figure 5 It is a schematic diagram of the sharp corner where the groove width suddenly changes (transitions);
[0028] Figure 6 This is a schematic diagram of the flat state of the groove bottom when the groove width is uniform;
[0029] Among them, 1. silicon substrate; 2. insulating dielectric layer; 3. conductive dielectric layer; 4. metal layer;
[0030] 110, first silicon substrate; 120, first trench structure; 121, first unit cell;
[0031] 210, second silicon substrate; 220, second trench structure; 221, second unit cell;
[0032] 231, a first silicon oxide layer; 232, a silicon nitride layer; 233, a second silicon oxide layer; 240, a polysilicon layer. DETAILED DESCRIPTION
[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0034] The purpose of the present invention is to provide a deep trench silicon capacitor structure to solve the problems existing in the prior art. By setting a trench structure with equal width on a silicon substrate, the formation of sharp corners at the bottom of the trench structure can be reduced or avoided, and the concentration of electrical stress and mechanical stress can be reduced, thereby improving the manufacturing quality and performance stability of the capacitor.
[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0036] like Figure 1 to Figure 4As shown, the present invention provides a deep trench silicon capacitor structure, including a silicon substrate 1, an insulating dielectric layer 2, a conductive dielectric layer 3 and a metal layer 4, the silicon substrate 1 is provided with a groove pattern, the groove pattern includes at least one unit cell, one or more unit cells are arranged and combined to form a groove pattern, and when arranged and combined, a method of radiating distribution from the center to the surroundings can be adopted, or a matrix distribution method can be adopted. The unit cell includes a groove structure in a certain shape, and the groove structure can be a triangle, a quadrilateral, a wave shape, or an irregular shape, or a combination of different shapes. No matter which shape of the groove structure is adopted, the width of the groove structure remains equal everywhere, so that no sudden change in width is formed on the extension path of the groove, and the generation of sharp corners at the bottom of the groove structure caused by the width change is reduced or reduced. The sharp corners are mainly generated at the sudden change or transition of the width of the groove, and the generation of the sharp corners has no direct relationship with the absolute width of the groove. Therefore, according to the etching means adopted, the width of the groove can be made as small as possible, so that more groove structures can be etched on the silicon substrate 1 to increase the capacity of the capacitor. Due to the use of a groove structure with uniform width, when etching the groove structure on the silicon substrate 1, a groove structure with uniform depth and smooth bottom morphology can be obtained. The insulating dielectric layer 2 covers the bottom, sidewalls and surface of the silicon substrate 1 outside the groove structure. The outer layer of the insulating dielectric layer 2 is covered with a conductive dielectric layer 3, and the conductive dielectric layer 3 fills the groove structure covered with the insulating dielectric layer 2. The metal layer 4 is connected to the conductive dielectric layer 3, and the metal layer 4 is connected to both ends of the circuit. When connecting the circuit, it can be connected to the circuit by bonding wires or mounting to ensure the effective extraction of the capacitor.
[0037] The present invention sets a groove structure on the silicon substrate 1, and the width of the groove structure is equal, so that the groove depth after etching is uniform and the bottom morphology is flat (such as Figure 6 ), reducing or avoiding the sharp corners at the bottom of the groove structure (such as Figure 5 The formation of the structure shown in the figure reduces the electrical stress and mechanical stress concentration, the capacitance value accuracy and electrical breakdown strength are effectively controlled and improved, and the manufacturing quality and performance stability of the capacitor are improved.
[0038] In one embodiment, the ratio of the depth to the width of the trench structure is greater than 10:1 to achieve high capacitance density.
[0039] In one embodiment, the insulating dielectric layer 2 includes at least one layer of dielectric material with a dielectric constant of 3 to 20, and the dielectric materials used in each layer may be the same or different.
[0040] In one embodiment, the dielectric material includes dielectric materials with a dielectric constant of 3 to 20, such as silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide, and the insulating dielectric layer 2 may be a combination of one or more of these dielectric materials.
[0041] In one embodiment, the conductive medium layer 3 is made of a conductive material having a resistivity of less than 0.003 Ω·cm.
[0042] In one embodiment, the conductive material is single crystal silicon or polycrystalline silicon doped with boron or phosphorus impurities.
[0043] In one embodiment, the metal material used for the metal layer 4 includes at least one of Al, TiW, Ni, Au, AlSiCu and W, and can be a single type or a combination of any two or more types.
[0044] In one embodiment, if Figure 2 As shown, the unit cell is a first unit cell 121 having a first groove structure 120, and the first groove structure 120 is etched on the first silicon substrate 110. The first groove structure 120 includes a transverse groove and a longitudinal groove, and the transverse groove and the longitudinal groove are only different in relative direction. The transverse groove and the longitudinal groove are perpendicular to each other, the transverse grooves are parallel to each other, and the longitudinal grooves are parallel to each other. As the transverse groove and the longitudinal groove extend, the two can be connected, and it should be noted that: the width of the transverse groove and the longitudinal groove is consistent, and is consistent with the width of the connection. A plurality of transverse grooves and a plurality of longitudinal grooves are combined into the first groove structure 120. In the transverse direction, the length of the transverse groove is consistent with the width of the longitudinal groove distribution, and in the longitudinal direction, the width of the transverse groove distribution is consistent with the length of the longitudinal groove. Thus, the first groove structure 120 can form a rectangular or square first unit cell 121, which is convenient for expansion into the plane to form a groove pattern.
[0045] In one embodiment, the ends of adjacent transverse grooves are connected by a first arc transition, the width of the first arc is consistent with the width of the transverse groove, and the ends of adjacent longitudinal grooves are connected by a second arc transition, the width of the second arc is consistent with the width of the longitudinal groove, and the width of the first arc transition is consistent with the width of the second arc transition. Therefore, the first groove structure 120 has the same groove width at each location.
[0046] In one embodiment, if Figure 3 and Figure 4 As shown, the unit cell is a second unit cell 221 having a second groove structure 220, and the second groove structure 220 is etched on the second silicon substrate 210. The second groove structure 220 is distributed in the form of a regular polygon, and the regular polygon can be a regular triangle, a square, etc. The second groove structure 220 adopts an annular groove, and the width of the annular groove is equal everywhere. The second groove structure 220 can form a second unit cell 221 with a regular polygon, which is convenient for expanding into the plane to form a groove pattern.
[0047] In one implementation, namely the first embodiment, as Figure 2As shown, a first groove structure 120 is designed and etched on the first silicon substrate 110. The first groove structure 120 is composed of a first unit cell 121 repeatedly combined multiple times. The grooves in the first unit cell 121 are located between several parallel horizontal strips (horizontal grooves) and between several parallel vertical strips (vertical grooves), and arc patterns are selectively added at the ends of the horizontal strips and the vertical strips to ensure that the spacing size of each position of the groove is consistent. The grooves can be made by a single etching process during the manufacturing process. The horizontal strips and the vertical strips are arranged at intervals. After etching, the first silicon substrate 110 has sufficient structural strength to meet the needs of subsequent processes.
[0048] The number of continuous horizontal strips in the first unit cell 121 is 7, the number of continuous vertical strips is 7, adjacent horizontal strips, adjacent vertical strips, and adjacent horizontal strips and vertical strips are arranged equidistantly with the width of the designed groove. The 7 continuous horizontal strips and the 7 adjacent continuous vertical strips in the first unit cell 121 have the same size in the same axis (horizontal or vertical), and the first unit cell 121 is a square.
[0049] The first unit cells 121 are distributed radially outward from the center of the first silicon substrate 110 , so that the first trench structures 120 are evenly distributed on the first silicon substrate 110 .
[0050] The first silicon substrate 110 of this embodiment is a square plate, and those skilled in the art can understand that its shape is not limited to this. It can be understood that the arrangement of the first groove structure 120 on the first silicon substrate 110 is not limited to the situation given in this embodiment. The number of continuous parallel horizontal strips in the first unit cell 121 is between 1 and x, x is any positive integer, the number of continuous parallel vertical strips is between 1 and y, y is any positive integer, and adjacent horizontal strips, adjacent vertical strips, and adjacent horizontal strips and vertical strips are arranged equidistantly with the width of the designed groove. The continuous x horizontal strips and the adjacent continuous y horizontal strips on the same axis in the first unit cell 121 are the same size, that is, the first unit cell 121 is a rectangle or square, which is convenient for array expansion.
[0051] In the first embodiment of the present invention, after completing Figure 2 After the groove pattern shown is etched, the following steps are performed in sequence:
[0052] Growth and deposition of insulating dielectric layer 2 (such as dielectric film material);
[0053] The conductive dielectric layer 3 (such as conductive polysilicon) fills the trench structure;
[0054] The metal layer 4 (eg, conductive metal) is deposited and tested and used as a top electrode.
[0055] The deep trench silicon capacitor structure manufactured by this embodiment has the trenches etched with equal dimensions everywhere, so that the bottom of the trench is flat, thereby improving the capacitance accuracy of the deep trench capacitor and meeting the electrical breakdown strength requirements.
[0056] In one embodiment, namely the second embodiment, as Figure 3 and Figure 4 As shown, a second groove structure 220 is designed and etched on the second silicon substrate 210. The second groove structure 220 is composed of multiple repeated combinations of second unit cells 221. The groove in the second unit cell 221 is located in a closed area surrounded by inner and outer contour lines. The inner and outer contour lines are both the circumference of a circle, and their centers coincide with each other. Therefore, the groove width is equal to the difference between the outer circle radius and the inner circle radius.
[0057] The second silicon substrate 210 of this embodiment is a square, and those skilled in the art will appreciate that its shape is not limited thereto. The inner and outer contours of the second unit cell 221 may be polygonal or other shapes or a combination of the two, and the edges of the polygonal and the shapes may be chamfered.
[0058] A plurality of second unit cells 221 are arranged in the form of regular polygons on the second silicon substrate 210, that is, in the groove pattern composed of the plurality of second unit cells 221, a regular polygon with the predetermined number of sides is formed between the center points of each predetermined number of second unit cells 221. Further, in this embodiment, the plurality of second unit cells 221 are arranged in the form of regular triangles, that is, in the groove pattern, the center points of each three non-collinear second unit cells 221 form a regular triangle. Further, the plurality of second unit cells 221 are arranged radially outward from the center of the second silicon substrate 210, and the minimum spacing between the outer contour lines of each second unit cell 221 remains equal, so that the second groove structure 220 is evenly distributed on the second silicon substrate 210.
[0059] According to the second embodiment of the present invention, the second groove structure 220 provided on the second silicon substrate 210 includes: an etched area (annular groove) surrounded by inner and outer contour lines with the same center point in the second unit cell 221, a substrate silicon column surrounded by the inner contour, and the second unit cells 221 are arranged in the form of an equilateral triangle on the second silicon substrate 210, wherein the etched areas between the inner and outer contour lines of multiple second unit cells 221 can be manufactured by a single etching process during the manufacturing process of the second silicon substrate 210, and in the equilateral triangle arrangement, the annular holes etched between the inner and outer contour lines of the second unit cells 221 maintain the structural strength of the second silicon substrate 210 to meet the needs of subsequent processes.
[0060] In the second embodiment of the present invention, after completing Figure 3 After the groove pattern shown is etched, the following steps are performed in sequence:
[0061] Growth and deposition of insulating dielectric layer 2 (such as dielectric film material);
[0062] The conductive dielectric layer 3 (such as conductive polysilicon) fills the trench structure;
[0063] The metal layer 4 (eg, conductive metal) is deposited and tested and used as a top electrode.
[0064] The deep trench silicon capacitor structure manufactured by this embodiment has the trenches etched with equal dimensions everywhere, so that the bottom of the trench is flat, thereby improving the capacitance accuracy of the deep trench capacitor and meeting the electrical breakdown strength requirements.
[0065] like Figure 4 As shown, the bottom of the groove has a smooth transition, and the deposited insulating dielectric layer 2 (comprising a first silicon oxide layer 231, a silicon nitride layer 232 and a second silicon oxide layer 233) and a conductive dielectric layer 3 (polysilicon layer 240) are of good quality, thus avoiding the generation of defects, thereby effectively improving the electrical breakdown strength of the deep trench capacitor product.
[0066] The present invention uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.
Claims
1. A deep trench silicon capacitor structure, characterized in that: include: A silicon substrate, wherein the silicon substrate is provided with a groove pattern, wherein the groove pattern includes at least one unit cell, and the unit cell includes a groove structure with equal width; An insulating dielectric layer, wherein the insulating dielectric layer covers the bottom and sidewalls of the trench structure and the surface of the silicon substrate outside the trench structure; A conductive dielectric layer, wherein the conductive dielectric layer fills the groove structure covered with the insulating dielectric layer; and a metal layer, wherein the metal layer is connected to the conductive medium layer.
2. The deep trench silicon capacitor structure according to claim 1, characterized in that: The ratio of the depth to the width of the groove structure is greater than 10:
1.
3. The deep trench silicon capacitor structure according to claim 1, characterized in that: The insulating dielectric layer includes at least one layer of dielectric material with a dielectric constant of 3-20.
4. The deep trench silicon capacitor structure according to claim 3, characterized in that: The dielectric material includes silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.
5. The deep trench silicon capacitor structure according to claim 1, characterized in that: The conductive medium layer is made of a conductive material with a resistivity below 0.003Ω·cm.
6. The deep trench silicon capacitor structure according to claim 5, characterized in that: The conductive material is single crystal silicon or polycrystalline silicon doped with boron or phosphorus impurities.
7. The deep trench silicon capacitor structure according to claim 1, characterized in that: The metal material used for the metal layer includes at least one of Al, TiW, Ni, Au, AlSiCu and W.
8. The deep trench silicon capacitor structure according to claim 1, characterized in that: The unit cell is a first unit cell having a first groove structure, wherein the first groove structure includes transverse grooves and longitudinal grooves, wherein the transverse grooves are parallel to each other, and the longitudinal grooves are parallel to each other. In the transverse direction, the length of the transverse grooves is consistent with the width of the longitudinal grooves, and in the longitudinal direction, the width of the transverse grooves is consistent with the length of the longitudinal grooves.
9. The deep trench silicon capacitor structure according to claim 8, characterized in that: The ends of the adjacent transverse grooves are connected by a first arc transition, the width of the first arc is consistent with the width of the transverse groove, and the ends of the adjacent longitudinal grooves are connected by a second arc transition, the width of the second arc is consistent with the width of the longitudinal groove.
10. The deep trench silicon capacitor structure according to claim 1, characterized in that: The unit cell is a second unit cell having a second groove structure, the second groove structure is distributed in the form of a regular polygon, and the second groove structure is an annular groove.