A satellite analog signal acquisition system

Abstract

The present invention discloses a satellite analog signal acquisition system, comprising a channel selection unit, a filtering unit, an AD conversion unit and a control unit. The channel selection unit is communicatively connected to the control unit, and is used to select an analog signal channel to be acquired according to an instruction of the control unit, and comprises at least one primary selection unit and a secondary selection unit, the filtering unit is connected to the output end of the secondary selection unit, and performs a filtering operation on the signal in the selected analog signal channel, the AD conversion unit is connected to the output end of the filtering unit, and performs analog-to-digital conversion on the filtered signal, the control unit is communicatively connected to the CPU, and comprises a data buffer area and a control logic, the data buffer area is communicatively connected to the AD conversion unit, and is used to cache the analog-to-digital conversion result of the filtered signal, the control logic is communicatively connected to the channel selection unit and the AD conversion unit, and is used to select and switch the analog signal channel to be acquired, and control the AD conversion unit.

Description

Technical Field

[0001] The invention relates to the field of aerospace technology, and in particular to a satellite simulation signal acquisition system. Background Art

[0002] For satellites, the acquisition of analog signals is an essential operation for each subsystem, and each satellite subsystem has high requirements for the quantity and accuracy of analog signal acquisition.

[0003] At present, there are generally two ways to collect analog signals. One is the processor direct collection method. This method has a simple hardware interface circuit. If a processor with high functional integration is selected during design, that is, a processor with integrated AD function is selected, the analog signal can be directly collected. However, the number of analog signals that can be collected by this method is limited, and it is difficult to meet the satellite's demand for the number of collection of analog signals such as attitude control subsystems, energy subsystems, and thermal control subsystems. If the number of collection channels needs to be increased, it is necessary to increase the number of collection channels by adding multiple switches. Even if the limitation of the number requirements is solved, the sampling accuracy of the AD conversion chip integrated in the CPU cannot meet the demand for higher sampling accuracy. At the same time, when the CPU performs switch selection and sampling, it also occupies the CPU resources, reducing the CPU utilization efficiency; the other method uses a processor plus an AD converter to realize the collection of analog signals. At present, the satellite's onboard computer mostly uses this method. This method also requires the use of a multiplexer to increase the number of collection channels. Its advantage is that it can select an AD converter that meets the sampling schedule according to the needs, which meets both the quantity requirements and the accuracy requirements. However, when the CPU is performing switch selection and sampling, it occupies CPU resources, especially in centralized control systems. There are at least 100 analog signal acquisition channels. If smoothing is added, there are nearly 1,000 channels, which will greatly reduce the CPU utilization efficiency and thus affect the performance of the satellite. Summary of the invention

[0004] Based on some or all of the problems in the prior art, the present invention provides a satellite simulation signal acquisition system, comprising:

[0005] A channel selection unit, which is communicatively connected to the control unit and is used to select an analog signal channel according to an instruction of the control unit, comprising:

[0006] at least one primary selection unit, whose input terminal is connected to the analog signal channel to be collected; and

[0007] a secondary selection unit, whose input end is connected to the output end of the primary selection unit;

[0008] A filtering unit connected to the output end of the secondary selection unit and configured to perform a filtering operation on the signal in the selected analog signal channel;

[0009] An AD conversion unit connected to the output end of the filtering unit and used for performing analog-to-digital conversion on the filtered signal; and

[0010] A control unit, which is communicatively connected to the CPU, comprises:

[0011] a data buffer area, which is communicatively connected to the AD conversion unit and is used to buffer the analog-to-digital conversion result of the filtered signal; and

[0012] The control logic is communicatively connected to the channel selection unit and the AD conversion unit, and is used for selecting and switching channels, and controlling the AD conversion unit.

[0013] Furthermore, the analog signal channels to be collected include voltage signal channels and temperature measurement signal channels.

[0014] Furthermore, the acquisition system also includes a reference source and a reference resistor, and the reference source and the reference resistor are connected between the temperature measurement signal channel and the channel selection unit.

[0015] Furthermore, the reference source voltage is 5V, and the reference resistor is 20KΩ.

[0016] Further, any of the first-level selection units includes at least one first analog electronic switch, and the second-level selection unit includes at least one second analog electronic switch, wherein the input end of any of the first analog electronic switches is connected to the analog signal channel to be collected and the control logic, and the output end is connected to the input end of the second analog electronic switch, the input end of the second analog electronic switch is also connected to the subsystem reference ground and the control logic, and the output end is connected to the filtering unit to output a differential signal.

[0017] Further, the AD conversion unit includes at least one AD converter, wherein the number of the AD converters is the same as the number of the second analog electronic switches.

[0018] Furthermore, the AD conversion unit includes two AD converters.

[0019] Furthermore, the control unit includes an FPGA, which is communicatively connected to the CPU via an IO bus.

[0020] The present invention provides a satellite analog signal acquisition system, which uses an independent control unit to realize analog signal acquisition and AD conversion. The CPU only configures parameters when the system is powered on, and reads signals after signal acquisition is completed. The remaining key operations, such as channel selection, waiting for signal stability, signal smoothing, AD conversion, etc., are all controlled by the control unit, which greatly reduces the consumption of CPU resources for analog signal acquisition, significantly improves the use efficiency of the CPU, thereby improving the safety and reliability of the software and ensuring the safety and reliability of the satellite. In addition, the control unit can also configure the number of smoothing times of the analog signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0022] Figure 1 A schematic diagram showing the structure of a satellite simulation signal acquisition system according to an embodiment of the present invention;

[0023] Figure 2 A schematic diagram showing the architecture of a control unit according to an embodiment of the present invention;

[0024] Figure 3 A schematic diagram showing the structure of a channel selection unit according to an embodiment of the present invention;

[0025] Figure 4 A schematic diagram showing the circuit structure of a channel selection unit according to an embodiment of the present invention; and

[0026] Figure 5 A schematic diagram showing the circuit structure of a filter unit and an AD conversion unit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0027] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.

[0028] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0029] It should be noted that the embodiments of the present invention describe the process steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0030] In the existing satellite design, the processor plus AD conversion chip is often used to realize analog signal acquisition, and a multi-way switch is used to increase the number of acquisitions. Although it can meet the number and accuracy requirements of analog quantity acquisition, it occupies more CPU resources and affects the performance of the satellite. This is mainly because the analog signals of the satellite are mostly slow variables. Therefore, a low-pass filter is usually required before AD acquisition. Normally, the stability of the acquisition signal requires about 150uS, the multi-way switch requires 20uS, and the AD conversion time of the AD converter is 30uS. Therefore, each AD sampling requires about 200uS. For small satellites, their analog acquisition signals include about 100 channels of thermal sensors and 50 channels of analog quantities that are smoothed 10 times for attitude control, which makes the overall acquisition time take 120mS. For the small satellite service software controlled at 4Hz, the software cycle is only 250mS. The time spent on analog signal acquisition obviously consumes too much processor resources, leaving too little time for processor operation, logic management, and task scheduling, which adds pressure and risks to the subsequent application software operation. The inventor found through research that in the process of analog signal acquisition, the CPU has clear steps such as channel selection, waiting for signal stability, and waiting for acquisition conversion to be completed, and the waiting time is relatively fixed. Based on this, in order to reduce the time spent by the CPU on analog signal acquisition while ensuring the accuracy of analog signal acquisition, the present invention provides a satellite analog signal acquisition system, which hands over some time-consuming logic management functions to an independent control unit to implement, so that the CPU only needs to configure parameters and read results. The independent control unit can be an FPGA, which can realize channel selection and signal smoothing, and put the acquisition results and DA output into the agreed CPU address space. During this period, the CPU does not need to wait and can perform other calculations or operations until the CPU needs analog signal information. It reads the AD conversion result and the required attitude control analog signal smoothing result from the control unit. The reading time is less than 200uS, which greatly reduces the consumption of CPU resources for analog signal acquisition and significantly improves the CPU utilization efficiency, thereby improving the safety and reliability of the software and ensuring the safety and reliability of the satellite. In addition, the number of smoothing times of the analog signal and the number of analog signal smoothing paths can be configured by software.

[0031] The scheme of the present invention is further described below in conjunction with the accompanying drawings of the embodiments.

[0032] Figure 1 FIG. 2 is a schematic diagram showing the structure of a satellite simulation signal acquisition system according to an embodiment of the present invention. Figure 1 As shown, a satellite analog signal acquisition system includes a channel selection unit 101, a filtering unit 102, an AD conversion unit 103 and a control unit 104.

[0033] The control unit includes a data buffer 141, a control logic 142, and an interface control logic 143, wherein the data buffer 141 is communicatively connected to the AD conversion unit 103 to cache the analog-to-digital conversion result, so that the CPU can read the conversion structure later; the control logic 142 is communicatively connected to the channel selection unit 101 and the AD conversion unit 103 to generate a channel selection signal according to the parameter configuration of the CPU, select and switch channels, and control the AD conversion unit; the interface control logic 143 is used to provide an interface with an external bus; in one embodiment of the present invention, the control unit 104 includes an FPGA. Taking a system including two AD converters as an example, Figure 2 FIG. 2 is a schematic diagram showing the architecture of a control unit according to an embodiment of the present invention. Figure 2 As shown, the control unit 104 is implemented by FPGA, and the FPGA includes a channel number dual port 201, an acquisition state machine 202, data dual ports 231, 232, a user dual port 204, a state transfer machine 205, and a latch and signal generation 206. The working process of the FPGA is as follows: the CPU writes the analog switch channel number corresponding to the channel to the channel number dual port 201 inside the FPGA through the IO bus, and then the acquisition state machine 202 controls the 2-way AD converter to collect and convert the data of the corresponding analog switch channel, and stores the conversion results of the 2-way AD converter in the data dual port 231 and the data dual port 232 respectively. When the analog signal information is needed, the CPU notifies the transfer state machine 205 to read the data, and the transfer state machine 205 transfers the conversion results of the currently sampled data from the data dual port 231 and the data dual port 232 to the user dual port 204 to wait for the user to read, and completes the acquisition of all analog signals waiting for the CPU to read. The latch and signal generation 206 can receive the data sent by the CPU and send it to the digital-to-analog converter for conversion and output. Since the acquisition system is applied to satellites, for safety reasons, the key registers use TMR technology, and the operation of the acquisition state machine is monitored. Table 1 shows the address allocation description of the FPGA registers and IO ports.

[0034]

[0035]

[0036] Table 1

[0037] The channel selection unit 101 is communicatively connected to the control logic 142 for receiving a channel selection signal and then selecting an analog signal channel to be collected according to the channel selection signal. Figure 3 FIG. 2 is a schematic diagram showing the structure of a channel selection unit according to an embodiment of the present invention. Figure 3As shown, for a satellite, the analog signals to be collected usually include voltage and temperature, which can be differentially input to the AD converter for conversion through an analog switch. Therefore, the channel selection unit 101 includes two-stage selection units. Among them, the first-stage selection unit 121 can be one or more, which is connected to the analog signal channel to be collected, and can receive the channel selection signal sent by the control logic, and select the corresponding analog signal channel according to the channel selection signal. In one embodiment of the present invention, an input protection circuit 123 is also provided between the first-stage selection unit 121 and the analog signal channel to be collected. There can be one or more second-stage selection units 122, any of which is connected to the output end of each corresponding first-stage selection unit 121, and can receive the channel selection signal sent by the control logic, select the analog signal and the corresponding subsystem reference ground according to the channel selection signal, and then form a differential pair of the corresponding signal channel.

[0038] The filter circuit 102 is connected to the output end of the channel selection unit 101, and is used to filter the signal in the selected analog signal channel. In one embodiment of the present invention, the filter circuit may include multiple channels, corresponding to the secondary selection units one by one.

[0039] The input end of the AD conversion unit 103 is connected to the output end of the filtering unit 102, and the output end is connected to the data buffer area 141, for performing analog-to-digital conversion on the filtered analog signal. In one embodiment of the present invention, the AD conversion unit may include multiple AD converters, and the AD converters correspond to the secondary selection units one by one.

[0040] In one embodiment of the present invention, the acquisition system further includes a digital-to-analog converter 105 and a corresponding output protection circuit 151. In another embodiment of the present invention, the acquisition system further includes an isolation amplifier 106.

[0041] In order to verify the acquisition system provided by the present invention, a certain satellite is taken as an example to specifically describe the circuit structure of the acquisition system.

[0042] In the satellite, analog quantity acquisition includes voltage quantity and temperature quantity, and there are 128 AD conversion signals in total, and the analog quantity input signal is a differential signal. Since the voltage quantity signal can directly enter the electronic switch, for the temperature quantity signal, a standard reference source and a reference resistor need to be provided, wherein the reference resistor uses a high-precision 20KΩ resistor, and the reference source is provided by AD584 through 12V voltage conversion to 5V. AD584 has a current output capacity of 10mA. In the satellite, there are 45 temperature quantities in total, and the pull-up resistor of each is 20KΩ. Therefore, from the perspective of derating design, 2 AD converters are required, and each AD converter provides a reference source for 23 of them. Since the reference resistor of each temperature quantity acquisition channel is 20KΩ and the reference source voltage is 5V, the impedance of the thermistor itself is not considered, and the maximum current consumption of each channel is 0.25mA, and the total current consumption of 23 channels is 5.75mA. At this time, considering the impedance of the thermistor itself, the derating can meet the design requirements of the first-level derating.

[0043] In view of the signal acquisition requirements of the satellite, analog switches HI1-0546 / 883 and HI1-0547 / 883 are used to form a channel selection unit 101. The input signal overvoltage capability of analog switches HI1-0546 / 883 and HI1-0547 / 883 can reach ±35V, and have excellent anti-latch function. AD converter uses AD1674, and its conversion process control and switching design between channels are implemented with FPGA. The hardware controls the switch selection state in an interlocking manner, and the reset state selects two channels, waiting for the CPU start signal to convert.

[0044] Figure 4 FIG. 2 is a schematic diagram showing a circuit structure of a channel selection unit according to an embodiment of the present invention. Figure 4As shown, the first-level selection unit 121 is composed of analog switches HI1-0546 / 883, which select the corresponding analog signal channel; the second-level selection unit 122 is composed of HI1-0547 / 883, which can select the analog signal and the corresponding subsystem reference ground at the same time, forming a differential pair of the corresponding signal channel, and after passing through the filtering unit, analog-to-digital conversion is performed, wherein the channel selection control signal is generated by the control unit. In the process of channel selection, FPGA only needs to output CH1-CH8 and CHEN1-CHEN8, and the system initial state must ensure that these signals are all 0. After initialization is completed, the channel automatically selects two analog quantities. Among them, CH4, CH3, CH2, CH1 and CHEN4, CHEN3, CHEN2, CHEN1 are input to the enable port of the first-level selection unit 121, which is responsible for selecting all channels of the two AD converters; CHEN8, CHEN7, CHEN6, CHEN5 are input to the enable port of the second-level selection unit 122 corresponding to the second AD converter, and CH8, CH7, CH6, CH5 are input to the enable port of the second-level selection unit 122 corresponding to the first AD converter, which is responsible for selecting the subsystem differential ground corresponding to each channel.

[0045] Figure 5 FIG. 1 is a schematic diagram showing the circuit structure of a filter unit and an AD conversion unit according to an embodiment of the present invention. Figure 5 As shown, the output of the secondary selection unit 122 is filtered by the filter unit and amplified by the isolation amplifier, and then input into the AD converter. The AD converter performs data conversion according to the control signal sent by the FPGA. The filter unit includes an amplifier AD620 and a resistor, and the isolation amplifier includes an operational amplifier OP27 and corresponding peripheral circuits. The AD converter adopts AD1674, which is controlled by the FPGA in a full control mode. The AD conversion result is stored in the FPGA and waits for the CPU to read.

[0046] The present invention provides a satellite analog signal acquisition system, which uses FPGA to realize the acquisition of analog signals. After the system is powered on, the CPU performs parameter configuration. After the configuration is completed, the CPU does not need to participate. The FPGA manages the AD converter, including acquisition logic, waiting time, smoothing number control, etc. The CPU does not need to wait, but only needs to read the conversion result of the collected analog signal when needed. It has the characteristics of intelligence, high efficiency, reliability, etc. At the same time, the acquisition system can smooth the signals of all analog channels, and the number of smoothing measurements can be 1 to 16 times, and the smoothing result is directly given.

[0047] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A satellite simulation signal acquisition system, characterized in that: include: Two groups of channel selection units are communicatively connected to the control unit and are configured to select analog signal channels to be collected according to instructions of the control unit, wherein each group of channel selection units includes: Four first-level selection units, whose input terminals are connected to the analog signal channels to be collected, and only the corresponding analog signal channels are selected; and a secondary selection unit, whose input end is connected to the output end of the primary selection unit, which simultaneously selects the analog signal and the corresponding subsystem reference ground to form a differential pair of the corresponding analog signal channel, wherein the instruction includes CH1 to CH8 and CHEN1 to CHEN8, wherein CH4, CH3, CH2, CH1 and CHEN4, CHEN3, CHEN2, CHEN1 are configured to select all channels of the two AD converters, and CHEN8, CHEN7, CHEN6, CHEN5, CH8, CH7, CH6, CH5 are configured to select the subsystem differential ground corresponding to each channel; Two groups of filter units, each group of filter units is connected to the output end of a secondary selection unit, and is configured to perform filtering operations on the signals in the selected analog signal channel; An AD conversion unit, comprising two AD converters, the input ends of the two AD converters are respectively connected to the output end of one of the filtering units, and is configured to perform analog-to-digital conversion on the filtered signal; and A control unit is implemented by an FPGA, wherein the FPGA is communicatively connected to a CPU via an IO bus, and comprises a channel number dual port, an acquisition state machine, a data dual port, a user dual port, a state transport machine, a latch and a signal generation, wherein the CPU is configured to write the analog switch channel number corresponding to the channel to the channel number dual port via the IO bus, the acquisition state machine is configured to control the AD conversion unit to perform data acquisition and conversion on the corresponding analog switch channel, and store the conversion result of the AD conversion unit in the data dual port, the transport state machine is configured to read data when receiving a CPU notification that analog signal information is required, then transport the conversion result of the currently sampled data from the data dual port to the user dual port to wait for the user to read, complete the acquisition of all analog signals and wait for the CPU to read, and the latch and signal generation are configured to receive the data sent by the CPU, and send it to the digital-to-analog converter for conversion and output.

2. The acquisition system according to claim 1, characterized in that: The analog signal channels to be collected include voltage signal channels and temperature measurement signal channels.

3. The acquisition system according to claim 2, characterized in that: The acquisition system also includes a reference source and a reference resistor, and the reference source and the reference resistor are connected between the temperature measurement signal channel and the channel selection unit.

4. The acquisition system according to claim 3, characterized in that: The reference source voltage is 5V, and the reference resistor is 20KΩ.

5. The acquisition system according to claim 1, characterized in that: Any of the primary selection units includes at least one first analog electronic switch, and the secondary selection unit includes a second analog electronic switch, wherein: An input end of any one of the first analog electronic switches is connected to the analog signal channel to be collected and the control logic, and an output end is connected to the input end of the second analog electronic switch; and The input end of the second analog electronic switch is connected to the output end of the first analog electronic switch, the subsystem reference ground and the control logic, and the output end is connected to the filter unit to output a differential signal.

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