Hybrid Memory

Abstract

The present invention discloses a hybrid memory, comprising a memory array, a word line decoder, an intermediate circuit and a read-write circuit, wherein the word line decoder is electrically coupled to the memory array, the intermediate circuit is electrically coupled to the memory array, and the read-write circuit is electrically coupled to the intermediate circuit. The memory array comprises a plurality of hybrid memory cells. Each hybrid memory cell comprises a read-write element group, a storage circuit and a selection circuit. The read-write element group is electrically coupled to a word line and two bit lines. The word line controls the conduction or disconnection of the read-write element group, and the two bit lines transmit two data signals respectively. The storage circuit is used to generate two read response signals according to a read drive signal. The selection circuit is electrically coupled to the storage circuit, and is used to control the storage circuit to present a volatile or non-volatile storage mode according to a selection voltage.

Description

Technical Field

[0001] The present invention relates to a memory, and in particular to a hybrid memory. Background Art

[0002] Static random access memory (SRAM) is a type of random access memory. The so-called static means that the data stored in it can be kept constant as long as the power is kept on. In contrast, the data stored in dynamic random access memory (DRAM) will be updated periodically. Compared with DRAM, SRAM has advantages such as fast speed and low power consumption. However, when the power supply stops, whether it is SRAM or DRAM, the data stored will disappear, so it is called volatile memory. Summary of the invention

[0003] In view of the above, the present invention provides a hybrid memory.

[0004] A hybrid memory according to one embodiment of the present invention includes a memory array, a word line decoder, an intermediate circuit and a read-write circuit, wherein the word line decoder is electrically coupled to the memory array, the intermediate circuit is electrically coupled to the memory array, and the read-write circuit is electrically coupled to the intermediate circuit. The memory array includes a plurality of hybrid memory cells. Each hybrid memory cell includes a read-write element group, a storage circuit and a selection circuit. The read-write element group is electrically coupled to a word line and two bit lines, wherein the word line controls the conduction or disconnection of the read-write element group, and the two bit lines transmit two data signals respectively. The storage circuit is used to generate two read response signals according to a read drive signal. The selection circuit is electrically coupled to the storage circuit, and is used to control the storage circuit to present a volatile storage mode or a non-volatile storage mode according to a selection voltage.

[0005] With the above structure, the hybrid memory disclosed in the present case includes an array composed of a plurality of hybrid memory cells, each of which can be set to a volatile storage mode or a non-volatile storage mode as required, and has high adaptability. By adjusting the setting of the selection voltage corresponding to each hybrid memory cell, the hybrid memory can be used with a variety of computing devices or other electronic devices with different requirements for storage modes without changing the circuit design of the memory, thereby reducing development costs.

[0006] The above description of the present disclosure and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of the present invention, and to provide further explanation of the claims of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a circuit diagram of a hybrid memory cell according to an embodiment of the present invention.

[0008] Figure 2 It is a schematic diagram of electrical coupling terminals of a hybrid memory cell according to an embodiment of the present invention.

[0009] Figure 3 An equivalent circuit diagram of a volatile storage mode of a hybrid memory cell according to an embodiment of the present invention is shown.

[0010] Figure 4 An equivalent circuit diagram of a hybrid memory cell in a non-volatile storage mode is shown according to an embodiment of the present invention.

[0011] Figure 5 is a circuit diagram of a hybrid memory cell according to another embodiment of the present invention.

[0012] Figure 6 is a block diagram of a hybrid memory according to an embodiment of the present invention.

[0013] Figure 7 It is a partial circuit diagram of a hybrid memory according to an embodiment of the present invention.

[0014] Figure 8 is a block diagram of a hybrid memory according to another embodiment of the present invention.

[0015] Fig. 9 FIG. 4 is a circuit diagram of a reference unit of a hybrid memory according to another embodiment of the present invention.

[0016] Description of reference numerals:

[0017] 1.1' Hybrid storage

[0018] 11.11' Hybrid memory cell

[0019] 13 Intermediary Circuit

[0020] 15 Read and write circuit

[0021] 17 Word Line Decoder

[0022] 19 Reference Units

[0023] 21 Reference word line decoder

[0024] 111 Storage Circuit

[0025] 113 Selection Circuit

[0026] 115 Read and write component group

[0027] 117 Controller

[0028] 131 First End

[0029] 132 Second End

[0030] 133 The Third End

[0031] 134 The Fourth End

[0032] 135 The Fifth End

[0033] 136 The Sixth End

[0034] 151 Comparator

[0035] 153 Reference signal providing circuit

[0036] 155 Control Circuit

[0037] 1511 First input

[0038] 1512 Second input

[0039] 1513 Output

[0040] R1 First variable resistor

[0041] R2 Second variable resistor

[0042] M1 first transistor

[0043] M2 Second transistor

[0044] M3 The third transistor

[0045] M4 The fourth transistor

[0046] M5 Fifth transistor

[0047] M6 Sixth transistor

[0048] BL1 First line

[0049] BL2 Second bit line

[0050] BLG Bit Line Group

[0051] BLR Reference Bit Line

[0052] WL Word Line

[0053] WLR Reference Word Line

[0054] VC control voltage

[0055] VSL Select voltage

[0056] n11~n61 First end

[0057] n12~n62 Second end

[0058] n13~n63 Control terminal

[0059] SW1 First switch

[0060] SW2 Second switch

[0061] SW3 The third switch

[0062] SW4 Fourth switch

[0063] SWR Switching Element

[0064] Rref Reference variable resistor

[0065] V1 First voltage

[0066] V2 Second voltage DETAILED DESCRIPTION

[0067] The detailed features and advantages of the present invention are described in detail in the following embodiments, and the contents are sufficient to enable any person skilled in the art to understand the technical content of the present invention and implement it accordingly, and according to the contents, claims and drawings disclosed in this specification, any person skilled in the art can easily understand the relevant purposes and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but are not intended to limit the scope of the present invention in any way.

[0068] The present invention proposes a mixed-mode memory cell that can operate in multiple storage modes, including a volatile storage mode and a non-volatile storage mode. Figure 1 and Figure 2 , Figure 1 FIG. 1 is a circuit diagram of a hybrid memory cell 1 according to an embodiment of the present invention. Figure 2 A plurality of electrical coupling terminals of the hybrid memory cell 1 are exemplarily illustrated.

[0069] The hybrid memory cell 1 includes a storage circuit 111, a selection circuit 113 and a read / write element group 115. The storage circuit 111 can present a volatile storage mode or a non-volatile storage mode according to the electrical coupling status of the internal elements, that is, it can store data temporarily or permanently, wherein the composition and coupling relationship of the internal elements will be described later. In the volatile storage mode, when the power supplied to the hybrid storage cell 1 is interrupted, the data originally stored in the storage circuit 111 will disappear; and in the non-volatile storage mode, when the power supplied to the hybrid storage cell 1 is interrupted, the data stored in the storage circuit 111 will not disappear. The selection circuit 113 is electrically coupled to the storage circuit 111, and is used to control the electrical coupling status of the internal elements of the aforementioned storage circuit 111 according to the selection voltage VSL, so as to control the storage circuit 111 to present a volatile storage mode or a non-volatile storage mode. The read / write element group 115 is electrically coupled to the storage circuit 111 and the selection circuit 113, and is used to be controlled by the word line WL to transmit two write signals from two bit lines (hereinafter referred to as the first bit line BL1 and the second bit line BL2) to the storage circuit 111. The storage circuit 111 can be controlled by the selection circuit 113 as described above to store the write signals from the first and second bit lines BL1 and BL2 in a volatile storage mode or a non-volatile storage mode.

[0070] Let's further explain the components contained in each circuit, such as Figure 1 As shown, the storage circuit 111 includes two variable resistors, hereinafter referred to as the first variable resistor R1 and the second variable resistor R2, and includes two transistors, hereinafter referred to as the first transistor M1 and the second transistor M2. The first and second variable resistors R1 and R2 are used as pull-up elements, and the first transistor M1 and the second transistor M2 are used as pull-down elements. In particular, the first and second variable resistors R1 and R2 can each include a phase change element or a resistive variable element. The phase change element can be composed of a phase change material (PCM) and a conductive material (such as a metal), and the two are structurally close. When a high current passes through the conductive material, the conductive material will heat up the phase change material, and the phase state of the phase change material can be adjusted accordingly. When the phase change material is in an amorphous state, the resistance of the resistor will be higher than the resistance when the phase change material is in a crystalline state. The first and second transistors M1 and M2 can be metal oxide semiconductor field effect transistors, especially N-type metal oxide semiconductor field effect transistors (NMOS). The resistive switching element is, for example, an element generally constituting a resistive random-access memory (RRAM).

[0071] The selection circuit 113 includes a third transistor M3 and a fourth transistor M4, wherein the third and fourth transistors M3 and M4 may be metal oxide semiconductor field effect transistors, and the present invention does not limit them to be N-type or P-type. As mentioned above, the selection circuit 113 can control the electrical coupling state of the internal components of the storage circuit 111 according to the selection voltage VSL. Further, the selection circuit 113 can control the electrical coupling state between the first and second variable resistors R1 and R2 of the storage circuit 111 and the first and second transistors M1 and M2 to be conductive or non-conductive according to the selection voltage VSL. The read-write element group 115 includes a fifth transistor M5 and a sixth transistor M6, which are controlled by the word line WL to transmit the write signals from the first and second bit lines BL1 and BL2 respectively. The fifth and sixth transistors M5 and M6 may be metal oxide semiconductor field effect transistors, in particular, N-type metal oxide semiconductor field effect transistors (NMOS).

[0072] like Figure 1 and Figure 2 As shown, each resistor has two terminals, and each transistor has three terminals. For the convenience of explanation, Figure 2 The three terminals of the first transistor M1 are respectively a first terminal n11, a second terminal n12 and a control terminal n13; the three terminals of the second transistor M2 are respectively a first terminal n21, a second terminal n22 and a control terminal n23; the three terminals of the third transistor M3 are respectively a first terminal n31, a second terminal n32 and a control terminal n33; the three terminals of the fourth transistor M4 are respectively a first terminal n41, a second terminal n42 and a control terminal n43; the three terminals of the fifth transistor M5 are respectively a first terminal n51, a second terminal n52 and a control terminal n53; and the three terminals of the sixth transistor M6 are respectively a first terminal n61, a second terminal n62 and a control terminal n63.

[0073] The following is based on Figure 2 To further illustrate the electrical coupling relationship of the internal components of the storage circuit 111, as shown in the figure, the two ends of the first variable resistor R1 of the storage circuit 111 are respectively used to receive a control voltage VC and electrically coupled to the control terminal n23 of the second transistor M2; the two ends of the second variable resistor R2 are respectively used to receive the control voltage VC and electrically coupled to the control terminal n13 of the first transistor M1. The first variable resistor R1 and the second variable resistor R2 can be electrically coupled to two voltage sources that can provide the control voltage VC, or electrically coupled to the same voltage source, which is not limited by the present invention. In addition, the second ends n12 and n22 of the first and second transistors M1 and M2 are grounded.

[0074] The electrical coupling relationship between the storage circuit 111 and the selection circuit 113 is further described. The first terminal n31 of the third transistor M3 of the selection circuit 113 is electrically coupled to one terminal of the first variable resistor R1 of the storage circuit 111 and the control terminal n23 of the second transistor M2; the second terminal n32 of the third transistor M3 of the selection circuit 113 is coupled to the first terminal n11 of the first transistor M1 of the storage circuit 111; and the control terminal n33 of the third transistor M3 of the selection circuit 113 is used to receive the selection voltage VSL. Symmetrical to the coupling relationship between the third transistor M3 and the elements in the storage circuit 111, the first terminal n41 of the fourth transistor M4 of the selection circuit 113 is electrically coupled to one terminal of the second variable resistor R2 of the storage circuit 111 and the control terminal n13 of the first transistor M1; the second terminal n42 of the fourth transistor M4 of the selection circuit 113 is coupled to the first terminal n21 of the second transistor M2 of the storage circuit 111; and the control terminal n43 of the fourth transistor M4 of the selection circuit 113 is also used to receive the selection voltage VSL. The control terminal n33 of the third transistor M3 and the control terminal n43 of the fourth transistor M4 can be electrically coupled to two voltage sources capable of providing the selection voltage VSL, or electrically coupled to the same voltage source, which is not limited by the present invention. The voltage source can be driven according to the user's selection, or the hybrid memory unit 1 can further include a microprocessor or a microcontroller to drive the voltage source to provide the selection voltage VSL according to a preset selection.

[0075] Through the above coupling relationship, when the selection voltage VSL turns on the third and fourth transistors M3 and M4, the third and fourth transistors M3 and M4 can make the electrical coupling between the first and second variable resistors R1 and R2 and the first and second transistors M1 and M2 conductive, so that the storage circuit 111 is in a volatile storage mode; and when the selection voltage VSL turns off the third and fourth transistors M3 and M4, the third and fourth transistors M3 and M4 make the electrical coupling between the first and second variable resistors R1 and R2 and the first and second transistors M1 and M2 non-conductive, so that the storage circuit 111 is in a non-volatile storage mode. The voltage value of the selection voltage VSL that turns on or off the third and fourth transistors M3 and M4 can be designed by a person skilled in the art according to the types of the third and fourth transistors M3 and M4, and will not be described in detail here.

[0076] Next, the relationship between the read / write element group 115 and other circuits is further described. As shown in the figure, the first end n51 of the fifth transistor M5 of the read / write element group 115 is electrically coupled to the first end n31 of the third transistor M3 of the selection circuit 113, that is, the first end n51 of the fifth transistor M5 is also electrically coupled to the first variable resistor R1 of the storage circuit 111. The second end n52 of the fifth transistor M5 is used to be electrically coupled to the first bit line BL1, and the control end n53 is used to be electrically coupled to the word line WL. Symmetrically, the first end n61 of the sixth transistor M6 of the read / write element group 115 is electrically coupled to the first end n41 of the fourth transistor M3 of the selection circuit 113, that is, the first end n61 of the sixth transistor M6 is also electrically coupled to the first variable resistor R1 of the storage circuit 111. The second end n62 of the sixth transistor M6 is used to be electrically coupled to the second bit line BL2, and the control end n63 is used to be electrically coupled to the word line WL. When the voltage provided by the word line WL turns on the fifth and sixth transistors M5 and M6, the fifth transistor M5 can transmit the write signal from the first bit line BL1, and the sixth transistor M6 can transmit the write signal from the second bit line BL2. The voltage value that turns on the fifth and sixth transistors M5 and M6 can be designed by technicians in the field of the present invention according to the types of the fifth and sixth transistors M5 and M6, and will not be elaborated here.

[0077] The objects to which the fifth and sixth transistors M5 and M6 transmit the write signal are determined by the selection voltage VSL, and more specifically, by whether the third and fourth transistors M3 and M4 are turned on or off. Figure 1 , Figure 3 and Figure 4 ,in Figure 3 and Figure 4 The equivalent circuit diagrams of the volatile storage mode and the non-volatile storage mode of the hybrid memory cell 1 are respectively shown according to an embodiment of the present invention. Figure 3 In the implementation scenario of the volatile storage mode shown, the third and fourth transistors M3 and M4 of the selection circuit 113 are turned on according to the selection voltage VSL, so the electrical coupling between the first and second variable resistors R1 and R2 and the first and second transistors M1 and M2 can be equivalent to being electrically coupled to each other by wires. Figure 3 The equivalent circuit shown is similar to the circuit of a volatile memory, namely, a static random access memory (SRAM). In this implementation scenario, the write and read operations of the hybrid memory cell 1 are the same as those of the SRAM, and thus will not be described in detail.

[0078] At Figure 4In the implementation scenario of the non-volatile storage mode shown, the third and fourth transistors M4 and M5 of the selection circuit 113 are turned off according to the selection voltage VSL, so that the first and second transistors M1 and M2 are also turned off. In this implementation scenario, the hybrid storage unit can use the first and second variable resistors R1 and R2 to store one bit together, or the first and second variable resistors R1 and R2 can store two bits respectively. Further, in the example of storing one bit together, the first and second bit lines BL1 and BL2 can be used as complementary bit lines (BLB) and bit lines (BL), respectively, and the write signals transmitted are a set of complementary signals, including a reset signal Vreset and a set signal Vset. As mentioned above, the first and second variable resistors R1 and R2 include phase change materials, which can be crystalline or amorphous according to the voltage or current waveform carried, so as to have a relatively low resistance value or a relatively high resistance value. For example, the reset signal Vreset can be a voltage or current waveform with high amplitude and short duration. Such a voltage or current waveform can make the phase change material non-crystalline and the corresponding resistor have a relatively high resistance; while the set signal Vset can be a voltage or current waveform with lower amplitude and longer duration than the reset signal Vreset. Such a voltage or current waveform can make the phase change material crystalline and the corresponding resistor have a relatively low resistance.

[0079] In this example, it can be assumed that when the first variable resistor R1 has a relatively low resistance and the second variable resistor R2 has a relatively high resistance, it represents bit 0, and vice versa, it represents bit 1. Therefore, when writing bit 0, the setting signal Vset can be transmitted to the first variable resistor R1 through the first bit line BL1 and the reset signal Vreset can be transmitted to the second variable resistor R2 through the second bit line BL2; and when writing bit 1, the reset signal Vreset can be transmitted to the first variable resistor R1 through the first bit line BL1 and the setting signal Vset can be transmitted to the second variable resistor R2 through the second bit line BL2. In the reading stage, a reading driving signal such as a constant voltage can be applied to the first and second bit lines BL1 and BL2, and the current values ​​of the two lines can be measured as two reading response signals, and then the resistance values ​​of the first and second variable resistors R1 and R2 can be determined based on the magnitude relationship of the current values ​​of the two lines to determine the stored bit. Alternatively, the read drive signal may be a constant current, a constant current is applied to the first and second bit lines BL1 and BL2 and the voltage values ​​of the two lines are measured as two read response signals, and then the resistance values ​​of the first and second variable resistors R1 and R2 are determined based on the magnitude relationship of the voltage values ​​of the two lines to determine the stored bit.

[0080] In the example of storing two bits respectively, the first variable resistor R1 and the second variable resistor R2 are independent storage elements. In this example, it can be assumed that when the variable resistor has a relatively low resistance, it represents bit 0, and vice versa, it represents bit 1. Transmitting a set signal Vset to the first variable resistor R1 through the first bit line BL1 can make the first variable resistor R1 store bit 0, and transmitting a reset signal Vreset to the first variable resistor R1 through the first bit line BL1 can make the first variable resistor R1 store bit 1, and the writing operation of the second variable resistor R2 is similar. In the reading stage, a predetermined voltage can be applied to the first and second bit lines BL1 and BL2 respectively and the current value can be measured, and the first and second variable resistors R1 and R2 can be judged to store bit 0 or 1 respectively based on the magnitude relationship between the measured current value and a reference current. Alternatively, a predetermined current can be applied to the first and second bit lines BL1 and BL2 respectively and the voltage value can be measured, and the first and second variable resistors R1 and R2 can be judged to store bit 0 or 1 respectively based on the magnitude relationship between the measured voltage value and a reference voltage.

[0081] By programming the resistance values ​​of the first and second variable resistors R1 and R2 with voltage or current waveforms, even if the power supply is interrupted, the first and second variable resistors R1 and R2 can still maintain the state before the power failure, and thus can be used as non-volatile storage elements. In particular, the first and second bit lines BL1 and BL2 can be controlled by a read-write control circuit (not shown). The read-write control circuit can perform the above-mentioned operations of providing a write signal or providing a read signal, and can also perform the judgment of the stored bit.

[0082] The present invention also proposes a hybrid memory unit, which, in addition to the circuit structure described in the above embodiments, further includes a controller. Figure 1 and Figure 5 ,in Figure 5 FIG. 1 is a circuit diagram of a hybrid memory cell 1' according to another embodiment of the present invention. Figure 1 and Figure 5 As shown, the hybrid memory cell 1' has the same electronic components and electrical coupling relationship as the hybrid memory cell 1, so the circuits and functional operations composed of the various electronic components are not repeated here. In addition to the electronic components and electrical coupling relationship of the hybrid memory cell 1, the hybrid memory cell 1' also includes a controller 117. The controller 117 is electrically coupled to the storage circuit 111 and the selection circuit 113, and is used to detect the selection voltage VSL, and selectively adjust the voltage value of the control voltage VC according to the selection voltage VSL. Among them, the controller 117 can be electrically coupled to the control circuit between the first and second variable resistors R1 and R2 of the storage circuit 111 and the voltage source providing the control voltage VC, or can include a device that provides the voltage source of the control voltage VC, and the present invention is not limited.

[0083] When the selection voltage VSL turns on the third and fourth transistors M3 and M4 of the selection circuit 113 and the storage circuit 111 presents a volatile storage mode, the controller 117 makes the control voltage VC have a first voltage value; and when the selection voltage VSL turns off the third and fourth transistors M3 and M4 of the selection circuit 113 and the storage circuit 111 presents a non-volatile storage mode, the controller 117 makes the control voltage VC have a second voltage value. The absolute value of the first voltage value is greater than the absolute value of the second voltage value. For example, when the storage circuit 111 presents a volatile storage mode, the controller 117 can make the control voltage VC the working voltage (VDD). When the storage circuit 111 presents a non-volatile storage mode, the controller 117 can make the control voltage VC zero, that is, make the first and second variable resistors R1 and R2 of the storage circuit 111 grounded; or when the storage circuit 111 presents a non-volatile storage mode, the controller 117 can make the control voltage VC the working voltage (VDD) or other voltage values. Compared to the embodiment in which the working voltage (VDD) is used as the control voltage VC in the non-volatile storage mode, the waveform design difficulty of the write signal (the aforementioned reset signal Vreset and setting signal Vset) is lower in the embodiment in which the control voltage VC is set to zero in the non-volatile storage mode.

[0084] The present invention also provides a mixed-mode memory, comprising an array composed of the mixed-mode memory cells 11 or 11' described in the above embodiments. Figure 6 , Figure 6 FIG. 1 is a block diagram of a hybrid memory 1 according to an embodiment of the present invention. Figure 6 As shown, the hybrid memory 1 includes a plurality of word lines WL, a plurality of bit line groups BLG, an array of a plurality of hybrid memory cells 11, an intermediate circuit 13, a read / write circuit 15, and a word line decoder 17. Each hybrid memory cell 11 is electrically coupled to a word line WL and a group of bit line groups BLG, wherein each bit line group BLG includes two bit lines (hereinafter referred to as a first bit line BL1 and a second bit line BL2). Further, the hybrid memory 1 may include m word lines WL, n bit line groups BLG, and a memory array consisting of m×n hybrid memory cells, wherein m and n are both natural numbers. It should be particularly noted here that Figure 6 The memory cell array included in the hybrid memory 1 is exemplarily shown to be composed of a hybrid memory cell 11 and represented by a box. However, the memory cell array included in the hybrid memory 1 may also be composed of a hybrid memory cell 11' or a part of the hybrid memory cell 11 and the other part of the hybrid memory cell 11'. The detailed circuit and operation of the hybrid memory cell 11 or 11' are as described above. Figure 1 to Figure 5 The corresponding embodiments are described and will not be repeated here.

[0085] As described in the above embodiments, the hybrid memory cell 11 will present a volatile storage mode or a non-volatile storage mode according to the selection voltage. By adjusting the selection voltage applied to each hybrid memory cell 11 in the hybrid memory 1, some hybrid memory cells 11 can be made to present a volatile storage mode, and some hybrid memory cells 11 can be made to present a non-volatile storage mode. Therefore, the hybrid memory 1 can be used with a variety of computing devices or other electronic devices that have different requirements for storage modes without changing the circuit design of the memory, thereby reducing development costs.

[0086] Please continue to refer to Figure 6 ,like Figure 6 As shown, the word line WL is electrically coupled to the word line decoder 17, and the word line WL is used to transmit the control signal from the word line decoder 17 to control whether the coupled hybrid memory cell 11 can perform read and write operations. The first bit line BL1 and the second bit line BL2 in the bit line group BLG are electrically coupled to the intermediate circuit 13, and the intermediate circuit 13 is electrically coupled to the read and write circuit 15. Thereby, the first bit line BL1 and the second bit line BL2 in the bit line group BLG can receive two write signals from the read and write circuit 15 through the intermediate circuit 13, or transmit the read response signal generated by the hybrid memory cell 11 according to the read drive signal to the read and write circuit 15 through the intermediate circuit 13. In other words, the intermediate circuit 13 can serve as a medium for transmitting the write signal from the read and write circuit 15 to the bit line group BLG or transmitting the read response signal from the bit line group BLG to the read and write circuit 15.

[0087] The intermediate circuit 13 includes a bit line decoder, wherein the functional operation of the bit line decoder is known to those skilled in the art and will not be described in detail herein. In addition, the intermediate circuit 13 may further include an adjuster, which is disposed between the bit line group BLG and the bit line decoder, and is used to adjust the write signal from the read / write circuit 15 and then transmit the adjusted write signal to the bit line group BLG, or adjust the read response signal from the bit line group BLG and then transmit the adjusted read response signal to the read / write circuit 15. To further illustrate the coupling relationship between the intermediate circuit 13 and the read / write circuit 15, as shown in FIG. Figure 6 As shown, the intermediate circuit 13 includes a first terminal 131 and a second terminal 132 corresponding to each other, and includes a third terminal 133 and a fourth terminal 134 corresponding to each other, wherein the first terminal 131 is electrically coupled to the first bit line BL1, the third terminal 133 is electrically coupled to the second bit line BL2, and the second terminal 132 and the fourth terminal 134 are electrically coupled to the read / write circuit 15. It should be particularly noted that, Figure 6The second terminal 132 and the fourth terminal 134 of the intermediate circuit 13 are exemplarily shown to be electrically coupled to the read / write circuit 15 . However, the intermediate circuit 13 may be electrically coupled to the read / write circuit 15 only through the second terminal 132 or the fourth terminal 134 .

[0088] The correspondence between the first terminal 131 and the second terminal 132 of the intermediate circuit 13 means that the signal output by the second terminal 132 is associated with the signal received by the first terminal 131, and the signal received by the second terminal 132 is associated with the signal output by the first terminal 131. For example, when the first terminal 131 of the intermediate circuit 13 receives a read response signal from the first bit line BL1, the second terminal 132 of the intermediate circuit 13 transmits the read response signal (or the adjusted read response signal if the intermediate circuit 13 includes an adjuster) through the intermediate circuit 13 to the read / write circuit 15; when the second terminal 132 of the intermediate circuit 13 receives a write signal from the read / write circuit 15, the first terminal 131 of the intermediate circuit 13 transmits the write signal (or the adjusted write signal if the intermediate circuit 13 includes an adjuster) through the intermediate circuit 13 to the first bit line BL1. The correspondence between the third terminal 133 and the fourth terminal 134 of the intermediate circuit 13 is similar and will not be described in detail.

[0089] The read / write circuit 15 has a write mode and a read mode, and can be switched between the write mode and the read mode according to an external instruction or a preset instruction. In the write mode, the read / write circuit 15 can generate a write signal according to an external instruction (such as an instruction input by a user), or receive a write signal from the outside, and then transmit it to the first bit line BL1 and the second bit line BL2 through the intermediate circuit 13, so that the hybrid storage unit 11 stores one or two bits according to the write signal. The detailed storage method is as described in the previous embodiment, and will not be repeated here. In the read mode, the read / write circuit 15 can apply a certain voltage (read driving signal) to the first and second bit lines BL1 and BL2 through the intermediate circuit 13 and obtain the current value of the two lines (read response signal) from the intermediate circuit 13, or apply a certain current (read driving signal) to the first and second bit lines BL1 and BL2 through the intermediate circuit 13 and obtain the voltage value of the two lines (read response signal) from the intermediate circuit 13, so as to determine the bit stored in the hybrid memory unit 11.

[0090] As mentioned above, the hybrid memory cell 11 can be written with one bit or two bits in the non-volatile storage mode. Correspondingly, the read mode of the read / write circuit 15 can have a one-bit judgment mode and a two-bit judgment mode. In the one-bit judgment mode, the read / write circuit 15 judges one bit based on the two read response signals obtained; and in the two-bit judgment mode, the read / write circuit 15 judges two bits based on the two read response signals obtained and a reference signal. In an implementation method in which a constant voltage is applied to obtain the current value of the bit line, assuming that the first or second variable resistor R1 or R2 has a first current value when it has a relatively high resistance and is applied with the constant voltage, and the first or second variable resistor R1 or R2 has a second current value when it has a relatively low resistance and is applied with the constant voltage, the current value of the reference signal is set to be between the first current value and the second current value. In an implementation scheme in which a constant current is applied to obtain a voltage value of a bit line, assuming that the first or second variable resistor R1 or R2 has a first voltage value when it has a relatively high resistance and is applied with the constant current, and that the first or second variable resistor R1 or R2 has a second voltage value when it has a relatively low resistance and is applied with the constant current, the voltage value of the reference signal is set to be between the first voltage value and the second voltage value.

[0091] The read / write circuit 15 may include a processor, a write circuit and a read circuit, wherein the processor is electrically coupled to the write circuit and the read circuit. The processor is, for example, a central processing unit, a microcontroller, a programmable logic controller, etc., and may enable the write circuit or the read circuit according to an external instruction (such as an instruction input by a user) or an internal preset instruction. The write circuit is used to execute the above-mentioned write mode, and the detailed circuit composition can be designed by the staff in the field to which the present invention belongs as needed, and will not be repeated here. As for the read circuit, the present invention proposes a special circuit composition to execute the above-mentioned one-bit judgment mode or two-bit judgment mode.

[0092] Please refer to Figure 1 , Figure 6 and Figure 7 ,in Figure 7 It is a partial circuit diagram of a hybrid memory according to an embodiment of the present invention. Figure 7 Exemplarily depicted Figure 6 The circuit composition of the read circuit of the read-write circuit 15 and the coupling relationship between the read circuit and the intermediate circuit 13 are shown. Figure 7As shown, the read / write circuit 15 includes a comparator 151, a reference signal providing circuit 153 and a control circuit 155, wherein the control circuit 155 is disposed between the comparator 151, the reference signal providing circuit 153 and the intermediate circuit 13. The comparator 151 has a first input terminal 1511, a second input terminal 1512 and an output terminal 1513. The comparator 151, for example, includes a sense amplifier (SA), which is used to compare the signals received by the first input terminal 1511 and the second input terminal 1512 to generate a comparison result and output it through the output terminal 1513. The electrical coupling relationship between the first input terminal 1511 and the second input terminal 1512 of the comparator 151 and other circuits is controlled by the control circuit 155, and the detailed control method will be described later. The output terminal 1513 of the comparator 151 can be coupled to a memory to store the comparison result, can be coupled to a user interface to present the comparison result, or can be coupled to the processor of the aforementioned read / write circuit 15 to further process the comparison result, and the present invention is not limited thereto. The reference signal providing circuit 153 may include a current source to provide a reference current, or include a voltage source to provide a reference voltage.

[0093] The control circuit 155 is used to control the electrical coupling conditions of the first input terminal 1511 and the second input terminal 1512 of the comparator 151. In the one-bit judgment mode, the control circuit 155 controls the first input terminal 1511 and the second input terminal 1512 of the comparator to obtain two read response signals passing through the intermediate circuit 13 respectively; in the two-bit judgment mode, the control circuit 155 controls the first input terminal 1511 of the comparator 151 to obtain one of the two read current signals passing through the intermediate circuit 13 and controls the second input terminal 1512 of the comparator 151 to obtain the reference current signal; or, controls the first input terminal 1511 of the comparator 151 to obtain the reference current signal and controls the second input terminal 1512 of the comparator 151 to obtain the other of the two read current signals passing through the intermediate circuit.

[0094] Specifically, the control circuit 155 may include a first switch SW1 , a second switch SW2 , a third switch SW3 , and a fourth switch SW4 . The first switch SW1 is arranged between the second end 132 of the intermediate circuit 13 and the first input end 1511 of the comparator 151, and is used to connect or disconnect the second end 132 of the intermediate circuit 13 and the first input end 1511 of the comparator 151; the second switch SW2 is arranged between the fourth end 134 of the intermediate circuit 13 and the second input end 1512 of the comparator 151, and is used to connect or disconnect the fourth end 134 of the intermediate circuit 13 and the second input end 1512 of the comparator 151; the third switch SW3 is arranged between the reference signal providing circuit 153 and the first input end 1511 of the comparator 151, and is used to connect or disconnect the reference signal providing circuit 153 and the first input end 1511 of the comparator 151; the fourth switch SW4 is arranged between the reference signal providing circuit 153 and the second input end 1512 of the comparator 151, and is used to connect or disconnect the reference signal providing circuit 153 and the second input end 1512 of the comparator 151.

[0095] In the one-bit determination mode, the first switch SW1 and the second switch SW2 are turned on, and the third switch SW3 and the fourth switch SW4 are turned off. The first input terminal 1511 of the comparator 151 obtains the read response signal from the first bit line BL1 (corresponding to the first variable resistor R1 of the hybrid memory cell 11) through the second terminal 132 of the intermediate circuit 13, and the second input terminal 1512 of the comparator 151 obtains the read response signal from the second bit line BL2 (corresponding to the second variable resistor R2 of the hybrid memory cell 11) through the fourth terminal 134 of the intermediate circuit 13. The comparator 151 can compare the current values ​​or voltage values ​​of the two obtained read response signals, and output the bit comparison result stored in the first and second variable resistors R1 and R2 of the hybrid memory cell 11.

[0096] The two-bit judgment mode can judge the bit stored in the first variable resistor R1 and the bit stored in the second variable resistor R2 respectively. When judging the bit stored in the first variable resistor R1, the first switch SW1 and the fourth switch SW4 are turned on, and the second switch SW2 and the third switch SW3 are turned off. The first input terminal 1511 of the comparator 151 obtains the read response signal from the first bit line BL1 through the second terminal 132 of the intermediate circuit 13, and the second input terminal 1512 of the comparator 151 obtains the reference signal from the reference signal providing circuit 153. The comparator 151 compares the current value or voltage value of the obtained read response signal with the reference signal, and outputs the comparison result corresponding to the bit stored in the first variable resistor R1 of the hybrid memory cell 11. When determining the bit stored in the second variable resistor R2, the first switch SW1 and the fourth switch SW4 are turned off, and the second switch SW2 and the third switch SW3 are turned on, the first input terminal 1511 of the comparator 151 obtains the reference signal from the reference signal providing circuit 153, and the second input terminal 1512 of the comparator 151 obtains the read response signal from the second bit line BL2 through the second terminal 132 of the intermediate circuit 13. The comparator 151 compares the current value or voltage value of the obtained read response signal with the reference signal, and outputs the comparison result corresponding to the bit stored in the second variable resistor R2 of the hybrid memory cell 11.

[0097] In the above embodiment, the reference signal providing circuit 153 of the read / write circuit 15 of the hybrid memory 1 is implemented by a current source or a voltage source, and the reference signal provided has a fixed current value or a fixed voltage value. The present invention also proposes a hybrid memory, wherein the reference signal providing circuit can be coupled to a variable resistor, and the current value or voltage value of the reference signal provided by the reference signal providing circuit can be changed corresponding to the change of the variable resistor. For further details, please refer to Figure 6 , Figure 7 and Figure 8 , Figure 8 is a block diagram of a hybrid memory 1 ′ according to another embodiment of the present invention. Figure 8 The hybrid memory 1' shown is substantially the same as Figure 6 The hybrid memory 1 shown. It should be noted that, in order to facilitate the presentation of the hybrid memory 1', the hybrid memory 1 also includes the following components: Figure 8Only one word line WL, one bit line group BLG and one hybrid memory cell 11 are shown for example, but in fact the hybrid memory 1' comprises a plurality of word lines WL, a plurality of bit line groups BLG, an array of a plurality of hybrid memory cells 11, an intermediate circuit 13, a read / write circuit 15 and a word line decoder 17. Each hybrid memory cell 11 is electrically coupled to a word line WL and a bit line group BLG, wherein each bit line group BLG comprises a first bit line BL1 and a second bit line BL2. Further, the hybrid memory 1' may comprise m word lines, n bit line groups and a memory array consisting of m×n hybrid memory cells, wherein m and n are both natural numbers. The functional operations and the coupling relationships between the word lines WL, hybrid memory cells 11, the intermediate circuit 13, the read / write circuit 15 and the word line decoder 17 included in the hybrid memory 1' are the same as those of the hybrid memory 1 described in the previous embodiments, and will not be described in detail here.

[0098] Compared to Figure 6 Hybrid memory 1, Figure 8 The hybrid memory 1' further includes a reference word line WLR, a plurality of reference bit lines BLR, a plurality of reference cells 19 and a reference word line decoder 21. It should be particularly noted that, in order to facilitate the description of the operation, Figure 8 Only one reference cell 19 and one reference bit line BLR are shown for example, but in reality, the number of reference cells 19 and reference bit lines BLR can be the same as the number of a column of hybrid memory cells 11. Taking a memory array composed of m×n hybrid memory cells as an example, the number of reference cells 19 and reference bit lines BLR can be n. Figure 8 As shown, the reference cell 19 is electrically coupled to the word line decoder 21 through the reference word line WLR, and is electrically coupled to the intermediate circuit 13 through the reference bit line BLR. The reference word line WLR is used to transmit a control signal from the reference word line decoder 21 to control whether the reference cell 19 operates. The operation of the reference cell 19 will be described later.

[0099] In addition to the first terminal 131 to the fourth terminal 134 as described in the previous embodiment, the intermediate circuit 13 of the hybrid memory 1' further includes a fifth terminal 135 and a sixth terminal 136 corresponding to each other, and the corresponding relationship between the fifth terminal 135 and the sixth terminal 136 is similar to the corresponding relationship between the first terminal 131 and the second terminal 132, which will not be repeated here. The fifth terminal 135 of the intermediate circuit 13 is electrically coupled to the reference unit 19 through the reference bit line BLR, and the sixth terminal 136 is electrically coupled to the read-write circuit 15. The read-write circuit 15 of the hybrid memory 1' is similar to the read-write circuit 15 of the hybrid memory 1, and includes Figure 7The circuit composition shown, wherein the operations of the comparator 151 and the switching circuit 155 are the same as those described in the previous embodiments, and are not described again. The difference between the read / write circuit 15 of the hybrid memory 1' and the read / write circuit 15 of the hybrid memory 1 is that the reference signal providing circuit 153 of the read / write circuit 15 of the hybrid memory 1' is electrically coupled to the sixth terminal 136 of the intermediate circuit 13 to obtain the reference signal from the reference unit 19 through the intermediate circuit 13.

[0100] For further information, please refer to Figure 8 and Fig. 9 ,in Fig. 9 1 is a circuit diagram of a reference unit of a hybrid memory according to another embodiment of the present invention. As shown in the figure, the reference unit 19 includes a switch element SWR (such as a transistor) and a reference variable resistor Rref electrically coupled to each other. The switch element SWR has a first end, a second end and a control end, wherein the first end is electrically coupled to one end of the reference variable resistor Rref, the second end is used to receive a first voltage V1, and the control end is electrically coupled and controlled by the reference word line WLR to connect or disconnect the first end and the second end. The other end of the reference variable resistor Rref is used to receive a second voltage V2. When the switch element SWR is turned on and there is a voltage difference between the first voltage V1 and the second voltage V2, the reference signal providing circuit 153 of the read / write circuit 15 of the hybrid memory 1' can obtain the current passing through the reference variable resistor Rref or the voltage difference between the two ends of the reference variable resistor Rref through the intermediate circuit 13 and the reference bit line BLR as a reference signal. Furthermore, the reference variable resistor Rref has the same composition as the first variable resistor R1 and the second variable resistor R2 in the hybrid memory cell 11, and may include a phase change element or a resistance change element. During the manufacturing process, the reference unit 19 and the variable resistor in the hybrid memory cell 11 may be formed together. Therefore, compared with the embodiment in which the fixed current value or the fixed voltage value of the reference signal is pre-designed, the reference signal generated in this embodiment can cope with the characteristic that the variable resistor is prone to variation during the manufacturing process.

[0101] With the above structure, the hybrid memory disclosed in the present case includes an array composed of a plurality of hybrid memory cells, each of which can be set to a volatile storage mode or a non-volatile storage mode as required, and has high adaptability. By adjusting the setting of the selection voltage corresponding to each hybrid memory cell, the hybrid memory can be used with a variety of computing devices or other electronic devices with different requirements for storage modes without changing the circuit design of the memory, thereby reducing development costs.

Claims

1. A hybrid memory, characterized in that: Include: a memory array comprising a plurality of hybrid memory cells; a word line decoder electrically coupled to the memory array; an intermediate circuit electrically coupled to the memory array; as well as a read / write circuit electrically coupled to the intermediate circuit; Each of the hybrid memory cells includes: A read / write element group is electrically coupled to a word line and two bit lines, the word line controls the conduction or disconnection of the read / write element group, and the two bit lines transmit two data signals respectively; a storage circuit for generating two read response signals according to a read driving signal; and a selection circuit electrically coupled to the storage circuit, the selection circuit being used to control the storage circuit to present a volatile storage mode or a non-volatile storage mode according to a selection voltage; The storage circuit includes a first variable resistor, a second variable resistor, a first transistor and a second transistor. When the read / write element group transmits the two data signals to the storage circuit and the storage circuit presents the non-volatile storage mode, the first variable resistor and the second variable resistor selectively change resistance values ​​according to the two data signals respectively. The selection circuit is used to control an electrical coupling state among the first variable resistor, the second variable resistor, the first transistor and the second transistor according to the selection voltage. When the selection circuit controls the electrical coupling state to be conductive according to the selection voltage, the storage circuit presents the volatile storage mode, and when the selection circuit controls the electrical coupling state to be non-conductive according to the selection voltage, the storage circuit presents the non-volatile storage mode. The first variable resistor and the second variable resistor include a phase change element and a resistance change element; The read-write circuit includes: a comparator having two input terminals, for comparing signals received by the two input terminals and outputting a comparison result; a reference signal providing circuit, used for providing a reference signal; and a control circuit for controlling the electrical coupling conditions of the two input terminals of the comparator; In which, in a single-bit judgment mode, the control circuit controls one of the two input terminals of the comparator to obtain one of the two read response signals passing through the intermediate circuit, and controls the other of the two input terminals of the comparator to obtain the reference signal; in a dual-bit judgment mode, the control circuit controls the two input terminals of the comparator to respectively obtain the two read response signals passing through the intermediate circuit.

2. The hybrid memory as claimed in claim 1, wherein the reference signal providing circuit comprises a plurality of reference cells, the reference cells are arranged in a row and located in the memory array, wherein: Each of the reference units includes a reference switch element and a reference variable resistor, and the reference variable resistor is electrically coupled to the reference switch element. 3 . The hybrid memory as claimed in claim 2 , wherein the reference variable resistor comprises a phase change element and a resistance change element, and wherein the reference signal providing circuit is used to obtain the reference signal associated with the reference variable resistor.

4. The hybrid memory as claimed in claim 1, wherein the selection circuit comprises: a third transistor, wherein a first terminal of the third transistor is electrically coupled to one terminal of the first variable resistor, the control terminal of the second transistor and the read / write element group, a second terminal of the third transistor is electrically coupled to the first terminal of the first transistor, and the control terminal of the third transistor is used to receive the selection voltage; and A fourth transistor, a first end of the fourth transistor is electrically coupled to one end of the second variable resistor, the control end of the first transistor and the read-write element group, a second end of the fourth transistor is electrically coupled to the first end of the second transistor, and the control end of the fourth transistor is used to receive the selection voltage.

5. The hybrid memory as claimed in claim 4, wherein the read / write element group comprises: a fifth transistor, a first terminal of the fifth transistor being electrically coupled to the first terminal of the third transistor, a second terminal of the fifth transistor being electrically coupled to one of the two bit lines, and a control terminal of the fifth transistor being electrically coupled to the word line; and A sixth transistor, a first terminal of the sixth transistor is electrically coupled to the first terminal of the fourth transistor, a second terminal of the sixth transistor is electrically coupled to the other of the two bit lines, and a control terminal of the sixth transistor is electrically coupled to the word line. 6 . The hybrid memory as claimed in claim 5 , wherein one end of the two variable resistors is electrically coupled to the read / write element group, and the other end of the two variable resistors is used to receive a control voltage. 7 . The hybrid memory as claimed in claim 6 , wherein the hybrid memory unit further comprises a controller, the controller is electrically coupled to the storage circuit and the selection circuit, and is used to detect the selection voltage and control the control voltage according to the selection voltage.

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