An analog circuit and encryption method based on EEPROM

Abstract

The present invention discloses an analog circuit and encryption method based on EEPROM, belonging to the field of integrated circuits, and comprising a storage unit EEPROM, a verification circuit, a register group and an address sequence generator. The storage unit EEPROM is used to store key configuration information, non-key configuration information and encryption verification code of the analog circuit; the verification circuit verifies whether the stored encryption verification code complies with the encryption rule, and the encryption algorithm can be arbitrarily selected; the register group receives the key configuration information, non-key configuration information and encryption verification code sent by the storage unit EEPROM; the address sequence generator sends an address request to the storage unit EEPROM, and the storage unit EEPROM sends corresponding data to the corresponding register in the register group after receiving the request. The present invention can ensure that the key configuration parameters of the circuit are not obtained in reverse, can well protect the core technology of the analog circuit, increase the difficulty of reverse design, and provide an important technical guarantee for the forward design chip with independent intellectual property rights to occupy the market.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an EEPROM-based analog circuit and an encryption method. Background Art

[0002] As the complexity and functionality of integrated circuits increase, the time, manpower and financial costs required for forward development are getting higher and higher. Many companies use reverse design methods to imitate or even copy competitors' chips. Forward-developed chips are likely to be imitated or copied by competitors before the cost is recovered. The encryption of integrated circuits is particularly important. High-performance analog circuits will be designed with many redundant configurations. During the factory testing phase, the circuit parameters are adjusted according to the configuration to ultimately optimize the circuit performance. The core of encryption is to encrypt these key configuration parameters. Summary of the invention

[0003] The object of the present invention is to provide an EEPROM-based analog circuit and encryption method to prevent key configuration parameters of the circuit from being reversely acquired.

[0004] In order to solve the above technical problems, the present invention provides an EEPROM-based analog circuit, comprising:

[0005] The storage unit EEPROM is used to store the key configuration information, non-key configuration information and encryption check code of the analog circuit;

[0006] Verification circuit, verifying whether the stored encryption verification code complies with the encryption rules, and the encryption algorithm can be selected arbitrarily;

[0007] A register group receives key configuration information, non-key configuration information and encryption check code sent by the storage unit EEPROM;

[0008] The address sequence generator sends an address request to the storage unit EEPROM, and the storage unit EEPROM sends corresponding data to the corresponding register in the register group after receiving the request.

[0009] Optionally, the critical configuration information refers to information that the designer does not want the user to obtain; the non-critical information refers to configuration information that the designer allows the user to obtain.

[0010] Optionally, the encryption verification code is a specific value used for encryption verification, which is calculated from all key configuration information. If any key information is different, the encryption verification code will be different.

[0011] The present invention also provides an encryption method for an analog circuit, comprising:

[0012] Step 1: The chip is powered on, and the address sequence generator sends an EEPROM enable signal and a continuous address signal, requesting the storage unit EEPROM to send key configuration information and an encryption check code;

[0013] Step 2, the storage unit EEPROM starts to send key configuration information to the register group, and sends an encryption verification code after the key information configuration is sent, and then the storage unit EEPROM enters a waiting state;

[0014] Step 3: The verification circuit starts to verify the key configuration information and the encrypted verification code stored in the register group.

[0015] Optionally, in step 3, if the encryption verification code and the key configuration information conform to the encryption logic, the verification passes. At this time, the address sequence generator sends a new address to the storage unit EEPROM, requests the storage unit EEPROM to send non-critical configuration information, and the storage unit EEPROM sends the non-critical configuration information to the register group; thereafter, the encryption verification process is completely completed, the address sequence generator is turned off, the serial communication function of the analog circuit is enabled, the output path of the register group key configuration data to the analog circuit is enabled, and the analog circuit enters a normal working state.

[0016] Optionally, in step 3, if the encryption check fails, the serial communication function of the analog circuit is disabled, the output path from the register group key configuration data to the analog circuit is disabled, and the process returns to step 2, the address sequence generator is restarted, and an EEPROM enable signal and continuous address requests are sent to request the storage unit EEPROM to send key configuration information and encryption check code.

[0017] Optionally, in step 3, if the encryption check fails multiple times, the analog circuit will fall into an infinite loop, the serial communication function of the analog circuit will be disabled, the output path from the register group key configuration data to the analog circuit will be disabled, the chip serial port will not be able to work normally, the analog circuit will not be able to obtain key configuration parameters, and will not be able to work normally.

[0018] The EEPROM-based analog circuit and encryption method provided by the present invention include a storage unit EEPROM, a verification circuit, a register group and an address sequence generator. The storage unit EEPROM is used to store the key configuration information, non-key configuration information and encryption verification code of the analog circuit; the verification circuit verifies whether the stored encryption verification code complies with the encryption rules, and the encryption algorithm can be selected arbitrarily; the register group receives the key configuration information, non-key configuration information and encryption verification code sent by the storage unit EEPROM; the address sequence generator sends an address request to the storage unit EEPROM, and the storage unit EEPROM sends the corresponding data to the corresponding register in the register group after receiving the request. The present invention can ensure that the key configuration parameters of the circuit are not obtained in reverse, can well protect the core technology of the analog circuit, increase the difficulty of reverse design, and provide an important technical guarantee for the forward design chip with independent intellectual property rights to occupy the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the structure of an analog circuit based on EEPROM provided by the present invention;

[0020] Figure 2 It is a schematic diagram of the implementation process of the encryption method of the analog circuit provided by the present invention. DETAILED DESCRIPTION

[0021] The following is a further detailed description of an EEPROM-based analog circuit and encryption method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0022] Embodiment 1

[0023] The present invention provides an EEPROM-based analog circuit, the structure of which is as follows: Figure 1 As shown, it includes the following modules:

[0024] Module 1, storage unit EEPROM, is used to store key configuration information, non-key configuration information and encryption check code of analog circuits; key configuration information refers to information that designers do not want users to obtain, such as information related to the performance of analog circuits; non-key information refers to configuration information that designers can allow users to obtain, such as information only related to the function of analog circuits; the chip has 5 key information, namely 0x0a, 0x0b, 0x0c, 0x0d, and 0x0e.

[0025] Module 2, verification circuit, is used to verify whether the stored verification code complies with the encryption rule. In this embodiment, the Chinese encryption rule is set to a simple sum, that is, the value of the encryption verification code is the sum of the first five groups of key information, and the corresponding correct encryption verification code is 0x3c.

[0026] Module 3, register group, receives the configuration data sent by the storage unit EEPROM. The number of register groups is 10. The first 5 store the key configuration information sent by the storage unit EEPROM, the sixth stores the encryption check code, and the 7th, 8th, 9th, and 10th store the non-key configuration information that can be accessed by the user.

[0027] Module 4, address sequence generator, is used to send address requests to the storage unit EEPROM. After receiving the request, the storage unit EEPROM will send corresponding data to the corresponding register in the register group.

[0028] Module 5: High-precision temperature sensor simulation circuit, used to test temperature in real time.

[0029] Embodiment 2

[0030] The present invention also provides an encryption method for an analog circuit, the process of which is as follows: Figure 2 As shown, including:

[0031] Step 1: The chip is powered on, and the address sequence generator sends an EEPROM enable signal and a continuous address signal. The address signals are 0x01, 0x02, 0x03, 0x04, 0x05, and 0x06, respectively, requesting the storage unit EEPROM to send key configuration information and encryption verification code;

[0032] Step 2, the storage unit EEPROM starts to send the first 5 key configuration information (0x0a, 0x0b, 0x0c, 0x0d, 0x0e) stored in sequence, and after sending, it sends the encryption verification code, and then the storage unit EEPROM enters the waiting state;

[0033] Step 3: The verification circuit starts to verify the key configuration information and the encrypted verification code stored in the register group.

[0034] In step 3, if the encryption check code is 0x3c, it proves that the encryption check code and the key configuration information conform to the encryption logic, and the check passes. At this time, the address sequence generator sends a new address to the storage unit EEPROM (0x07, 0x08, 0x09, 0x0a), and requests the storage unit EEPROM to send non-critical information. The storage unit EEPROM sends the non-critical configuration information to the register group. After that, the encryption check process is completely completed, the address sequence generator is turned off, the serial port communication function of the circuit is enabled, the register group key configuration data to the analog circuit output path is enabled, and the circuit enters a normal working state.

[0035] In step 3, if the encryption verification code is not 0x3c, it proves that the encryption verification code and the key configuration information do not conform to the encryption logic, and the verification fails; the serial communication function of the analog circuit is disabled, and the output path from the register group key configuration data to the analog circuit is disabled, and the process returns to step 2, and the address sequence generator sends an enable EEPROM signal and a continuous address signal to request the storage unit EEPROM to send key information and the encryption verification code.

[0036] In step 3, if the encryption check fails multiple times, the analog circuit will fall into an infinite loop, the serial communication function of the analog circuit will be disabled, the output path from the register group key configuration data to the analog circuit will be disabled, the chip serial port will not be able to work normally, the analog circuit will not be able to obtain key configuration parameters, and will not be able to work normally.

[0037] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An EEPROM-based analog circuit, characterized in that: include: The storage unit EEPROM is used to store the key configuration information, non-key configuration information and encryption check code of the analog circuit; Verification circuit, verifying whether the stored encryption verification code complies with the encryption rules, and the encryption algorithm can be selected arbitrarily; A register group receives key configuration information, non-key configuration information and encryption check code sent by the storage unit EEPROM; An address sequence generator sends an address request to the storage unit EEPROM, and the storage unit EEPROM sends corresponding data to a corresponding register in the register group after receiving the request; The key configuration information refers to information that the designer does not want the user to obtain; the non-key configuration information refers to configuration information that the designer can allow the user to obtain; the encryption verification code is a specific value used for encryption verification, which is calculated from all the key configuration information. If any key information is different, the encryption verification code will be different.

2. An encryption method for an analog circuit, characterized in that: include: Step 1: The chip is powered on, and the address sequence generator sends an EEPROM enable signal and a continuous address signal, requesting the storage unit EEPROM to send key configuration information and an encryption check code; Step 2, the storage unit EEPROM starts to send key configuration information to the register group, and sends an encryption verification code after the key information configuration is sent, and then the storage unit EEPROM enters a waiting state; Step 3: The verification circuit starts to verify the key configuration information and the encrypted verification code stored in the register group.

3. The encryption method of the analog circuit as claimed in claim 2, characterized in that: In step 3, if the encryption verification code and the key configuration information conform to the encryption logic, the verification is passed. At this time, the address sequence generator sends a new address to the storage unit EEPROM, requests the storage unit EEPROM to send non-critical configuration information, and the storage unit EEPROM sends the non-critical configuration information to the register group; thereafter, the encryption verification process is completely completed, the address sequence generator is turned off, the serial communication function of the analog circuit is enabled, the output path of the register group key configuration data to the analog circuit is enabled, and the analog circuit enters a normal working state.

4. The encryption method of the analog circuit as claimed in claim 3, characterized in that: In step 3, if the encryption check fails, the serial communication function of the analog circuit is disabled, the output path from the register group key configuration data to the analog circuit is disabled, and the process returns to step 2, the address sequence generator is restarted, and an EEPROM enable signal and continuous address requests are sent to request the storage unit EEPROM to send key configuration information and encryption check code.

5. The encryption method of the analog circuit as claimed in claim 4, characterized in that: In step 3, if the encryption check fails multiple times, the analog circuit will fall into an infinite loop, the serial communication function of the analog circuit will be disabled, the output path from the register group key configuration data to the analog circuit will be disabled, the chip serial port will not be able to work normally, the analog circuit will not be able to obtain key configuration parameters, and will not be able to work normally.

Images