A multi-core architecture with embedded FPGA and data processing method thereof

Abstract

The present invention discloses a multi-core architecture with an embedded FPGA and a data processing method thereof, wherein the multi-core architecture includes a multi-core array, the multi-core array includes multiple computing cores and at least one processing core integrated with an FPGA, the processing core and the multiple computing cores are set with a synchronous clock, the processing core communicates with its adjacent computing cores through inter-core routing, and the calculation data of the current computing core is transmitted from the computing core to the FPGA computing unit in at least one processing core through the inter-core routing for calculation. The beneficial effects of the present invention are: by integrating the processing core of the FPGA in the multi-core array, the processing core communicates with its adjacent computing cores through the inter-core routing, and the calculation data of the current computing core is transmitted from the computing core to the FPGA computing unit in at least one processing core through the inter-core routing for calculation, which saves processing time and improves calculation efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of many-core architectures, and in particular to a many-core architecture with an embedded FPGA and a data processing method thereof. Background Art

[0002] When the existing multi-core architecture encounters an unsupported algorithm or operation instruction, it usually transmits the data to the CPU outside the chip for processing. After the CPU completes the processing, the result is returned to the core of the chip to continue the operation of the next algorithm or operation instruction. This method consumes a lot of time in terms of instruction fetching and decoding. Summary of the invention

[0003] To solve the above problems, the object of the present invention is to provide a many-core architecture with embedded FPGA and a data processing method thereof, which can save processing time and improve computing efficiency.

[0004] The present invention provides a many-core architecture with an embedded FPGA, comprising: a many-core array, wherein the many-core array includes multiple computing cores and at least one processing core integrated with an FPGA, wherein the processing core is set with a synchronous clock with the multiple computing cores, and the processing core communicates with its adjacent computing cores through inter-core routing.

[0005] As a further improvement of the present invention, the computing core includes an AI computing unit, a storage unit and a route, the processing core includes an FPGA computing unit, a storage unit and a route, and the processing core has the same storage unit and routing configuration as the multiple computing cores.

[0006] As a further improvement of the present invention, the computing core includes an AI computing unit, a storage unit and a route, the processing core includes an FPGA computing unit, a storage unit and a route, and the storage capacity of the storage unit of the processing core is different from that of the storage units of the multiple computing cores.

[0007] As a further improvement of the present invention, the many-core array is a two-dimensional matrix network, a two-dimensional ring network, a two-dimensional star network or a three-dimensional hierarchical network.

[0008] As a further improvement of the present invention, the many-core array is a two-dimensional matrix network, at least one of the processing cores is arranged at a corner of the many-core array, and the processing core communicates with its two adjacent computing cores through two inter-core routing paths.

[0009] As a further improvement of the present invention, the many-core architecture includes a plurality of processing cores, and the plurality of processing cores are symmetrically arranged at corners of the many-core array.

[0010] As a further improvement of the present invention, the many-core array is a two-dimensional matrix network, at least one of the processing cores is arranged inside the many-core array, and the processing core communicates with its four adjacent computing cores through four inter-core routing paths.

[0011] As a further improvement of the present invention, the many-core architecture includes a plurality of processing cores, and the plurality of processing cores are symmetrically arranged on a diagonal line inside the many-core array.

[0012] The present invention also provides a data processing method for a multi-core architecture with an embedded FPGA. Using the multi-core architecture with an embedded FPGA, the data processing method includes: computing data that cannot be processed by the current computing core is transmitted from the current computing core to at least one processing core through inter-core routing for calculation.

[0013] As a further improvement of the present invention, computing data that cannot be processed by the current computing core is transmitted from the current computing core to an FPGA computing unit in at least one of the processing cores through inter-core routing for calculation. After the FPGA computing unit completes the calculation, the calculation result is transmitted to the next computing core through inter-core routing to continue the calculation.

[0014] As a further improvement of the present invention, a single computing task is divided into a plurality of sub-computing tasks, and the plurality of sub-computing tasks are allocated to at least one of the processing cores and the plurality of computing cores for intermediate processing;

[0015] At time t-1, core a processes the corresponding sub-computation task and transmits the processed data to core b;

[0016] At time t, core b receives the data transmitted by core a and continues to process it, and transmits the processed data to core c;

[0017] At time t+1, core c receives the data transmitted by core b and continues to process it, and transmits the processed data to other cores for further processing;

[0018] Thus, on the time axis, at least one of the processing cores and the plurality of computing cores pipeline processes respective sub-computing tasks, wherein the core a, the core b, the core c and the other cores are one of the at least one of the processing cores and the plurality of computing cores;

[0019] At the same time, at least one of the processing cores and the multiple computing cores process their respective sub-computing tasks in parallel.

[0020] As a further improvement of the present invention, the computing data of the corresponding sub-computing tasks that cannot be processed by the current computing core are transmitted from the current computing core to the processing core for processing through inter-core routing.

[0021] As a further improvement of the present invention, the processing core closest to the current computing core is found through inter-core routing, and the calculation data of the sub-computation task that the current computing core cannot process is transmitted to the FPGA computing unit in the processing core for calculation. After the FPGA computing unit completes the calculation, the calculation result is transmitted to the next computing core through inter-core routing to continue the calculation.

[0022] As a further improvement of the present invention, multiple processing cores closest to the current computing core are found through inter-core routing, and the calculation data of multiple sub-computation tasks that cannot be processed by the current computing core are transmitted to the FPGA computing units in each processing core for calculation. After each FPGA computing unit completes the calculation, the calculation result is transmitted to the next computing core through inter-core routing to continue the calculation.

[0023] The present invention also provides a many-core chip, including the many-core architecture with embedded FPGA.

[0024] As a further improvement of the present invention, the many-core chip includes the many-core architecture of the embedded FPGA, the on-chip processor, the PCle controller, the DMA, the universal interface, and the DDR controller. The many-core architecture of the embedded FPGA, the on-chip processor, the PCle controller, the DMA, the universal interface, and the DDR controller communicate through a bus.

[0025] The present invention also provides an electronic device, comprising a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the data processing method of the multi-core architecture embedded with FPGA.

[0026] The present invention also provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the data processing method of the multi-core architecture embedded with FPGA.

[0027] The beneficial effects of the present invention are:

[0028] Integrating FPGA into AI multi-core chips saves processing time and improves computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0030] Figure 1A principle block diagram of a many-core chip with a many-core architecture including an embedded FPGA according to an exemplary embodiment of the present disclosure;

[0031] Figure 2 It is a schematic diagram of a many-core architecture with an embedded FPGA according to an exemplary embodiment of the present disclosure, in which the FPGA is integrated at the corner of the many-core array;

[0032] Figure 3 A schematic diagram of a many-core architecture with an embedded FPGA according to an exemplary embodiment of the present disclosure, in which the FPGA is integrated into a many-core array;

[0033] Figure 4 A schematic diagram of data processing during operation of a multi-core architecture with an embedded FPGA according to an exemplary embodiment of the present disclosure;

[0034] Figure 5 The present invention is a timing diagram of a multi-core architecture with an embedded FPGA during operation according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0036] It should be noted that if the embodiments of the present disclosure involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0037] In addition, in the description of the present disclosure, the terms used are only for illustrative purposes and are not intended to limit the scope of the present disclosure. The terms "include" and / or "comprise" are used to specify the existence of the elements, steps, operations and / or components, but do not exclude the existence or addition of one or more other elements, steps, operations and / or components. The terms "first", "second" and the like may be used to describe various elements, do not represent the order, and do not limit these elements. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "multiple" is two and more than two. These terms are only used to distinguish one element from another element. In conjunction with the following drawings, these and / or other aspects become apparent, and it is easier for those of ordinary skill in the art to understand the description of the embodiments described in the present disclosure. The accompanying drawings are used to describe the embodiments described in the present disclosure for illustrative purposes only. Those skilled in the art will easily recognize from the following description that, without departing from the principles described in the present disclosure, alternative embodiments of the structures and methods shown in the present disclosure can be adopted.

[0038] AI chips are modules specifically designed to handle a large number of computing tasks in artificial intelligence applications. Traditional CPUs and GPUs are not designed for AI algorithms and cannot achieve the best cost-effectiveness. APU (AI Processing Unit) is a brain-like chip with a multi-core architecture. It supports parallel computing capabilities that are crucial for deep learning. It is faster than traditional processors and greatly speeds up the training and reasoning process. However, APU has certain limitations when applied to deep learning algorithms, and its hardware structure has relatively weak support for primitives and instructions. When encountering unsupported algorithms or operation instructions, the data needs to be transferred to the CPU outside the chip for processing. After the CPU completes the processing, the result is returned to the core of the chip to continue the operation of the next algorithm or operation instruction. Although the CPU has great flexibility and coverage, it also takes a lot of time for the CPU to use instruction fetching and decoding.

[0039] The present disclosure implements a multi-core architecture with an embedded FPGA, including: a multi-core array, the multi-core array includes multiple computing cores and at least one processing core with an integrated FPGA, the processing core and the multiple computing cores are set with a synchronous clock, and the processing core communicates with its adjacent computing cores through inter-core routing. Figure 1 As shown, a multi-core architecture with an embedded FPGA in an embodiment of the present disclosure integrates the FPGA into the AI ​​computing core array and communicates with the outside world through the inter-chip routing of the AI ​​computing core array. The control modules such as the CPU / ARM / MCU can configure the FPGA during initialization. By implementing pre-compilation through the FPGA, when the AI ​​computing core array performs calculations, the CPU and ARM do not need to schedule the data or instructions of the FPGA, and a pipeline data processing mode can be formed to reduce processing delays and improve processing efficiency.

[0040] The many-core architecture with an embedded FPGA implemented in the present disclosure utilizes the advantage of FPGA pre-compiling tasks and then processing them at high speed, solving the time-consuming problems in instruction fetching, decoding, etc. Compared with the many-core architecture in which the FPGA is integrated outside the chip, the many-core architecture with an embedded FPGA implemented in the present disclosure solves the problem of extra energy consumption in inter-chip communication transmission caused by the integration of the FPGA outside the chip, and the problem of interruption of data pipeline processing when scheduling tasks on the FPGA caused by the integration of the FPGA outside the chip, resulting in a decrease in overall performance.

[0041] The multi-core architecture with an embedded FPGA described in the embodiment of the present disclosure solves the problem of interrupting data pipeline processing and causing overall performance degradation when scheduling tasks on the FPGA through a bus, and also reduces the overhead of the on-chip CPU accordingly.

[0042] The many-core architecture of an embedded FPGA described in the embodiment of the present disclosure can support the newly added processing core of the embedded FPGA by simply adding the type of node in the existing on-chip network structure. The newly added processing core of the embedded FPGA can also be used as an ordinary computing core, so there is no need to modify the software and various applications that have been adjusted in the upper layer. When encountering complex logical control operations, the processing core of the embedded FPGA is called to complete the corresponding logical operation. When multiple processing cores of the embedded FPGA are designed in a many-core array, multiple small networks can be supported for logical control at the same time.

[0043] In one achievable implementation, the computing core includes an AI computing unit, a storage unit, and a route, and the processing core includes an FPGA computing unit, a storage unit, and a route, and the storage unit and the route configuration of the processing core are the same as those of the multiple computing cores. For example, the storage capacity of the storage unit of the processing core and the multiple computing cores can be the same. The computing core and the processing core are designed as equally positioned modules for integration, with the same timing control and communication mode, to form an array integration architecture of a quasi-isomorphic two-dimensional grid.

[0044] In an achievable implementation, the configuration of the storage units of the processing core and the multiple computing cores may be different, for example, the storage capacity of the storage units of the processing core and the multiple computing cores may be different. The storage capacity of the storage units of each core (including the processing core and the multiple computing cores) may be different, or the storage capacity of each core may be different. The present disclosure does not limit the size of the storage capacity of the storage units of the processing core and the multiple computing cores, or whether they are the same.

[0045] In an achievable implementation, the many-core array is a two-dimensional matrix network, a two-dimensional ring network, a two-dimensional star network, or a three-dimensional hierarchical network. The selection of the many-core array network structure can be selected and designed according to the functions and requirements of the chip. As for the number of processing cores embedded in the FPGA, it can be adaptively designed according to the functions to be completed by the chip. When the processing volume of logical operations and judgment instructions is small, only one FPGA processing core can be integrated in the on-chip many-core array. When the processing volume of logical operations and judgment instructions is large, the number of processing cores embedded in the FPGA can be appropriately increased. In addition, designing multiple integrated FPGA processing cores in a many-core array can support the simultaneous operation of multiple small networks and improve the operation speed.

[0046] In a preferred embodiment, the many-core array is designed as a two-dimensional square network. The symmetrical structure design optimizes data transmission, processing, chip power consumption and heat dissipation, thereby improving the overall performance of the chip.

[0047] As for the position of the processing core of the embedded FPGA in the many-core array, its optimal position can be determined according to the position of the specified input computing core of the calculation data, so as to quickly find the processing core of the embedded FPGA closest to the computing core, thereby improving the overall computing speed of the chip.

[0048] In one possible implementation, Figure 2 As shown, the many-core array selects a two-dimensional matrix network, and at least one processing core with an embedded FPGA is set at the corner of the many-core array. The processing core communicates with its two adjacent computing cores through two inter-core routing paths.

[0049] In an achievable implementation, the many-core architecture includes multiple processing cores, and the multiple processing cores, i.e., an even number of processing cores, can be symmetrically arranged at the corners of the many-core array. This symmetrical arrangement of the processing cores is suitable for two-dimensional matrix networks, especially two-dimensional square networks. Each additional processing core can increase the processing capacity of the chip logic operation and judgment instructions accordingly. For example, two processing cores can be symmetrically arranged at the diagonal corners of the many-core array, one at the upper left corner of the many-core array, and the other at the lower right corner of the many-core array. Two processing cores can also be symmetrically arranged at the upper right corner and the lower left corner of the many-core array. Designing two processing cores with embedded FPGAs at the diagonal corners of the many-core array can increase the processing capacity of logic operations and judgment instructions on the one hand, and on the other hand, the symmetrical design can also reduce the time for data to be transmitted from the computing core to the processing core, thereby improving the real-time performance of the operation. Four processing cores can also be arranged at the four corners of the many-core array. A processing core is set at each corner. Generally, for situations where the processing volume of logic operations and judgment instructions is large, four processing cores are set at the four corners. While increasing the logic operation and judgment instruction capabilities, it reduces the time for data to be transmitted from the computing core to the processing core. In the specific design, it is necessary to comprehensively consider the chip area, function and energy consumption, and make adaptive designs for the number and location of processing cores.

[0050] In one possible implementation, Figure 3 As shown, the many-core array is a two-dimensional matrix network, at least one processing core is arranged inside the many-core array, and the processing core communicates with its four adjacent computing cores through four inter-core routing paths.

[0051] In one achievable implementation, the many-core architecture includes multiple processing cores, and the multiple processing cores can be symmetrically arranged on the diagonal inside the many-core array. This method of symmetrical processing cores on the diagonal inside the many-core array is particularly suitable for two-dimensional square networks. Each additional processing core can increase the processing capacity of the chip's logical operations and judgment instructions accordingly. Designing multiple processing cores with embedded FPGAs on the diagonal inside the many-core array can increase the processing capacity of logical operations and judgment instructions on the one hand, and on the other hand, the symmetrical design can also reduce the time for data to be transmitted from the computing core to the processing core, thereby improving the real-time performance of the operation. For example, for a two-dimensional 4*4 network, a processing core with embedded FPGA can be set in the second row and second column and the third row and third column of the many-core array. For example, a processing core with embedded FPGA can also be set in the second row and third column and the third row and second column of the many-core array. For example, a processing core can be set in the second row and second column, the second row and third column, the third row and second column, and the third row and third column of the many-core array. This is generally aimed at situations where the processing volume of logic operations and judgment instructions is large. Setting four processing cores inside the many-core array increases the logic operation and judgment instruction capabilities while reducing the time for data to be transmitted from the computing core to the processing core. In the specific design, it is necessary to comprehensively consider the area, function, and energy consumption of the chip, and make an adaptive design for the number and position of the processing cores.

[0052] The data processing method of the multi-core architecture with embedded FPGA described in the embodiment of the present disclosure adopts the multi-core architecture with embedded FPGA in the above-mentioned embodiment, and the calculation data is transmitted from the calculation core to at least one processing core through inter-core routing for calculation. Figure 4 As shown, when the current computing core encounters an unsupported operation instruction (such as complex logic control and judgment instructions, etc.), the calculation data that the current computing core cannot process is transmitted from the current computing core to the FPGA computing unit in at least one processing core through the inter-core routing for calculation. After the FPGA computing unit completes the calculation, the calculation result is transmitted to the next computing core through the inter-core routing to continue the calculation.

[0053] In one possible implementation, Figure 5 As shown, in a multi-core architecture with an embedded FPGA disclosed in the present invention, a single computing task is divided into a plurality of sub-computing tasks during data processing, and the plurality of sub-computing tasks are distributed to at least one processing core and a plurality of computing cores for processing.

[0054] At time t-1, core a processes the corresponding sub-computation task and transmits the processed data to core b; at time t, core b receives the data transmitted by core a and continues to process, and transmits the processed data to core c; at time t+1, core c receives the data transmitted by core b and continues to process, and transmits the processed data to other cores for further processing; in this way, on the time axis, at least one processing core and multiple computing cores pipeline process their respective sub-computation tasks, wherein core a, core b, core c and other cores are one of the at least one processing core and multiple computing cores. Wherein, t is an integer greater than or equal to 1, and time 0 is the time when the operation starts.

[0055] For example, Figure 5 As shown, on the entire time axis, APU core 1 transmits the data processed in time period T1 to APU core 5 (computing core 5) for processing in time period T2, while APU core 1 (computing core 1) continues to process the data in time period T2, and transmits the data processed in time period T2 to APU core 5 for processing in time period T3, while APU core 1 continues to process the data in time period T3, and transmits the data processed in time period T3 to APU core 5 for processing in time period T4, ...,

[0056] APU core 5 processes the data processed by APU core 1 in time period T1 in time period T2, and transmits the data processed in time period T2 to FPGA core 8 (processing core) for processing in time period T3. Meanwhile, APU core 5 continues to process the data processed by APU core 1 in time period T2 in time period T3, and transmits the data processed in time period T3 to FPGA core 8 for processing in time period T4. Meanwhile, APU core 5 continues to process the data processed by APU core 1 in time period T3 in time period T4, ...,

[0057] FPGA core 8 processes the data processed by APU core 5 in time period T2 in time period T3, and transmits the data processed in time period T3 to APU core 3 for processing in time period T4. Meanwhile, FPGA core 8 processes the data processed by APU core 5 in time period T3 in time period T4, ...,

[0058] In this way, a pipeline processing mode is formed on the time axis.

[0059] In addition, at the same time, at least one processing core and multiple computing cores process their respective sub-computing tasks in parallel.

[0060] For example, Figure 5As shown, in the T6 time period, APU core 1 (computing core 1), APU core 5 (computing core 5), APU core 3 (computing core 3), and APU core 6 (computing core 6) each process the corresponding computing subtasks, while FPGA core 8 (processing core) processes the corresponding logic control and judgment instruction subtasks.

[0061] In this pipeline processing mode, data transmission and operation between multiple cores do not require intervention and scheduling by the on-chip CPU, which reduces processing delays and improves processing efficiency. FPGA can process algorithms that the APU core cannot process or processes inefficiently, as well as the processing of logic control and judgment instructions, etc. All transmission and processing processes are completed on the chip, which can greatly save transmission bandwidth, reduce energy consumption, improve computing efficiency, and accelerate the reasoning / training process of neural networks.

[0062] In an achievable implementation, when the many-core array includes multiple processing cores with embedded FPGAs, if the current computing core encounters an unsupported sub-computing task, the processing core closest to the current computing core can be found through inter-core routing, and the data of the sub-computing task that the current computing core cannot process is transmitted to the FPGA computing unit in the processing core for operation. After the FPGA computing unit completes the operation, the operation result is transmitted to the next computing core through inter-core routing to continue the operation. By quickly finding the processing core with embedded FPGA closest to the computing core, the overall operation rate of the chip is improved.

[0063] In a feasible implementation, when the many-core array includes multiple processing cores with embedded FPGAs, if the current computing core encounters multiple unsupported sub-computing tasks, it can respectively find multiple processing cores closest to the current computing core through inter-core routing, and transmit the calculation data of multiple sub-computing tasks that the current computing core cannot process to the FPGA computing units in each processing core for calculation. After each FPGA computing unit completes the calculation, it transmits the calculation results to the next computing core through inter-core routing to continue the calculation. Multiple processing cores with embedded FPGAs process sub-computing tasks at the same time, which greatly improves the overall computing efficiency of the chip.

[0064] The present disclosure also relates to a many-core chip, including a many-core architecture with an embedded FPGA as described in an embodiment of the present disclosure. In one practicable manner, Figure 2As shown, the multi-core chip includes a multi-core architecture with an embedded FPGA (such as an AI computing core array), an on-chip processor (such as a CPU / ARM / MCU), a PCle controller, a DMA, a general interface (such as UART / I2C / SPI / GPIO, etc.), and a DDR controller. The multi-core architecture with an embedded FPGA, the on-chip processor, the PCle controller, the DMA, the general interface, and the DDR controller communicate through a bus. On the one hand, this multi-core chip takes advantage of the FPGA's high-speed processing after pre-compilation, which can solve a lot of time-consuming problems in instruction fetching and decoding. Without changing the existing on-chip network structure, it only needs to increase the type of nodes, so that the chip can support various complex logic control operations while realizing ordinary AI calculations. On the other hand, the FPGA is integrated into the multi-core architecture (AI computing core array), and external communication is carried out through the inter-chip routing of the AI ​​computing core array to reduce chip energy consumption. The CPU / ARM / MCU only configures the FPGA during initialization. By implementing pre-compilation through FPGA, when the AI ​​computing core array performs calculations, the CPU and ARM do not need to schedule data or instructions on the FPGA, which can form a pipeline data processing mode, reduce processing delays, and improve processing efficiency.

[0065] The many-core chip described in the embodiments of the present disclosure can be applied to the field of artificial intelligence. By adding a processing core with an embedded FPGA to the AI ​​computing array, it can process algorithms that the AI ​​computing core cannot process or processes inefficiently as well as the processing of logic control and judgment instructions, which can greatly save transmission bandwidth, reduce energy consumption, improve computing efficiency, and accelerate the reasoning / training process of neural networks.

[0066] The present disclosure also relates to an electronic device, including a server, a terminal, etc. The electronic device includes: at least one processor; a memory connected to the at least one processor; and a communication component connected to the storage medium, the communication component receiving and sending data under the control of the processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to implement the data processing method of the many-core architecture embedded with FPGA in the above embodiment.

[0067] In an optional implementation, the memory is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs, and modules. The processor executes various functional applications and data processing of the device by running the non-volatile software programs, instructions, and modules stored in the memory, that is, implementing the data processing method of the many-core architecture with embedded FPGA.

[0068] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and applications required for at least one function; the data storage area may store a list of options, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to an external device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0069] One or more modules are stored in the memory, and when executed by one or more processors, the data processing method of the multi-core architecture with embedded FPGA in any of the above method embodiments is executed.

[0070] The above-mentioned product can execute the data processing method of the many-core architecture with embedded FPGA provided in the embodiment of the present application, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not described in detail in this embodiment, please refer to the data processing method of the many-core architecture with embedded FPGA provided in the embodiment of the present application.

[0071] The present disclosure also relates to a computer-readable storage medium for storing a computer-readable program, wherein the computer-readable program is used for a computer to execute part or all of the above-mentioned data processing method embodiments of a multi-core architecture with an embedded FPGA.

[0072] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0073] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0074] In addition, it will be understood by those skilled in the art that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present disclosure and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0075] It will be appreciated by those skilled in the art that, although the present disclosure has been described with reference to exemplary embodiments, various changes may be made and elements thereof may be replaced with equivalents without departing from the scope of the present disclosure. In addition, many modifications may be made to adapt specific circumstances or materials to the teachings of the present disclosure without departing from the substantive scope of the present disclosure. Therefore, the present disclosure is not limited to the specific embodiments disclosed, but the present disclosure will include all embodiments falling within the scope of the appended claims.

Claims

1. A multi-core architecture with embedded FPGA, characterized in that: include: A many-core array, the many-core array comprising a plurality of computing cores and at least one processing core integrated with an FPGA, the processing core and the plurality of computing cores are set with a synchronous clock, the processing core communicates with its adjacent computing cores via an inter-core routing; the processing core is configured by a control module during initialization of the processing core to configure the FPGA in the processing core, and the FPGA is pre-compiled; The computing core includes an AI computing unit, a storage unit, and a route, the processing core includes an FPGA computing unit, a storage unit, and a route, and the storage unit and the routing configuration of the processing core are the same as those of the multiple computing cores; The many-core array is a two-dimensional matrix network, at least one of the processing cores is arranged at the corners of the many-core array, and the processing core communicates with its two adjacent computing cores through two inter-core routing paths. The many-core architecture includes multiple processing cores, and the multiple processing cores are symmetrically arranged at the corners of the many-core array.

2. The many-core architecture with embedded FPGA according to claim 1, characterized in that: The computing core includes an AI computing unit, a storage unit and a router, the processing core includes an FPGA computing unit, a storage unit and a router, and the storage capacity of the storage unit of the processing core is different from that of the storage units of the multiple computing cores.

3. A multi-core architecture with embedded FPGA according to any one of claims 1-2, characterized in that: The many-core array is a two-dimensional matrix network, a two-dimensional ring network, a two-dimensional star network or a three-dimensional hierarchical network.

4. The many-core architecture with embedded FPGA according to claim 3, characterized in that: The many-core array is a two-dimensional matrix network, or at least one of the processing cores is arranged inside the many-core array, and the processing core communicates with four adjacent computing cores through four inter-core routing paths.

5. The many-core architecture with embedded FPGA according to claim 4, characterized in that: The many-core architecture includes a plurality of processing cores, and the plurality of processing cores are symmetrically arranged on a diagonal line inside the many-core array.

6. A data processing method for a multi-core architecture with an embedded FPGA, characterized in that: Using a multi-core architecture with an embedded FPGA as described in any one of claims 1-5, the data processing method includes: computing data that cannot be processed by the current computing core is transmitted from the current computing core to at least one processing core through inter-core routing for calculation.

7. The data processing method of a multi-core architecture with embedded FPGA according to claim 6, characterized in that: The computing data that cannot be processed by the current computing core is transmitted from the current computing core to the FPGA computing unit in at least one of the processing cores through inter-core routing for calculation. After the FPGA computing unit completes the calculation, the calculation result is transmitted to the next computing core through inter-core routing to continue the calculation.

8. The data processing method of a multi-core architecture with embedded FPGA according to claim 6, characterized in that: Dividing a single computing task into a plurality of sub-computing tasks, and assigning the plurality of sub-computing tasks to at least one of the processing cores and the plurality of computing cores for processing; At time t-1, core a processes the corresponding sub-computation task and transmits the processed data to core b; At time t, core b receives the data transmitted by core a and continues to process it, and transmits the processed data to core c; At time t+1, core c receives the data transmitted by core b and continues to process it, and transmits the processed data to other cores for further processing; Thus, on the time axis, at least one of the processing cores and the plurality of computing cores pipeline processes respective sub-computing tasks, wherein the core a, the core b, the core c and the other cores are one of the at least one of the processing cores and the plurality of computing cores; At the same time, at least one of the processing cores and the multiple computing cores process their respective sub-computing tasks in parallel.

9. The data processing method of a multi-core architecture with embedded FPGA according to claim 8, characterized in that: The computing data of the sub-computing tasks that cannot be processed by the current computing core are transmitted from the current computing core to the processing core for processing through the inter-core routing.

10. The data processing method of a multi-core architecture embedded with FPGA according to claim 9, characterized in that: Through inter-core routing, the processing core closest to the current computing core is found, and the computing data of the sub-computation task that the current computing core cannot handle is transmitted to the FPGA computing unit in the processing core for calculation. After the FPGA computing unit completes the calculation, the calculation result is transmitted to the next computing core through inter-core routing to continue the calculation.

11. The data processing method of a multi-core architecture embedded with FPGA according to claim 9, characterized in that: Through inter-core routing, multiple processing cores closest to the current computing core are found respectively, and the calculation data of multiple sub-computation tasks that the current computing core cannot handle are transmitted to the FPGA computing units in each processing core for calculation. After each FPGA computing unit completes the calculation, the calculation results are transmitted to the next computing core through inter-core routing to continue the calculation.

12. A many-core chip, characterized in that: A multi-core architecture with an embedded FPGA is included as described in any one of claims 1-5.

13. The many-core chip according to claim 12, characterized in that: It includes the many-core architecture of the embedded FPGA, an on-chip processor, a PCle controller, a DMA, a universal interface, and a DDR controller. The many-core architecture of the embedded FPGA, the on-chip processor, the PCle controller, the DMA, the universal interface, and the DDR controller communicate through a bus.

14. An electronic device comprising a memory and a processor, characterized in that: The memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement a data processing method of a multi-core architecture with an embedded FPGA as described in any one of claims 6-11.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is executed by a processor to implement a data processing method of a multi-core architecture with an embedded FPGA as claimed in any one of claims 6 to 11.

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