Source signal output circuit and inverter thereof

Abstract

The present disclosure discloses a source signal output circuit and an inverter thereof. The inverter is configured to provide a control signal with a full range to a multiplexer for selecting a source signal, and outputs a control signal with a full range by using an element operating in a low voltage range. Therefore, the present disclosure has the advantage that it can manufacture a drive circuit with a small area at a low process cost.

Description

Technical Field

[0001] The present disclosure relates to a driving circuit for a display device, and more particularly, to an inverter providing a control signal having a full range for selecting a source signal, and a source signal output circuit selecting and outputting a source signal by using the inverter. Background Art

[0002] The display device includes a driving circuit for driving a display panel such as an LCD panel or an LED panel. The driving circuit may be manufactured as an integrated circuit and mounted on the display device.

[0003] The driving circuit is used to receive display data representing the screen, generate a source signal corresponding to the display data, and provide the source signal to the display panel.

[0004] In order to reduce the area of ​​the driving circuit and improve its operating characteristics, various improvements have been made to the driving circuit.

[0005] For example, the driving circuit includes an output buffer that generates a source signal. The output buffer can be designed to generate a source signal with a full range by using an intermediate voltage between a driving voltage and a ground voltage. In this case, the full range can be understood to mean a voltage between the driving voltage and the ground voltage.

[0006] In addition, the driving circuit includes a multiplexer for transmitting the source signal of the output buffer to the display panel. The multiplexer is configured to select and output the source signal having a full range in response to the control signal.

[0007] In the driving circuit, the output buffer can be configured using transistors operating in a low voltage range to reduce the area and process cost of the driving circuit. In this case, the low voltage range can be understood to mean a voltage range from the driving voltage to the intermediate voltage, or a voltage range from the intermediate voltage to the ground voltage.

[0008] Compared to transistors operating in the full range, transistors operating in the low voltage range occupy a small area and may reduce process costs.

[0009] The driving circuit includes an inverter for providing a control signal having a full range to the multiplexer. The inverter is configured to provide the control signal to the multiplexer.

[0010] Generally, an inverter is configured by providing a control signal having a full range using a driving voltage and a ground voltage, and using transistors operating in the full range.

[0011] In the driving circuit, not only the output buffer but also the inverter needs to be configured using transistors operating in a low voltage range, so that the driving circuit with a small area can be manufactured at a low process cost. Summary of the invention

[0012] Various embodiments are directed to an inverter providing a source signal output circuit, the inverter including an element that operates in a low voltage range and can output a control signal having a full range for selecting and outputting a source signal.

[0013] Furthermore, various embodiments are directed to providing a source signal output circuit capable of controlling a multiplexer by using an inverter.

[0014] In one embodiment, a source signal output circuit may include a multiplexer configured to select a source signal having a first voltage range from a first voltage to a second voltage in response to a control signal, and an inverter configured to output a control signal by using an intermediate voltage between the first voltage and the second voltage. The inverter includes: a first inversion unit configured to provide a first inversion signal having a second voltage range from the first voltage to the intermediate voltage in response to a first input signal; a second inversion unit configured to provide a second inversion signal having a third voltage range from the intermediate voltage to the second voltage in response to a second input signal; and an output unit configured to provide a control signal having a first voltage range by outputting one of the first inversion signal and the second inversion signal.

[0015] In addition, the inverter of the source signal output circuit may include: a first inverting unit configured to provide a first inverted signal in response to a first input signal; a second inverting unit configured to provide a second inverted signal in response to a second input signal; and an output unit configured to select one of the first inverted signal and the second inverted signal, and output the selected signal as a control signal. The control signal belongs to a first voltage range from a first voltage to a second voltage. The first inverting unit uses an intermediate voltage between the first voltage and the second voltage, and outputs a first inverted signal having a second voltage range from the first voltage to the intermediate voltage. The second inverting unit uses an intermediate voltage and outputs a second inverted signal having a third voltage range from the intermediate voltage to the second voltage. The first inverting unit, the second inverting unit, and the output unit are configured to operate in a low voltage range less than the first voltage range.

[0016] The present disclosure is advantageous in that it can manufacture a driving circuit having a small area at a low process cost because an inverter for providing a control signal having a full range to a multiplexer is configured using elements operating in a low voltage range. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a circuit diagram showing a preferred embodiment of a source signal output circuit according to the present disclosure.

[0018] Figure 2 It is shown Figure 1 A circuit diagram of an embodiment of an inverter.

[0019] Figure 3 It is shown Figure 2 A circuit diagram of an inverter outputting a control signal having a voltage range from a driving voltage to an intermediate voltage.

[0020] Figure 4 It is shown Figure 2 A circuit diagram of an inverter outputting a control signal having a voltage range from an intermediate voltage to a ground voltage. DETAILED DESCRIPTION

[0021] Exemplary embodiments will be described in more detail below with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be constructed to be limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Throughout the present disclosure, in all figures and embodiments of the present disclosure, the same reference numerals represent the same parts.

[0022] You can refer to Figure 1 The source signal output circuit of the present disclosure is described.

[0023] The source signal output circuit forms part of a driving circuit manufactured as an integrated circuit, and may be shown to include output buffers BF1 and BF2 , a multiplexer MUX, and an inverter 100 .

[0024] The source signal output circuit is shown as using the driving voltage VDD as the first voltage, using the ground voltage GND as the second voltage, and using the half driving voltage HVDD as the intermediate voltage. In this case, for example, the intermediate voltage can be understood as having an intermediate level between the driving voltage VDD and the ground voltage GND.

[0025] For the description of the present disclosure, the full range is represented as a first voltage range, and can be understood as being between the drive voltage VDD (i.e., the first voltage) and the ground voltage GND (i.e., the second voltage). The second voltage range can be understood as being between the drive voltage VDD (i.e., the first voltage) and the half drive voltage HVDD (i.e., the middle voltage). The third voltage range can be understood as being between the half drive voltage HVDD (i.e., the middle voltage) and the ground voltage GND (i.e., the second voltage).

[0026] For convenience of description, VDD is represented as a first voltage, GND is represented as a second voltage, and HVDD is represented as an intermediate voltage.

[0027] The output buffer BF1 is configured to receive the first input voltage IN1 and output a source signal SO1 corresponding to the first input voltage IN1 by using the first voltage VDD and the intermediate voltage HVDD.

[0028] The output buffer BF2 is configured to receive the second input voltage IN2 and output a source signal SO2 corresponding to the second input voltage IN2 by using the intermediate voltage HVDD and the second voltage GND.

[0029] That is, the output buffer BF1 outputs the source signal SO1 having the first voltage range. The output buffer BF2 outputs the source signal SO2 having the second voltage range.

[0030] The multiplexer MUX selects the output direction of the source signal SO1 of the output buffer BF1 and the source signal SO2 of the output buffer BF2 in response to the control signal Vs, and outputs the source signal SO1 and the source signal SO2. Figure 1 In FIG. 1 , the multiplexer MUX is shown as directly outputting the source signal SO1 and the source signal SO2 with respect to the two output channels. On the other hand, the multiplexer MUX can change the channels of outputting the source signal SO1 and the source signal SO2 by cross-connection (as shown by the dotted lines) between the two output channels and between the output buffers BF1 and BF2.

[0031] That is, the multiplexer MUX is configured to output a source signal within a first voltage range (i.e., full range) for each output terminal. To this end, it is also necessary to provide a control signal Vs having a first voltage range (i.e., full range). If the control signal Vs has a first voltage range, it can be understood that the control signal Vs has a level that swings between a first voltage VDD (i.e., the highest level of the first voltage range) and a second voltage GND (i.e., the lowest level of the first voltage range).

[0032] The second voltage range and the third voltage range can be understood as belonging to the first voltage range. The control signal Vs having the second voltage range can be understood as having a high level corresponding to the first voltage VDD. The control signal Vs having the third voltage range can be understood as having a low level corresponding to the second voltage GND.

[0033] That is, for example, when the control signal Vs is provided as a first voltage VDD having a high level, the multiplexer MUX can directly output the source signal SO1 and the source signal SO2, and when the control signal Vs is provided as a second voltage GND having a low level, the multiplexer MUX can output the source signal SO1 and the source signal SO2 by crossing the source signal SO1 and the source signal SO2.

[0034] The inverter 100 is configured to receive a first input signal Vin1 and a second input signal Vin2 and output a control signal Vs based on values ​​of the first input signal Vin1 and the second input signal Vin2 .

[0035] Reference Figure 2 , the inverter 100 is configured to output the control signal Vs by using an intermediate voltage HVDD between the first voltage VDD and the second voltage GND.

[0036] To this end, the inverter 100 may be configured to include a first inverting unit 10 , a second inverting unit 20 , and an output unit 30 .

[0037] The first inversion unit 10 is configured to provide a first inversion signal having a second voltage range from a first voltage VDD to an intermediate voltage HVDD in response to a first input signal Vin1 .

[0038] Furthermore, the second inversion unit 20 is configured to provide a second inversion signal having a third voltage range from the middle voltage HVDD to the second voltage GND in response to the second input signal Vin2 .

[0039] More specifically, the first inverting unit 10 is configured to include a first pull-up element and a first pull-down element, which receive the first input signal Vin1 and output a first inverted signal by using the first voltage VDD and the intermediate voltage HVDD. In this case, the first pull-up element corresponds to the PMOS transistor Q1, and the first pull-down element corresponds to the NMOS transistor Q2.

[0040] The PMOS transistor Q1 is configured to have a source to which the first voltage VDD is applied and a gate to which the first input signal Vin1 is applied, and outputs a first inverted signal through its drain. The NMOS transistor Q2 is configured to have a source to which the intermediate voltage HVDD is applied, a gate to which the first input signal Vin1 is applied, and a drain commonly connected to the drain of the PMOS transistor Q1.

[0041] According to this configuration, the first inverting unit 10 can be understood as having a PMOS transistor Q1 (i.e., a first pull-up element) and an NMOS transistor Q2 (i.e., a first pull-down element) configured as a CMOS transistor structure, and in response to the first input signal Vin1, outputs a first inverting signal swinging within a second voltage range (i.e., between the first voltage VDD and the intermediate voltage HVDD) through a common drain.

[0042] In addition, the second inverting unit 20 is configured to include a second pull-up element and a second pull-down element, which receive the second input signal Vin2 and output a second inverted signal by using the intermediate voltage HVDD and the second voltage GND. In this case, the second pull-up element corresponds to the PMOS transistor Q3, and the second pull-down element corresponds to the NMOS transistor Q4.

[0043] The PMOS transistor Q3 is configured to have a source to which the intermediate voltage HVDD is applied, a gate to which the second input signal Vin2 is applied, and a drain commonly connected to the drain of the NMOS transistor Q4. The NMOS transistor Q4 is configured to have a source to which the second voltage GND is applied and a gate to which the second input signal Vin2 is applied, and outputs a second inverted signal through its drain.

[0044] According to this configuration, the second inverting unit 20 can be understood as having a PMOS transistor Q3 (i.e., a second pull-up element) and an NMOS transistor Q4 (i.e., a second pull-down element) configured as a CMOS transistor structure, and in response to the second input signal Vin2, outputs a second inverting signal swinging within a third voltage range (i.e., between the intermediate voltage HVDD and the second voltage GND) through a common drain.

[0045] The output unit 30 is configured to provide a control signal Vs having a first voltage range by selecting one of the first inversion signal of the first inversion unit 10 and the second inversion signal of the second inversion unit 20 and outputting the selected signal.

[0046] To this end, the output unit 30 includes a first switching unit 31 and a second switching unit 32 .

[0047] When the first inverted signal of the first inverting unit 10 belongs to the first voltage range, the first switching unit 31 is configured to output the first inverted signal as the control signal Vs.

[0048] To this end, when the gate voltage is fixed by the intermediate voltage HVDD and the potential difference between the first inversion signal of the first inversion unit 10 and the gate voltage is equal to or higher than the preset level, the first switch unit 31 outputs the first inversion signal as the control signal Vs. That is, the first switch unit 31 can be understood to include a PMOS diode, and when the intermediate voltage HVDD is applied to the gate of the PMOS diode, and the first inversion signal equal to or higher than the preset level of the intermediate voltage HVDD is applied to the source of the PMOS diode and the PMOS diode is reversely biased, the PMOS diode outputs the control signal Vs through its drain.

[0049] More specifically, the first switch unit 31 includes a PMOS transistor M1 configured to function as a PMOS diode. The PMOS transistor M1 is configured to have a gate to which the intermediate voltage HVDD is applied, a source to which the first inverting signal of the first inverting unit 10 is applied, and a reverse bias coupled to the source, and outputs the control signal Vs through its drain.

[0050] In addition, when the second inverted signal of the second inverting unit 20 belongs to the second voltage range, the second switching unit 32 is configured to output the second inverted signal as the control signal Vs.

[0051] To this end, when the gate voltage is fixed by the intermediate voltage HVDD and the potential difference between the second inversion signal of the second inversion unit 20 and the gate voltage is equal to or higher than the preset level, the second switch unit 32 outputs the second inversion signal as the control signal Vs. That is, the second switch unit 32 can be understood to include an NMOS diode, and when the intermediate voltage HVDD is applied to the gate of the NMOS diode, and the second inversion signal equal to or lower than the preset level of the intermediate voltage HVDD is applied to the source of the NMOS diode and the NMOS diode is reversely biased, the NMOS diode outputs the control signal Vs through its drain.

[0052] More specifically, the second switch unit 32 includes an NMOS transistor M2 configured to function as an NMOS diode. The NMOS transistor M2 is configured to have a gate to which the intermediate voltage HVDD is applied, a source to which the second inverting signal of the second inverting unit 20 is applied, and a reverse bias coupled to the source, and outputs the control signal Vs through its drain.

[0053] The PMOS transistor M1 included in the first switch unit 31 and the NMOS transistor M2 included in the second switch unit 32 form a common drain and are configured to output a control signal Vs through the common drain.

[0054] like Figure 2 The inverter 100 configured in Figure 3 As shown, the control signal Vs is output in response to the first input signal Vin1 having the second voltage range, or it can be output as shown Figure 4 The control signal Vs is shown output in response to the second input signal Vin2 having a third voltage range.

[0055] First, refer to Figure 3 , when the first input signal Vin1 is applied as the level of the intermediate voltage HVDD, the second input signal Vin2 is applied as the level of the second voltage GND.

[0056] When the second input signal Vin2 is applied as the level of the second voltage GND, the PMOS transistor Q3 is turned on. However, the NMOS transistor M2 remains turned off because the intermediate voltage HVDD is applied to the source and gate of the NMOS transistor M2, and a sufficient voltage for turning on the NMOS transistor M2 is not formed between the gate and source of the NMOS transistor M2. That is, the second switch unit 32 does not operate.

[0057] However, when the first input signal Vin1 is applied as the level of the intermediate voltage HVDD, the PMOS transistor Q1 is turned on. The first inversion signal having the level of the first voltage VDD is applied to the source of the PMOS transistor M1 of the first switch unit 31 by the pull-up operation of the PMOS transistor Q1.

[0058] The PMOS transistor M1 of the first switch unit 31 is turned on because the first voltage VDD is applied to the source of the PMOS transistor M1 and a sufficient voltage for turning on the PMOS transistor M1 is formed between the gate and the source of the PMOS transistor M1. That is, the first switch unit 31 is turned on and outputs the control signal Vs having the level of the first voltage VDD, that is, the first inversion signal of the first inversion unit 10.

[0059] That is, by turning on the PMOS transistor Q1 and the PMOS transistor M1 , the control signal Vs is outputted as a level of the first voltage VDD having the second voltage range.

[0060] Reference Figure 4 , when the first input signal Vin1 is applied as the level of the first voltage VDD, the second input signal Vin2 is applied as the level of the intermediate voltage HVDD.

[0061] When the first input signal Vin1 is applied as the level of the first voltage VDD, the NMOS transistor Q2 is turned on. However, the PMOS transistor M1 remains turned off because the intermediate voltage HVDD is applied to the source and gate of the PMOS transistor M1, and a sufficient voltage for turning on the PMOS transistor M1 is not formed between the gate and source of the PMOS transistor M1. That is, the first switch unit 31 does not operate.

[0062] However, when the second input signal Vin2 is applied as the level of the intermediate voltage HVDD, the NMOS transistor Q4 is turned on. The second inversion signal having the level of the second voltage GND is applied to the source of the NMOS transistor M2 of the second switch unit 32 by the pull-down operation of the NMOS transistor Q4.

[0063] The NMOS transistor M2 of the second switch unit 32 is turned on because the second voltage GND is applied to the source of the NMOS transistor M2 and a sufficient voltage for turning on the NMOS transistor M2 is formed between the gate and the source of the NMOS transistor M2. That is, the second switch unit 32 is turned on and outputs the control signal Vs having the level of the second voltage GND, that is, the second inversion signal of the second inversion unit 20.

[0064] That is, by turning on the NMOS transistor Q4 and the NMOS transistor M2 , the control signal Vs is output as a level of the second voltage GND having the third voltage range.

[0065] As described above, the control signal Vs may be output as a level of the first voltage VDD or a level of the second voltage GND. That is, the control signal Vs having a first voltage range may be provided to the multiplexer MUX.

[0066] Each of the second voltage range from the first voltage VDD to the intermediate voltage HVDD and the third voltage range from the intermediate voltage HVDD to the second voltage GND may be understood as a low voltage range smaller than the first voltage range from the first voltage VDD to the second voltage GND.

[0067] Therefore, the PMOS transistor Q1 and the NMOS transistor Q2 of the first inverting unit 10 , the PMOS transistor Q3 and the NMOS transistor Q4 of the second inverting unit 20 , and the PMOS transistor M1 and the NMOS transistor M2 of the output unit 30 may be configured to operate in a low voltage range.

[0068] The inverter 100 includes elements operating in a low voltage range and can provide a control signal Vs having a first voltage range (ie, full range). That is, by using elements operating in a low voltage range, the inverter 100 can obtain the same effect as elements having a full range.

[0069] Therefore, the present disclosure can realize a source signal output circuit by using not only the buffers BF1 and BF2 corresponding to output buffers but also the inverter 100 as an element operating in a low voltage range.

[0070] Therefore, the present disclosure is advantageous in that it can manufacture a driving circuit having a small area at a low process cost.

[0071] Although various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are only exemplary. Therefore, the disclosure described herein should not be limited based on the described embodiments.

Claims

1. Source signal output circuit, including: a multiplexer configured to select a source signal having a first voltage range from a first voltage to a second voltage in response to a control signal; as well as an inverter configured to output the control signal by using an intermediate voltage between the first voltage and the second voltage, The driving voltage is used as the first voltage, the ground voltage is used as the second voltage, and the half driving voltage is used as the intermediate voltage and has an intermediate level between the driving voltage and the ground voltage. Wherein, the inverter comprises: A first inverting unit configured to provide a first inverted signal having a second voltage range from the first voltage to the intermediate voltage in response to a first input signal; a second inverting unit configured to provide a second inverted signal having a third voltage range from the middle voltage to the second voltage in response to a second input signal; and The output unit is configured to provide the control signal having the first voltage range by outputting one of the first inverted signal and the second inverted signal.

2. The source signal output circuit according to claim 1, wherein: The second voltage range is included in a low voltage range smaller than the first voltage range, and the third voltage range is included in a low voltage range smaller than the first voltage range; and The first inverting unit, the second inverting unit, and the output unit are configured to operate within the low voltage range.

3. The source signal output circuit according to claim 1, wherein: the first inversion unit includes a first pull-up element and a first pull-down element configured to receive the first input signal and output the first inversion signal by using the first voltage and the intermediate voltage, and The second inversion unit includes a second pull-up element and a second pull-down element configured to receive the second input signal and output the second inversion signal by using the intermediate voltage and the second voltage.

4. The source signal output circuit according to claim 3, wherein: Each of the second voltage range and the third voltage range is included in a low voltage range smaller than the first voltage range, and The first pull-up element, the first pull-down element, the second pull-up element, and the second pull-down element are configured to operate within the low voltage range.

5. The source signal output circuit according to claim 1, wherein: The output unit comprises: a first switch unit, configured to output the first inverted signal as the control signal when the first inverted signal of the first inverted unit belongs to the first voltage range; and The second switch unit is configured to output the second inverted signal as the control signal when the second inverted signal of the second inverted unit belongs to the second voltage range.

6. The source signal output circuit according to claim 5, wherein: When the first gate voltage is fixed by the intermediate voltage and the potential difference between the first inverted signal and the first gate voltage is equal to or higher than a preset level, the first switching unit outputs the first inverted signal as the control signal, and When the second gate voltage is fixed by the intermediate voltage and a potential difference between the second inverted signal and the second gate voltage is equal to or higher than a preset level, the second switching unit outputs the second inverted signal as the control signal.

7. The source signal output circuit according to claim 5, wherein: The first switch unit includes a PMOS diode configured to output the control signal through a drain of the PMOS diode when the intermediate voltage is applied to a first gate of the PMOS diode and the first inverted signal equal to or higher than a preset level of the intermediate voltage is applied to a source of the PMOS diode and the PMOS diode is reverse biased, and The second switching unit includes an NMOS diode, and the NMOS diode is configured to output the control signal through the drain of the NMOS diode when the intermediate voltage is applied to the second gate of the NMOS diode and the second inverted signal equal to or lower than a preset level of the intermediate voltage is applied to the source of the NMOS diode and the NMOS diode is reverse biased.

8. An inverter of a source signal output circuit, comprising: A first inverting unit configured to provide a first inverted signal in response to a first input signal; A second inverting unit configured to provide a second inverted signal in response to a second input signal; as well as an output unit configured to output one of the first inverted signal and the second inverted signal as a control signal, wherein the control signal belongs to a first voltage range from a first voltage to a second voltage, The first inversion unit uses an intermediate voltage between the first voltage and the second voltage and outputs the first inversion signal having a second voltage range from the first voltage to the intermediate voltage, The second inversion unit uses the intermediate voltage and outputs the second inversion signal having a third voltage range from the intermediate voltage to the second voltage, and The first inverting unit, the second inverting unit and the output unit are configured to operate in a low voltage range that is smaller than the first voltage range, The output unit is configured to provide the control signal to a multiplexer for selecting a source signal having the first voltage range.

9. The inverter according to claim 8, wherein: the first inversion unit includes a first pull-up element and a first pull-down element configured to receive the first input signal and output the first inversion signal by using the first voltage and the intermediate voltage, and The second inversion unit includes a second pull-up element and a second pull-down element configured to receive the second input signal and output the second inversion signal by using the intermediate voltage and the second voltage.

10. The inverter according to claim 9, wherein: The second voltage range is included in a low voltage range smaller than the first voltage range, the third voltage range is included in a low voltage range smaller than the first voltage range, and The first pull-up element, the first pull-down element, the second pull-up element, and the second pull-down element are configured to operate within the low voltage range.

11. The inverter according to claim 8, wherein: The output unit comprises: a first switch unit, configured to output the first inverted signal as the control signal when the first inverted signal of the first inverted unit belongs to the first voltage range; and The second switch unit is configured to output the second inverted signal as the control signal when the second inverted signal of the second inverted unit belongs to the second voltage range.

12. The inverter according to claim 11, wherein: When the first gate voltage is fixed by the intermediate voltage and the potential difference between the first inverted signal and the first gate voltage is equal to or higher than a preset level, the first switching unit outputs the first inverted signal as the control signal, and When the second gate voltage is fixed by the intermediate voltage and a potential difference between the second inverted signal and the second gate voltage is equal to or higher than a preset level, the second switching unit outputs the second inverted signal as the control signal.

13. The inverter according to claim 11, wherein: The first switch unit includes a PMOS diode configured to output the control signal through a drain of the PMOS diode when the intermediate voltage is applied to a first gate of the PMOS diode and the first inverted signal equal to or higher than a preset level of the intermediate voltage is applied to a source of the PMOS diode and the PMOS diode is reverse biased, and The second switching unit includes an NMOS diode, and the NMOS diode is configured to output the control signal through the drain of the NMOS diode when the intermediate voltage is applied to the second gate of the NMOS diode and the second inverted signal equal to or lower than a preset level of the intermediate voltage is applied to the source of the NMOS diode and the NMOS diode is reverse biased.

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