Silicon carbide semiconductor device and method for manufacturing the same

Abstract

A silicon carbide semiconductor device and a method for manufacturing the same that can improve the yield are obtained. A silicon carbide layer (2) of the first conductivity type has a defect region having crystal defects. A plurality of well regions (4) of the second conductivity type are formed in the silicon carbide layer (2). A source region (6) of the first conductivity type is formed in the well region (4). A gate oxide film (7) is formed on the silicon carbide layer (2), the well region (4) and the source region (6). A gate electrode (8) is formed on the gate oxide film (7). A source electrode (10) is connected to the well region (4) and the source region (6). No source region (6) is formed in the defect region (3).

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same. Background Art

[0002] Silicon carbide crystal is expected to be a material for next-generation switching elements capable of achieving high withstand voltage, low loss, and high-temperature operation (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2012-244083

[0004] However, silicon carbide crystals contain a large number of crystal defects such as stacking faults, and current silicon carbide semiconductor devices have a problem in that leakage current is generated due to crystal defects in the wafer or crystal defects generated during epitaxial growth, which reduces the yield. Summary of the invention

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a silicon carbide semiconductor device and a method for manufacturing the same that can improve the yield.

[0006] The silicon carbide semiconductor device involved in the present invention is characterized in that it has: a silicon carbide layer of a first conductivity type, which has a defect area with crystal defects; a plurality of well areas of a second conductivity type, which are formed in the silicon carbide layer; a source area of ​​the first conductivity type, which is formed in the well area; a gate oxide film, which is formed on the silicon carbide layer, the well area and the source area; a gate electrode, which is formed on the gate oxide film; and a source electrode, which is connected to the well area and the source area, and the source area is not formed in the defect area.

[0007] Effects of the Invention

[0008] In the present invention, the source region is not formed in the defect region. If there is no source region, the transistor will not be turned on even if a voltage is applied to the gate electrode, so no leakage current will be generated. As a result, the yield can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view showing the silicon carbide semiconductor device according to the first embodiment.

[0010] Figure 2 This is a flowchart of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0011] Figure 3 FIG. 1 is a top view showing a silicon carbide wafer after epitaxial growth.

[0012] Figure 4This is a plan view showing a state in which a region where an active region is to be formed is determined on a silicon carbide wafer.

[0013] Figure 5 This is an enlarged top view showing crystal defects included in each chip.

[0014] Figure 6 This is an enlarged top view showing crystal defects included in each chip.

[0015] Figure 7 It is a cross-sectional view showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0016] Figure 8 It is a cross-sectional view showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0017] Fig. 9 It is a cross-sectional view showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0018] Fig.10 It is a cross-sectional view showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0019] Fig.11 is a cross-sectional view showing a silicon carbide semiconductor device according to a comparative example.

[0020] Fig.12 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0021] Fig.13 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0022] Fig.14 It is a top view showing a method for manufacturing a semiconductor device according to a fourth embodiment.

[0023] Fig.15 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fourth embodiment.

[0024] Fig.16 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the fifth embodiment.

[0025] Fig.17 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION

[0026] A silicon carbide semiconductor device and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components, and duplicate description may be omitted.

[0027] Implementation method 1.

[0028] Figure 1 1 is a cross-sectional view showing a silicon carbide semiconductor device according to Embodiment 1. Hereinafter, unless otherwise specified, the semiconductor device means a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). An N-type silicon carbide layer 2 is epitaxially grown on a silicon carbide substrate 1. The silicon carbide layer 2 has a defect region 3 in which a crystal defect exists. A plurality of P-type well regions 4 are formed in the silicon carbide layer 2. A P-type contact region 5 and an N-type source region 6 are formed in the well region 4. In addition, the P-type contact region 5 may not be present.

[0029] A gate oxide film 7 is formed on the silicon carbide layer 2, the well region 4, and the source region 6. A gate electrode 8 is formed on the gate oxide film 7. The gate electrode 8 is covered by an interlayer insulating film 9 such as a thermal oxide film. A source electrode 10 is formed on the silicon carbide layer 2 and the interlayer insulating film 9, and is electrically connected to the P-type contact region 5 and the source region 6. A drain electrode 11 is formed on the lower surface of the silicon carbide substrate 1. In this way, a plurality of units of the MOSFET are formed on the silicon carbide layer 2. As a feature of this embodiment, the source region 6 is not formed in the defect region 3.

[0030] Next, a method for manufacturing the silicon carbide semiconductor device according to the present embodiment will be described. Figure 2 This is a flowchart of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0031] First, silicon carbide layer 2 epitaxially grown on silicon carbide substrate 1 is inspected for crystal defects (step S1 ). Figure 3 1 is a top view showing a silicon carbide wafer after epitaxial growth. The epitaxially grown silicon carbide layer 2 mainly includes a plurality of crystal defects such as a triangle defect 12, a drop defect 13, and a carrot defect 14.

[0032] Figure 4 This is a top view showing a state where an area where an active area is formed is determined on a silicon carbide wafer. The active area is an area that actually operates as a MOSFET chip in a completed semiconductor device. An area 15 where an active area will be formed in the future is determined on a silicon carbide wafer, and information related to crystal defects in the area 15 is obtained. As information on crystal defects, for example, the size, coordinates, and shape of the crystal defects can be obtained simultaneously by using a SiC wafer defect inspection / evaluation device (SICA) produced by "Razer Tech". Figure 5 as well as Figure 6 This is an enlarged top view showing the crystal defects contained in each chip. Figure 5There are no crystal defects larger than 100 μm. Figure 6 There are crystal defects larger than 100μm in the sample.

[0033] Next, the defect information is screened (step S2). Even if the present embodiment is applied, a chip having a crystal defect 16 exceeding 100 μm is judged as unqualified (step S3) and is set as unqualified (step S4). On the other hand, if there are crystal defects less than or equal to 100 μm, regardless of the shape or number, it is judged as qualified (step S5). For the chip judged to be qualified, the position of the defect area 3 where the crystal defect exists is determined.

[0034] Figures 7 to 10 1 is a cross-sectional view showing a method for manufacturing a silicon carbide semiconductor device according to Embodiment 1. Figure 7 As shown, a plurality of well regions 4 are formed in the silicon carbide layer 2 by photolithography and implantation of aluminum (Al) (step S6). A negative resist layer 17 is applied to the entire upper surface of the silicon carbide layer 2.

[0035] Here, a common mask for exposing the negative resist layer 17 to form the source region 6 is a mask that covers the region of each well region 4 where the source region 6 is to be formed and has openings in other regions. Figure 8 As shown, the negative resist layer 17 is exposed using the common mask. Thus, the negative resist layer 17 outside the region where the source region 6 is to be formed is exposed to light and activated. In the figure, the activated portion of the negative resist layer 17 is indicated by 17a, and the inactivated portion is indicated by 17b.

[0036] Next, use a local laser exposure machine such as Fig. 9 As shown, the negative resist layer 17 located at the predetermined position of the defect region 3 is locally exposed to laser light for activation. The local laser exposure device is a commercially available device capable of local exposure at the nm level.

[0037] Next, if Fig.10 As shown, the negative resist layer 17 after exposure and laser exposure is developed so that the activated portion 17a of the negative resist layer 17 remains and the inactivated portion 17b is removed. Thus, an opening can be formed in the region outside the defective region 3 where the source region 6 is to be formed, and the negative resist layer 17 remains in the defective region 3. Using the developed negative resist layer 17 as a mask, nitrogen (N) is injected into the well region 4 as an impurity to form the source region 6 in the well region 4. At this time, the source region 6 is not formed in the defective region 3 where the negative resist layer 17 remains (step S7). Then, the negative resist layer 17 is removed.

[0038] Next, the well region 4 and the source region 6 are activated by high temperature heat treatment. Then, the gate oxide film 7, the gate electrode 8, the source electrode 10, the drain electrode 11, etc. are formed (step S8). Through the above steps, the silicon carbide semiconductor device according to the present embodiment is manufactured.

[0039] Next, the effects of the present embodiment will be described in comparison with a comparative example. Fig.11 2 is a cross-sectional view showing a silicon carbide semiconductor device according to a comparative example. In the comparative example, a source region 6 is also formed in the defect region 3. In the defect region 3, due to the disordered crystal orientation, the gate oxide film 7 is not formed, and the gate electrode 8 is in contact with the silicon carbide layer 2, resulting in current leakage. In addition, if there is a recessed portion in the silicon carbide layer 2, current leakage occurs between the source and the drain.

[0040] In contrast, in the present embodiment, the source region 6 is not formed in the defect region 3. Without the source region 6, the transistor is not turned on even if a voltage is applied to the gate electrode 8, so no leakage current is generated. As a result, the yield can be improved.

[0041] Furthermore, even when the defect region 3 exists in multiple cells instead of just one cell, the generation of leakage current can be prevented in the same manner. In the cell where the source region 6 is not formed, the flow of electrons disappears, but since there are tens of thousands of cells in the chip, even if the flow of electrons disappears in a few cells, the impact is small.

[0042] When a defective region 3 exists in one of two regions where source regions 6 are to be formed included in one well region 4, both source regions 6 are not formed. However, in order to prevent characteristic degradation, it is preferable not to form only the source region 6 where the defective region 3 exists.

[0043] Implementation method 2.

[0044] Fig.12 as well as Fig.13 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 2. As in Embodiment 1, crystal defects are inspected and a well region 4 is formed. Fig.12 As shown, a first positive resist layer 18 is applied to the entire upper surface of the silicon carbide layer 2. Next, a second positive resist layer 19 is formed on the first positive resist layer 18 in the defect region 3 by inkjet coating. As an inkjet coater, a commercially available device capable of locally coating a resist layer with a diameter of several μm is used.

[0045] Next, if Fig.13As shown, the first and second positive resist layers 18 and 19 are exposed and developed in the region where the source region 6 is to be formed. Next, N is implanted into the well region 4 using the developed first and second positive resist layers 18 and 19 as masks to form the source region 6.

[0046] Here, the thickness of the second positive resist layer 19 is the same as that of the first positive resist layer 18. Therefore, a resist layer having a thickness twice that of the normal one is applied to the defective region 3. Therefore, the first positive resist layer 18 located below the second positive resist layer 19 is not exposed, and the first positive resist layer 18 after development remains in the defective region 3. Therefore, even if N is injected, the source region 6 is not formed in the defective region 3, and thus, the same effect as that of the first embodiment can be obtained. Other structures and effects are the same as those of the first embodiment.

[0047] Implementation method 3.

[0048] As in the first embodiment, crystal defects are inspected and the well region 4 is formed. Next, a resist layer is applied to the entire upper surface of the silicon carbide layer 2. Fig.10 Similarly, the resist layer after exposure and development is used as a mask to inject N into the well region 4 to form the source region 6. Here, in this embodiment, the resist layer is exposed by a commercially available maskless exposure machine. The maskless exposure machine generates and prepares the usual mask data for forming the source region 6 and the mask data matching the position of the defect region 3 in units of wafers. Then, the resist layer is exposed based on the generated mask data by the maskless exposure machine in such a way that the developed resist layer remains in the defect region 3. Therefore, even if impurities are injected, the source region 6 is not formed in the defect region 3, and therefore, the same effect as in embodiment 1 can be obtained. Other structures and effects are the same as in embodiment 1. In addition, the resist layer used for exposure by the maskless exposure machine can be a positive resist layer or a negative resist layer. In addition, exposure can be performed in units of chips or in units of wafers.

[0049] Implementation method 4.

[0050] Fig.14 It is a top view showing a method for manufacturing a semiconductor device according to a fourth embodiment. Fig.15: is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 4. As in Embodiment 1, crystal defects are inspected and a well region 4 is formed. Next, an insulating film 20 such as a nitride film or an oxide film is formed on the entire upper surface of the silicon carbide layer 2 by CVD. The thickness of the insulating film 20 is about 2 μm, but it can also be thicker. Next, an anti-etching layer is applied to the entire surface, and the anti-etching layer above the defective region 3 is left by exposure and development. After the insulating film 20 is etched using the anti-etching layer as a mask, the anti-etching layer is removed. Thus, as shown in FIG. Fig.14 As shown, the insulating film 20 remains above the defect region 3 .

[0051] Next, a resist layer is applied to the entire upper surface of the silicon carbide layer 2, and a conventional mask exposure is performed. Fig.15 As shown, a resist pattern 21 is formed, and the resist pattern 21 has openings in the areas where the source regions 6 are to be formed in the plurality of well regions 4. Next, N is injected into the well regions 4 using the resist pattern 21 and the insulating film 20 as masks to form the source regions 6. Since impurities are not injected into the portion where the insulating film 20 is formed, the source region 6 is not formed in the defective region 3. Therefore, the same effect as in embodiment 1 can be obtained. Other structures and effects are the same as in embodiment 1. In addition, the resist pattern 21 can be a positive resist layer or a negative resist layer.

[0052] Implementation method 5.

[0053] Fig.16 as well as Fig.17 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 5. As in Embodiment 1, crystal defects are inspected and a well region 4 is formed. Fig.16 As shown, N is implanted using a normal resist pattern 22 in which an opening is opened in a region where the source region 6 is to be formed, and the source region 6 is formed in each of the plurality of well regions 4. At this time, the source region 6 is formed in all the well regions 4, including the well region 4 where the defective region 3 exists. Then, the resist pattern 22 is removed.

[0054] Next, if Fig.17 As shown, a positive resist layer 23 is applied to the entire upper surface of the silicon carbide layer 2. The positive resist layer 23 in the defective region 3 is removed by exposure and development using a maskless exposure machine or a laser exposure machine. The positive resist layer 23 is used as a mask to implant Al into the defective region 3, thereby eliminating the source region 6 present in the defective region 3. Since there is no source region 6 in the defective region 3, the same effect as in the first embodiment can be obtained. The other structures and effects are the same as those in the first embodiment.

[0055] Description of the label

[0056] 2 silicon carbide layer, 3 defect region, 4 well region, 6 source region, 7 gate oxide film, 8 gate electrode, 10 source electrode, 17 negative resist layer, 18 first positive resist layer, 19 second positive resist layer, 20 insulating film, 21 resist pattern.

Claims

1. A silicon carbide semiconductor device, characterized in that: have: A first conductive type silicon carbide layer having a defect region where a crystal defect exists, wherein the crystal defect includes a triangle defect, a drop defect, or a carrot defect having a size of less than or equal to 100 μm; a plurality of well regions of the second conductivity type, which are formed in the silicon carbide layer; a source region of the first conductivity type, formed in the well region; a gate oxide film formed on the silicon carbide layer, the well region, and the source region; a gate electrode formed on the gate oxide film; as well as a source electrode connected to the well region and the source region, The source region is not formed in the defect region.

2. A method for manufacturing a silicon carbide semiconductor device, characterized in that: It has the following processes: Inspecting the crystal defects of the first conductive type silicon carbide layer to determine the location of a defect region where the crystal defects exist, wherein the crystal defects include triangle defects, drop defects or carrot defects less than or equal to 100 μm generated by epitaxial growth; forming a plurality of well regions of the second conductivity type in the silicon carbide layer; forming a source region of the first conductivity type in the well region; forming a gate oxide film on the silicon carbide layer, the well region, and the source region; forming a gate electrode on the gate oxide film; as well as forming a source electrode connected to the well region and the source region, The source region is not formed in the defect region.

3. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein: It has the following processes: applying a negative resist layer on the silicon carbide layer; exposing the negative resist layer outside the region where the source region is to be formed; locally performing laser exposure on the negative resist layer located in the defective area; Developing the negative resist layer after exposure and laser exposure; as well as The developed negative resist layer is used as a mask to implant impurities into the well region to form the source region.

4. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein: It has the following processes: Applying a first positive resist layer on the silicon carbide layer; In the defective region, forming a second positive resist layer on the first positive resist layer; exposing and developing the first and second positive resist layers located in a region where the source region is to be formed; and Using the developed first and second positive resist layers as masks, impurities are implanted into the well region to form the source region. The first positive resist layer remains in the defective region after development.

5. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein: It has the following processes: Applying an anti-corrosion layer on the silicon carbide layer; as well as The exposed and developed resist layer is used as a mask to inject impurities into the well region to form the source region. The resist layer is exposed by a maskless exposure device so that the developed resist layer remains in the defect region.

6. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein: It has the following processes: forming an insulating film on the defective region; forming, on the silicon carbide layer, a resist pattern in which an opening is opened in a region where the source region is to be formed; as well as The source region is formed by implanting impurities into the well region using the resist pattern and the insulating film as masks.

7. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein: It has the following processes: forming the source regions in the plurality of well regions respectively; as well as The source region present in the defect region is eliminated by implanting impurities of the second conductivity type into the defect region.

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