T-type double-channel transistor and manufacturing method, semiconductor device and manufacturing method

Abstract

The embodiment of the present application provides a T-type double-channel transistor and a manufacturing method, a semiconductor device and a manufacturing method. The manufacturing method of the T-type double-channel transistor includes: providing a wafer, the wafer having a plurality of transistor forming regions, each transistor forming region having a transistor column, each transistor column having a relatively exposed first step sidewall and a second step sidewall in a first direction; forming a gate oxide layer and a gate having a step structure on the first step sidewall and the second step sidewall in sequence; forming a source at a first end of the transistor column; forming a drain at a second end of the transistor column, wherein the first end and the second end are respectively opposite ends of the transistor column in a second direction, the second direction is a thickness direction of the wafer, and the second direction is perpendicular to the first direction; the transistor column between the source and the drain constitutes a double channel region of the T-type double-channel transistor.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and relates to but is not limited to a T-type double-channel transistor and a manufacturing method, a semiconductor device and a manufacturing method. Background Art

[0002] Transistors are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in dynamic random access memory (DRAM) to control the capacitance in each DRAM storage cell.

[0003] In the related art, the structure of transistors is mainly planar transistors and buried channel transistors. Regardless of the planar transistor structure or the buried channel transistor structure, the source (Source, S) and drain (Drain, D) are located on both sides of the gate (G). In this structure, the source and drain occupy different positions, making the area of ​​the transistor larger. In addition, in the memory device, the source and drain of the transistor will be connected to different structures after formation. When the source and drain are located on both sides of the gate, it is easy to cause the circuit wiring inside the memory to be complicated and the manufacturing process to be difficult. Summary of the invention

[0004] In view of this, embodiments of the present application provide a T-type double-channel transistor and a manufacturing method, a semiconductor device and a manufacturing method.

[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a T-type double-channel transistor, the method comprising:

[0006] A wafer is provided, wherein the wafer has a plurality of transistor forming regions, each of the transistor forming regions has a transistor column, and each of the transistor columns has a first step sidewall and a second step sidewall that are relatively exposed in a first direction;

[0007] Sequentially forming a gate oxide layer and a gate having a step structure on the first step sidewall and the second step sidewall respectively;

[0008] forming a source electrode at a first end of the transistor column;

[0009] A drain is formed at the second end of the transistor column, wherein the first end and the second end are two opposite ends of the transistor column in a second direction, the second direction is the thickness direction of the wafer, and the second direction is perpendicular to the first direction; the transistor column between the source and the drain constitutes a double channel region of the T-type double channel transistor.

[0010] In some embodiments, the transistor formation region is formed by:

[0011] Along the second direction, taking the first surface of the wafer as the etching starting point, the wafer is partially etched to form a grid-shaped etching groove composed of a plurality of silicon pillars; wherein each of the silicon pillars has a first preset thickness, and the first preset thickness is less than the initial thickness of the wafer; the first surface of the wafer is any surface of the wafer along the second direction;

[0012] Depositing insulating material in the grid-shaped etched grooves to form an insulating layer surrounding each of the silicon pillars;

[0013] The silicon column and the insulating layer are etched to form a transistor column having the first step sidewall and the second step sidewall, and an etched groove located on the first step sidewall and the second step sidewall, so as to obtain the transistor forming region.

[0014] In some embodiments, etching the silicon pillar and the insulating layer to form a transistor pillar having the first step sidewall and the second step sidewall, and an etched groove located on the first step sidewall and the second step sidewall, comprises:

[0015] Partially etching the silicon pillar and both sides of the insulating layer along the third direction to remove the silicon pillar having the first preset thickness in the first direction and the second preset thickness in the second direction; and

[0016] Removing the insulating layer having the first preset thickness in the first direction and the third preset thickness in the second direction, forming a transistor column having a step sidewall having a fourth preset thickness in the second direction, and an etched groove adjacent to the first step sidewall and the second step sidewall;

[0017] Among them, the first preset thickness is less than half of the initial thickness of the silicon column in the first direction; the second preset thickness is less than the third preset thickness, and the sum of the second preset thickness and the fourth preset thickness is equal to the third preset thickness.

[0018] In some embodiments, the step of sequentially forming a gate oxide layer and a gate having a step structure on the first step sidewall and the second step sidewall, respectively, comprises:

[0019] Forming an initial gate oxide layer having the step structure on the first step sidewall and the second step sidewall of the transistor column respectively by in-situ oxidation;

[0020] Depositing polysilicon material in each of the etched grooves to form a polysilicon layer;

[0021] In the second direction, each of the initial gate oxide layers with a step structure and each of the polysilicon layers are etched simultaneously to remove a portion of the thickness of the initial gate oxide layer with a step structure and the polysilicon layer in the second direction to form the gate oxide layer with a step structure and the gate.

[0022] In some embodiments, after forming the gate oxide layer and the gate, the method further includes:

[0023] The insulating material is deposited in each of the etched grooves to form an isolation layer; wherein the sum of the thicknesses of the isolation layer, the gate and the step sidewall in the second direction is equal to the thickness of the transistor column in the second direction.

[0024] In some embodiments, before forming the drain, the method further includes:

[0025] Starting from the second side of the wafer, the wafer is thinned until the second end of the transistor column is exposed; wherein the second side of the wafer is a side opposite to the first side of the wafer.

[0026] In some embodiments, forming a drain at the second end of the transistor column includes:

[0027] Ion implantation is performed on the second end of the transistor column to form the drain electrode having a fifth preset thickness in the second direction; wherein the fifth preset thickness is less than or equal to the fourth preset thickness.

[0028] In a second aspect, an embodiment of the present application provides a T-type double-channel transistor, the transistor comprising:

[0029] Double channel area;

[0030] a source electrode, located at a first end of the double channel region;

[0031] a drain electrode located at the second end of the dual channel region, wherein the first end and the second end are two opposite ends of the dual channel region in a second direction, and the second direction is a thickness direction of a wafer forming the dual channel region; the source electrode, the drain electrode and the dual channel region form a T-shaped structure;

[0032] A double gate, located at two sides of the double channel region, and each of the gates corresponds to the double channel region;

[0033] The gate oxide layer with a step structure is located between the double channel region and each of the gates.

[0034] In a third aspect, an embodiment of the present application provides a method for forming a semiconductor device, the method comprising:

[0035] Forming at least one memory cell, wherein each of the memory cells at least comprises: a T-type double-channel transistor; the T-type double-channel transistor comprises: a gate, a source, and a drain; the T-type double-channel transistor is manufactured by a manufacturing method of a T-type double-channel transistor;

[0036] forming a word line, wherein the word line is connected to the gate of the T-type double-channel transistor, the word line is used to provide a word line voltage, and the T-type double-channel transistor is controlled to be turned on or off by the word line voltage;

[0037] A bit line is formed, wherein the bit line is connected to a source or a drain of the T-type double channel transistor, and the bit line is used to perform a read or write operation on the memory cell when the T-type double channel transistor is turned on.

[0038] In a fourth aspect, an embodiment of the present application provides a semiconductor device, comprising: at least one memory cell, a word line, and a bit line, each of the memory cells at least comprising: a T-type double-channel transistor; the T-type double-channel transistor at least comprising: a gate, a source, and a drain;

[0039] The word line is connected to the gate of the T-type double-channel transistor, and the word line is used to provide a word line voltage, and the T-type double-channel transistor is controlled to be turned on or off by the word line voltage;

[0040] The bit line is connected to a source or a drain of the T-type double channel transistor, and the bit line is used to perform a read or write operation on the memory cell when the T-type double channel transistor is turned on.

[0041] The T-type double-channel transistor and manufacturing method, semiconductor device and manufacturing method provided by the embodiments of the present application, since the source and drain of the formed T-type double-channel transistor are respectively located at the first end and the second end of the channel region in the second direction, and the second direction is the thickness direction of the wafer forming the channel region, thus greatly reducing the area of ​​the transistor, and the T-type double-channel transistor provided by the embodiments of the present application can be used to form a memory, since the drain and source of the transistor are located on different surfaces of the wafer, thus, the different structures connected to the source and drain in the memory can be designed respectively on the two surfaces of the wafer, that is, respectively designed on the two opposite surfaces of the wafer, thereby simplifying the circuit layout inside the memory and reducing the process difficulty of memory manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0043] Figure 1A It is a schematic diagram of the structure of a planar transistor in the related art;

[0044] Figure 1B It is a structural schematic diagram of a buried channel transistor in the related art;

[0045] Figure 1C A DRAM memory cell formed by a planar transistor in the related art;

[0046] Figure 1D A DRAM memory cell formed by a buried channel transistor structure in the related art;

[0047] Figure 2 A schematic diagram of an optional structure of a T-type double-channel transistor provided in an embodiment of the present application;

[0048] Figure 3A An optional flow chart of a method for manufacturing a T-type double-channel transistor provided in an embodiment of the present application;

[0049] Figure 3B A cross-sectional view of a grid-shaped etched groove along a second direction provided in an embodiment of the present application;

[0050] Figure 3C A top view along the second direction of the grid-shaped etched grooves provided in an embodiment of the present application;

[0051] Figure 3D A schematic diagram of a structure for forming an insulating layer provided in an embodiment of the present application;

[0052] Figure 3E A top view of forming a transistor column provided in an embodiment of the present application;

[0053] Figure 3F A schematic diagram of the structure of a transistor forming region provided in an embodiment of the present application;

[0054] Figure 3G A schematic diagram of a structure for forming an initial gate oxide layer having a step structure provided in an embodiment of the present application;

[0055] Figure 3H A schematic diagram of a structure of a gate oxide layer and a gate having a step structure provided in an embodiment of the present application;

[0056] Fig. 3IA schematic diagram of a structure for forming an isolation layer provided in an embodiment of the present application;

[0057] Figure 3J A schematic diagram of a structure for forming a source electrode provided in an embodiment of the present application;

[0058] Figure 3K A schematic diagram of the structure of a transistor after thinning the second surface of the wafer provided in an embodiment of the present application;

[0059] Figure 3L A schematic diagram of a structure for forming a drain electrode provided in an embodiment of the present application;

[0060] Figure 3M A schematic diagram of a structure for forming a drain electrode provided in an embodiment of the present application;

[0061] Figure 3N A cross-sectional view of a T-type double-channel transistor provided in an embodiment of the present application along a third direction;

[0062] Fig.3O A cross-sectional view of a T-type double-channel transistor provided in an embodiment of the present application along a third direction;

[0063] Figure 3P A cross-sectional view of a T-type double-channel transistor provided in an embodiment of the present application along a third direction;

[0064] Figure 3Q A cross-sectional view of a T-type double-channel transistor provided in an embodiment of the present application along a third direction;

[0065] Figure 3R A cross-sectional view of a T-type double-channel transistor provided in an embodiment of the present application along a third direction;

[0066] Figure 4A An optional structural schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0067] Figure 4B A top view of a semiconductor device provided by an embodiment of the present application along a second direction;

[0068] Figure 4C A schematic diagram of an optional structure of a DRAM storage unit provided in an embodiment of the present application;

[0069] Figure 4D A schematic diagram of an optional structure of a PCM storage unit provided in an embodiment of the present application;

[0070] Figure 5 An optional structural schematic diagram of a method for forming a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the specific technical solution of the invention will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0072] In the following description, the suffixes such as "module" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module" or "unit" can be used mixedly.

[0073] In the related art, the mainstream memory transistor structures are mainly planar transistors and buried channel array transistors (BCAT). Regardless of whether it is a planar transistor or a buried channel transistor, the source and the drain are located on both sides of the gate in the structure. Figure 1A is a schematic diagram of the structure of a planar transistor in the related art, Figure 1B Schematic diagram of the structure of a buried channel transistor in the related art, such as Figure 1A and 1B As shown, the source S and drain D of the transistor in the related art are respectively located on both sides of the horizontal grid G. In this structure, the source and drain occupy different positions, so that the area of ​​the transistor is larger.

[0074] In addition, since transistors can be fabricated on silicon substrates, they can be used in various memories, such as DRAM. Typically, DRAM is composed of multiple memory cells, each of which is mainly composed of a transistor and a capacitor controlled by the transistor, that is, a memory cell of 1 transistor and 1 capacitor C (1T1C). Figure 1C A DRAM memory cell formed by a planar transistor in the related art. Figure 1D A DRAM memory cell formed by a buried channel transistor structure in the related art, such as Figure 1C and 1DAs shown, the source (or drain) 101 of the transistor in the DRAM memory cell is connected to the bit line 102, and the drain (or source) 103 is connected to the capacitor 104. For the chip formed by BCAT, it is usually packaged in a chip on board (COB) manner to form a memory. Since the source and drain of the planar transistor and the buried channel transistor are respectively located on both sides of the gate level, the bit line and the capacitor in the DRAM memory cell will also be located on the same side of the gate, and the subsequent process also needs to realize the connection between the bit line, the transistor and the capacitor, the connection between the word line (WL) and the transistor, etc., which leads to complex circuit wiring in the storage array area of ​​the memory and greater difficulty in the manufacturing process.

[0075] Based on the above-mentioned problems existing in the related art, the embodiments of the present application provide a T-type double-channel transistor and a manufacturing method, a semiconductor device and a manufacturing method, which can provide a T-type double-channel transistor structure with a smaller area. Moreover, the T-type double-channel transistor structure provided by the embodiments of the present application can simplify the circuit layout inside the memory and reduce the process difficulty of memory manufacturing.

[0076] Figure 2 An optional structural diagram of a T-type double-channel transistor provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the T-type double-channel transistor 20 includes: a double-channel region 201 , a source 202 , a drain 203 , a gate 204 , and a gate oxide layer 205 having a step structure.

[0077] The source 202 is located at the first end of the dual channel region 201; the drain 203 is located at the second end of the dual channel region 201, wherein the first end and the second end are two opposite ends of the dual channel region in the second direction, and the second direction is the thickness direction of the wafer forming the dual channel region (such as Figure 2 In the embodiment of the present application, the positions of the source 202 and the drain 203 can be interchanged.

[0078] The gate 204 is a symmetrical double gate structure located on both sides of the double channel region 201 , and each gate 204 corresponds to the double channel region 201 . A gate oxide layer 205 with a step structure is located between the double channel region 201 and each gate 204 .

[0079] In the embodiment of the present application, from the overall point of view, the transistor finally formed is a T-type double-channel transistor, that is, the source, drain and double-channel region of the transistor together form a T-type structure, wherein the double-channel region can be a vertical double-channel region or a double-channel region with a T-type structure. When the double-channel region is a vertical double-channel region, the source (or drain) located on one side of the double-channel region has a T-type structure; when the double-channel region is a T-type structure, the source (or drain) located on one side of the double-channel region has a planar structure. Of course, the double-channel region can also be understood as a channel region formed by the merger of two single-channel regions, that is, two single-channel regions are connected to form the double-channel region, wherein each single-channel region corresponds to a gate.

[0080] In the embodiment of the present application, the source and the drain are respectively located at opposite ends in the thickness direction of the wafer forming the dual channel region, that is, the source and the drain of the T-type dual channel transistor provided in the embodiment of the present application are located on two opposite surfaces of the wafer, thus greatly reducing the area of ​​the transistor.

[0081] The T-type double-channel transistor provided in the embodiment of the present application can be formed by the manufacturing method of the T-type double-channel transistor provided in the following embodiment.

[0082] Figure 3A An optional flow chart of a method for manufacturing a T-type double-channel transistor provided in an embodiment of the present application is shown as follows: Figure 3A As shown, the manufacturing method of the T-type double-channel transistor includes the following steps:

[0083] Step S301, providing a wafer, wherein the wafer has a plurality of transistor forming regions, each of the transistor forming regions has a transistor column, and each of the transistor columns has a first step sidewall and a second step sidewall that are relatively exposed in a first direction.

[0084] Step S302 : sequentially forming a gate oxide layer and a gate having a step structure on the first step sidewall and the second step sidewall, respectively.

[0085] Step S303: forming a source at the first end of the transistor column.

[0086] Step S304: forming a drain at the second end of the transistor column.

[0087] A drain is formed at the second end of the transistor column, wherein the first end and the second end are two opposite ends of the transistor column in a second direction, the second direction is the thickness direction of the wafer, and the second direction is perpendicular to the first direction; the transistor column between the source and the drain constitutes a double channel region of the T-type double channel transistor.

[0088] Please refer to the following FIG. 3B to FIG. 3M , the manufacturing method of the T-type double-channel transistor provided in the embodiment of the present application is further described in detail.

[0089] In the embodiment of the present application, the T-type double-channel transistor formation region is an area on the wafer for forming the transistor, each of the T-type double-channel transistor formation regions has a transistor column, each transistor column has a first step sidewall and a second step sidewall that are relatively exposed in the first direction, wherein the first step sidewall (or the second step sidewall) can be formed by two vertical surfaces, for example, the first step sidewall (or the second step sidewall) can be formed by a vertical surface and a horizontal surface, and the vertical surface is perpendicular to the horizontal surface; or, the first step sidewall (or the second step sidewall) can also be in the form of two surfaces with a certain angle, for example, the first step sidewall (or the second step sidewall) can be formed by a vertical surface and a plane, and there is a preset angle between the vertical surface and the plane, and the preset angle can be any angle greater than 0 degrees and less than 90 degrees, or it can also be any angle greater than 90 degrees and less than 135 degrees. In the embodiment of the present application, the transistor formation region also has an insulating layer that wraps the other sidewalls of the transistor column.

[0090] Below, please refer to FIG. 3B to FIG. 3E , perform the steps in step S301: provide a wafer, the wafer has a plurality of transistor formation regions, each of the transistor formation regions has a transistor column, each of the transistor columns has a first step sidewall and a second step sidewall that are relatively exposed in a first direction. In some embodiments, the T-type double channel transistor formation region is formed by the following steps:

[0091] Step S3011, along the second direction, taking the first surface of the wafer as the etching starting point, partially etching the wafer to form a grid-shaped etching groove composed of a plurality of silicon pillars.

[0092] Each of the silicon pillars has a first preset thickness, and the first preset thickness is less than an initial thickness of the wafer; and the first surface of the wafer is any surface of the wafer along the second direction.

[0093] Here, the thickness direction of the wafer is defined as the second direction. Two mutually intersecting first directions and third directions are defined on the top surface or bottom surface of the wafer, and the top surface or bottom surface of the wafer can be determined based on the first direction and the third direction.

[0094] In some embodiments, the third direction is perpendicular to the second direction and the first direction. It should be noted that in other embodiments, the third direction may not be perpendicular to the second direction, and the angle between the third direction and the second direction may be any angle.

[0095] Here, the first direction may be an X-axis direction, the second direction may be a Z-axis direction, and the third direction may be a Y-axis direction.

[0096] Figure 3B A cross-sectional view of a grid-shaped etched groove along a second direction provided in an embodiment of the present application, Figure 3C A top view of a grid-shaped etched groove along a second direction provided in an embodiment of the present application, combined with Figure 3B and 3C , it can be seen that along the second direction, with the first surface 30-1 of the wafer as the etching starting point, the wafer 30 is partially etched to form a grid-like etched groove 31 composed of a plurality of silicon pillars 301, wherein each silicon pillar 301 is located at an intersection in the grid, and there is an equal gap between any two adjacent silicon pillars. In the embodiment of the present application, each silicon pillar 301 has a first preset thickness A in the Z-axis direction, and the first preset thickness is less than the initial thickness B of the wafer; the first surface 30-1 of the wafer is any one surface of the wafer along the Z-axis direction, and the second surface 30-2 of the wafer is a surface corresponding to the first surface 30-1 of the wafer along the Z-axis direction.

[0097] Here, a dry etching process may be used to etch the wafer, for example, a plasma etching process or a reactive ion etching process. It is worth noting that in the embodiment of the present application, the etching of the wafer is a partial etching in the thickness direction of the wafer, that is, the etching process will not etch through the wafer.

[0098] Step S3012: depositing insulating material in the grid-shaped etched grooves to form an insulating layer surrounding each of the silicon pillars.

[0099] In the embodiment of the present application, the insulating material may be silicon dioxide material or other insulating materials. Figure 3D A schematic diagram of a structure for forming an insulating layer provided in an embodiment of the present application is shown in FIG. Figure 3D As shown, an insulating material SiO2 is deposited in the grid-shaped etched grooves 31 , and the surrounding of each silicon pillar 301 is filled with the insulating material SiO2 to form an insulating layer 302 .

[0100] It should be noted that in the actual process of depositing the insulating material, the insulating material SiO2 will cover the surface of the silicon column 301. Usually after the deposition is completed, a chemical mechanical polishing (CMP) process is used to polish and remove excess insulating material SiO2 to expose the surface of the silicon column 301.

[0101] Step S3013, etching the silicon column and the insulating layer to form a transistor column having the first step sidewall and the second step sidewall, and an etched groove located on the first step sidewall and the second step sidewall, to obtain the transistor formation area.

[0102] In some embodiments, the silicon pillar and the insulating layer are etched to form a transistor pillar having the first step sidewall and the second step sidewall, and an etching groove located on the first step sidewall and the second step sidewall, to obtain the transistor formation area, including: partially etching both sides of the silicon pillar and the insulating layer along a third direction to remove the silicon pillar having a first preset thickness in the first direction and a second preset thickness in the second direction; and removing the insulating layer having the first preset thickness in the first direction and a third preset thickness in the second direction to form a transistor pillar having a step sidewall having a fourth preset thickness in the second direction, and an etching groove adjacent to the first step sidewall and the second step sidewall; wherein the first preset thickness is less than half of the initial thickness of the silicon pillar in the first direction; the second preset thickness is less than the third preset thickness, and the sum of the second preset thickness and the fourth preset thickness is equal to the third preset thickness.

[0103] based on Figure 3D , Figure 3E A top view of a transistor column formed according to an embodiment of the present application, Figure 3F A schematic diagram of the structure of the transistor formation region provided in the embodiment of the present application, such as Figure 3E and Figure 3F As shown, along the Z-axis direction, both sides of the silicon pillar 301 and the partial insulating layer 303 in the insulating layer 302 are partially etched (here, the partial insulating layer refers to the insulating layer in a transistor formation area, such as Figure 3E 303), removing the silicon pillar having the first preset thickness C in the first direction and the second preset thickness E in the second direction; and removing the insulating layer having the first preset thickness C in the first direction and the third preset thickness F in the second direction, to obtain an etched groove 304, forming a transistor pillar 305 having a step sidewall having a fourth preset thickness G in the second direction, and an etched groove 304 adjacent to the first step sidewall and the second step sidewall ( Figure 3G ), and then forming a transistor forming region 30' (such as Figure 3E The transistor column 305 has exposed first step sidewalls 305 - 1 and second step sidewalls 305 - 2 on both sides.

[0104] In an embodiment of the present application, the first preset thickness C is less than half of the initial size D of the silicon column 302 in the X-axis direction; the second preset thickness E is less than the third preset thickness F, and the sum of the second preset thickness E and the fourth preset thickness G is equal to the third preset thickness F.

[0105] It should be noted that many transistors will be formed on a wafer, so there are multiple transistor formation regions in a wafer. In the embodiment of the present application, for the sake of convenience of explanation, only a limited number of transistor formation regions are shown as an example.

[0106] See next Figure 3F and Figure 3H , executing step S302, forming a gate oxide layer and a gate having a step structure on the first step sidewall and the second step sidewall respectively.

[0107] In some embodiments, before executing step S302, the transistor manufacturing method further includes:

[0108] Step S10: depositing the insulating material at the bottom of each of the etched grooves to form a third insulating layer.

[0109] In some embodiments, please refer to Figure 3F , in each etched groove ( Figure 3F An insulating material is deposited at the bottom of the projection position of the insulating layer in the X-axis direction to form a third insulating layer ( Figure 3F (not shown in the figure), the thickness of the third insulating layer is the same as the thickness I of the step sidewall of the transistor column 305.

[0110] Here, the material of the third insulating layer includes but is not limited to any one of the following: silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide.

[0111] Next, a transistor column on a wafer is taken as an example to explain the subsequent formation process.

[0112] In some embodiments, after forming the third insulating layer, the process of forming the gate oxide layer and the gate with a step structure is performed, wherein the step of sequentially forming the gate oxide layer and the gate with a step structure on the step sidewall of each transistor column comprises the following steps:

[0113] Step S3021 , forming an initial gate oxide layer having the step structure on the first step sidewall and the second step sidewall of the transistor column respectively by in-situ oxidation.

[0114] Figure 3GA schematic diagram of a structure of forming an initial gate oxide layer having a step structure provided in an embodiment of the present application, such as Figure 3F and Figure 3G As shown, here, the exposed portions of the first step sidewall 305 - 1 and the second step sidewall 305 - 2 of the transistor column 305 can be in-situ oxidized by heating or pressurizing to form an initial gate oxide layer 306 .

[0115] Step S3022: depositing polysilicon material in each of the etched grooves to form a polysilicon layer.

[0116] Here, a polysilicon layer may be formed by depositing polysilicon material in the etched groove after the third insulating layer is deposited through a process of chemical vapor deposition (PVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0117] Step S3023: In the second direction, each of the initial gate oxide layers with a step structure and each of the polysilicon layers are simultaneously etched to remove a portion of the thickness of the initial gate oxide layer with a step structure and the polysilicon layer in the second direction to form the gate oxide layer with a step structure and the gate.

[0118] Figure 3H A schematic diagram of a structure of a gate oxide layer and a gate having a step structure provided in an embodiment of the present application, such as Figure 3H As shown, the initial gate oxide layer 306 and the polysilicon layer with a step structure formed above are partially etched simultaneously along the Z-axis direction to obtain a gate oxide layer 307 and a gate 308 with a step structure. In the embodiment of the present application, a dry etching technique can be used to etch the initial gate oxide layer with a step structure and the polysilicon layer.

[0119] In some embodiments, after forming a gate oxide layer and a gate having a step structure, the method for manufacturing a transistor further includes:

[0120] Step S11, depositing the insulating material in each of the etched grooves to form an isolation layer; wherein the sum of the thicknesses of the isolation layer, the gate and the step sidewall in the second direction is equal to the thickness of the transistor column in the second direction.

[0121] Here, the material of the isolation layer includes but is not limited to any one of the following: silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide; the material of the isolation layer is the same as or different from that of the insulating layer.

[0122] In some embodiments, when forming the isolation layer, the insulating material will cover the surface of the silicon pillar. Usually, after the deposition is completed, the CMP process is used to polish and remove the excess insulating material to expose the surface of the silicon pillar.

[0123] Fig. 3I A schematic diagram of a structure for forming an isolation layer provided in an embodiment of the present application is shown in FIG. Fig. 3I As shown, the isolation layer 309 is located in the projection area of ​​the transistor column 305 and the etched insulating layer in the X-axis direction, and the sum of the thicknesses of the isolation layer 309, the gate 308 and the step sidewalls of the transistor column 305 in the Z-axis direction is equal to the thickness of the transistor column 305 in the Z-axis direction.

[0124] Next reference Figure 3J , execute step S303 to form a source at the first end of the transistor column.

[0125] Here, the first end of the transistor column is one end of the transistor column in the Z-axis direction. Figure 3J A schematic diagram of a structure for forming a source electrode provided in an embodiment of the present application is shown in FIG. Figure 3L As shown, the source 310 is formed by implanting the first end of the transistor column.

[0126] In some embodiments, the shape of the source electrode includes any one of the following: square, semicircle, triangle, or any polygon.

[0127] In some embodiments, before executing step S304, the transistor manufacturing method further includes:

[0128] Step S12, starting from the second surface of the wafer, thinning the wafer until the second end of the transistor column is exposed; wherein the second surface of the wafer is a surface opposite to the first surface of the wafer.

[0129] Here, please continue to see Figure 3J The second surface 30-2 of the wafer is opposite to the first surface 30-1 of the wafer. In the embodiment of the present application, before thinning the second surface of the wafer, the first surface of the wafer needs to be fixed on a support structure to prevent the structure of the transistor from being damaged when thinning the second surface 30-2 of the wafer.

[0130] The first end and the second end are two opposite ends of the transistor column in the second direction. Figure 3K A schematic diagram of the structure of a transistor after thinning the second surface of the wafer according to an embodiment of the present application is provided, such as Figure 3K As shown, the second surface of the wafer is thinned to expose the second end 311 ′ of the transistor column.

[0131] Next, refer to Figure 3L , executing step S304, performing ion implantation on the second end of the transistor column to form the drain having a fifth preset thickness in the second direction.

[0132] Figure 3L and Figure 3M The schematic diagram of the structure of forming the drain electrode provided in the embodiment of the present application is that ion implantation is performed on the second end 311' of the transistor column, thereby forming the drain electrode 311 having a fifth preset thickness I in the Z-axis direction; wherein, Figure 3N As shown, the thickness J of the drain 311 is less than the thickness I of the step sidewall; Figure 3M As shown, the thickness J of the drain 311 is equal to the thickness I of the step sidewall.

[0133] In the embodiment of the present application, the transistor finally formed is a T-type double-channel transistor as a whole, that is, the source, drain and double-channel region of the transistor together form a T-type structure, wherein the double-channel region can be a vertical double-channel region (such as Figure 3M As shown), it can also be a double channel region with a T-shaped structure (as shown Figure 3L As shown). When the dual channel region is a vertical dual channel region, the source (or drain) located on one side of the dual channel region has a T-type structure; when the dual channel region is a T-type structure, the source (or drain) located on one side of the dual channel region has a planar structure. Of course, the dual channel region can also be understood as a channel region formed by merging two single channel regions, that is, two single channel regions are connected to form the dual channel region, wherein each single channel region corresponds to a gate.

[0134] In some embodiments, the double channel region of the T-type double channel transistor provided in the embodiments of the present application is parallel to the Z-axis direction, and the cross-sectional shapes of the source, drain and channel (C) include any one of the following: rectangle (square), semicircle, triangle or any polygon.

[0135] In some embodiments, the T-shaped double channel in the transistor is in a vertical direction, and the horizontal cross-section of the transistor can be a rectangle (square), semicircle, triangle, and polygon. The source and drain in the transistor are at the upper and lower ends of the transistor, so the source and drain can be interchangeable, and the source and drain can be processed on the two sides of the same wafer, so the shapes of the source and drain can be different. Due to process requirements, the horizontal cross-section of one end of the source and drain can be a rectangle (square) with two parallel sides, a cut circle, and a polygon, and the horizontal cross-section of the other end of the source and drain can be any shape.

[0136] Figure 3N and 3RA cross-sectional view of a T-type double-channel transistor along a third direction provided in an embodiment of the present application, as shown in 3N, the cross-sectional shape of the source, drain and channel of the T-type double-channel transistor may be a rectangle (square); as shown in 3O, the cross-sectional shape of the source, drain and channel of the T-type double-channel transistor may be a semicircle; as shown in Figure 3P As shown, the cross-sectional shapes of the source, drain and channel of the T-type double channel transistor can be polygonal; Figure 3Q As shown, the cross-sectional shapes of the source, drain and channel of the T-type double channel transistor can be polygonal; Figure 3R As shown, the cross-sectional shapes of the source, drain and channel of the T-type double channel transistor may be cut circles.

[0137] In the embodiment of the present application, the positions of the source and the drain can be interchanged, and the shapes of the source and the drain of the T-type double-channel transistor formed in the embodiment of the present application can be the same or different.

[0138] The T-type double-channel transistor formed by the T-type double-channel transistor manufacturing method provided by the embodiment of the present application has a source and a drain respectively located at the first end and the second end of the channel region in the second direction, and the second direction is the thickness direction of the wafer forming the channel region. In this way, the area of ​​the transistor is greatly reduced.

[0139] In some embodiments, when the T-type double-channel transistor provided in the embodiments of the present application is applied to a memory, since the drain and source of the T-type double-channel transistor are located on different surfaces of a wafer, the different structures connected to the source and drain in the memory can be designed respectively on the two surfaces of the wafer, thereby simplifying the circuit layout inside the memory and reducing the process difficulty of memory manufacturing.

[0140] The present application provides a semiconductor device. Figure 4A An optional structural diagram of a semiconductor device provided in an embodiment of the present application is shown in FIG. Figure 4B A top view of a semiconductor device along a second direction provided in an embodiment of the present application, such as Figure 4A and 4B As shown, the semiconductor device 40 includes: at least one memory cell, a word line 402 ( Figure 4A not shown) and the bit line 403.

[0141] Each of the memory cells includes at least one T-type double-channel transistor 401 , and the T-type double-channel transistor 401 at least includes a double gate G, a source S, and a drain D.

[0142] The T-type double-channel transistor 401 also includes a double-channel region, and the source of each of the T-type double-channel transistors is located at the first end of the double-channel region; the drain of each of the T-type double-channel transistors is located at the second end of the double-channel region; wherein the first end and the second end are two opposite ends of the double-channel region in the second direction, and the second direction is the thickness direction of the wafer forming the double-channel region. That is, the T-type double-channel transistor 401 in the embodiment of the present application has a T-type double channel or a vertical double channel, and the source and drain of the T-type double-channel transistor 401 are respectively located at the two ends of the double-channel region.

[0143] The bit line 403 is connected to the source S or the drain D of the T-type double-channel transistor 401 , and the bit line is used to perform a read or write operation on the memory cell when the T-type double-channel transistor is turned on.

[0144] In the embodiment of the present application, since the T-type double-channel transistor in the embodiment of the present application is a double-gate structure, the word line can be connected to the connection part of the double gate, such as Figure 4B As shown, the dual gate G( Figure 4B The word line 402 is connected to the connection part G-1, and the word line is used to provide a word line voltage, and the T-type double channel transistor 401 is controlled to be turned on or off by the word line voltage.

[0145] In some embodiments, when the source S of the T-type double channel transistor 401 is connected to the bit line 403, the drain of the T-type double channel transistor is grounded; when the drain of the T-type double channel transistor 401 is connected to the bit line 403, the source of the T-type double channel transistor is grounded.

[0146] The semiconductor device provided in the embodiments of the present application includes various types of memories, such as NAND flash memory (Flash), Nor Flash, DRAM, static random access memory (SRAM) and phase-change memory (PCM).

[0147] In some embodiments, when the semiconductor device is a DRAM, the storage unit further includes: a storage capacitor.

[0148] like Figure 4C As shown, Figure 4CThis is an optional structural diagram of a DRAM storage unit provided in an embodiment of the present application. It can be seen that in the DRAM storage unit 40', one end of the storage capacitor 404 is connected to the drain or source of the T-type double-channel transistor 401, and the other end of the storage capacitor 404 is grounded. The storage capacitor 404 is used to store data written into the memory unit. Here, the word line is connected to the connection part of the double gate of the T-type double-channel transistor ( Figure 4C not shown).

[0149] In some embodiments, when the semiconductor device is a PCM, the storage unit further includes: an adjustable resistor.

[0150] like Figure 4D As shown, Figure 4D This is an optional structural diagram of a PCM storage unit provided in an embodiment of the present application. It can be seen that in the PCM storage unit 40", the adjustable resistor 405 is connected between the bit line 403 and the source of the T-type double channel transistor 401, or the adjustable resistor 405 is connected between the bit line 403 and the drain of the T-type double channel transistor 401, and the adjustable resistor 405 is used to adjust the state of the data stored in the memory cell through the bit line voltage provided by the bit line. Here, the word line is connected to the connection part of the double gate of the T-type double channel transistor ( Figure 4D not shown).

[0151] In some embodiments, when the semiconductor device includes a plurality of the memory cells, the semiconductor device is NAND Flash or Nor Flash. When the plurality of the memory cells are connected in parallel, the semiconductor device is NorFlash; when the plurality of the memory cells are connected in series, the semiconductor device is NAND Flash.

[0152] In the embodiments of the present application, only some common semiconductor devices are listed by way of example, and the protection scope of the present application is not limited thereto. Any semiconductor device including the T-type double-channel transistor provided in the embodiments of the present application belongs to the protection scope of the present application.

[0153] In the embodiment of the present application, by designing the structure of the transistor of the semiconductor device as a new structure with a vertical channel, the area of ​​the storage unit is reduced and the storage density of the storage unit is improved. At the same time, the source and drain of the T-type double-channel transistor in the embodiment of the present application are located at the upper and lower ends of the vertical channel region. In this way, during the formation process of the semiconductor device, the bit line or other structure can be respectively arranged on the vertical two sides of the channel region. For example, for DRAM, the bit line and capacitor of the DRAM storage unit can be respectively arranged on the two sides of the same wafer. In this way, the circuit arrangement of the word line, bit line and capacitor can be simplified, and the difficulty of the manufacturing process of the semiconductor device can be reduced.

[0154] The present application provides a method for forming a semiconductor device. Figure 5 An optional structural diagram of a method for forming a semiconductor device provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the method comprises the following steps:

[0155] Step S501: forming at least one memory cell, wherein each of the memory cells at least comprises: a T-type double-channel transistor.

[0156] Step S502: forming a word line, wherein the word line is connected to the gate of the T-type double-channel transistor, the word line is used to provide a word line voltage, and the T-type double-channel transistor is controlled to be turned on or off by the word line voltage.

[0157] Step S503: forming a bit line, wherein the bit line is connected to the source or drain of the T-type double channel transistor, and the bit line is used to perform a read or write operation on the memory cell when the T-type double channel transistor is turned on.

[0158] In some embodiments, the T-type double channel transistor in the memory cell is formed by the following steps:

[0159] Step S5010, remove a certain thickness of silicon from a partial area of ​​the first surface of the first wafer through an etching process (corresponding to the first preset thickness in the above embodiment), forming a grid-shaped groove with a silicon column in the middle (corresponding to the grid-shaped etched groove in the above embodiment), fill the groove with silicon dioxide (corresponding to the insulating layer in the above embodiment), and then perform chemical mechanical polishing to expose the surface of the silicon column.

[0160] Step S5011: remove silicon of a certain thickness in a partial area of ​​the first surface of the first wafer by an etching process to form a trench structure (corresponding to the first etched trench in the above embodiment).

[0161] Step S5012: forming silicon nitride in the trench to serve as a side spacer structure (corresponding to the insulating layer in the above embodiment).

[0162] Step S5013, remove a certain thickness of silicon (corresponding to the silicon pillar in the above embodiment) and silicon nitride (corresponding to the insulating layer in the above embodiment) in a partial area of ​​the first surface through an etching process to form a double trench structure (corresponding to the etched trench in the above embodiment), and the depth of the double trench is shallower than that of trench one.

[0163] Step S5014, forming silicon oxide as a gate oxide layer (corresponding to the initial gate oxide layer with a step structure in the above embodiment) on the sidewall and bottom of the trench (corresponding to the first step sidewall and the second step sidewall in the above embodiment) by in-situ growth.

[0164] Step S5015, filling the trench with polysilicon (corresponding to forming a polysilicon layer in the above embodiment), and removing the top polysilicon to a certain depth by etching, and then removing the exposed silicon oxide on the top (corresponding to step S2023 in the above embodiment).

[0165] Step S5016, forming silicon nitride on the top of the second trench and grinding it flat until the silicon surface is exposed to serve as the top isolation structure (corresponding to the formation of the isolation layer in the above embodiment);

[0166] Step S5017 , forming a source terminal in the transistor region (corresponding to the first end of the transistor column in the above embodiment) reserved in step S5011 by ion implantation.

[0167] Step S5018, forming subsequent corresponding structures on the first side of the first wafer through various processes; then bonding the first wafer to the second wafer, and finally thinning the silicon on the back side of the first wafer to ensure that a certain thickness of silicon remains in the groove area until the second side of the first wafer (corresponding to the second end of the transistor column in the above embodiment) is exposed.

[0168] Here, the subsequent corresponding structures include: forming a bit line, forming a resistor or forming a capacitor, etc. Various logic circuits and sensors are arranged in the second wafer, and the second wafer and the first wafer together form a memory.

[0169] In some embodiments, the wafer bonding process is implemented before the back side silicon thinning process, and the second wafer provides support for the first wafer during the thinning process to prevent the first wafer from being damaged during the thinning process.

[0170] Step S5019, forming a drain on the second surface of the first wafer by ion implantation at a position opposite to the source in step S5011 (corresponding to the second end of the transistor column), and finally forming subsequent corresponding structures on the second surface of the first wafer.

[0171] Here, the subsequent corresponding structures include: forming a bit line, forming a resistor, or forming a capacitor and the like.

[0172] In the embodiment of the present application, word lines and bit lines are realized by forming metal lines at preset word line positions and preset bit line positions. The metal lines include but are not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.

[0173] In the embodiment of the present application, by designing the structure of the transistor of the semiconductor device as a new transistor structure with a vertical channel, the area of ​​the memory cell is reduced and the storage density of the memory cell is improved. At the same time, the source and drain of the T-type double-channel transistor in the embodiment of the present application are located at the upper and lower ends of the vertical channel region. In this way, during the formation of the semiconductor device, the bit line or other structure can be respectively arranged on the vertical two sides of the double-channel region. For example, for DRAM, the bit line and capacitor of the DRAM memory cell can be respectively arranged on the two sides of the same wafer. In this way, the circuit arrangement of the word line, bit line and capacitor can be simplified, and the difficulty of the manufacturing process of the semiconductor device can be reduced.

[0174] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0175] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0176] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0177] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a T-type double-channel transistor, characterized in that: The method comprises: A wafer is provided, wherein the wafer has a plurality of transistor forming regions, each of the transistor forming regions has a transistor column, and each of the transistor columns has a first step sidewall and a second step sidewall that are relatively exposed in a first direction; Sequentially forming a gate oxide layer and a gate having a step structure on the first step sidewall and the second step sidewall respectively; forming a source electrode at a first end of the transistor column; A drain is formed at the second end of the transistor column, wherein the first end and the second end are two opposite ends of the transistor column in a second direction, the second direction is the thickness direction of the wafer, and the second direction is perpendicular to the first direction; the transistor column between the source and the drain constitutes a double channel region of the T-type double channel transistor, and the double channel region has a relatively exposed step sidewall in the first direction; An isolation layer exposing the transistor column is formed on one side of the gate along the second direction; wherein the sum of the thicknesses of the isolation layer, the gate and the first step sidewall in the second direction is equal to the thickness of the transistor column in the second direction.

2. The method according to claim 1, characterized in that The transistor forming region is formed by: Along the second direction, taking the first surface of the wafer as the etching starting point, the wafer is partially etched to form a grid-shaped etching groove composed of a plurality of silicon pillars; wherein each of the silicon pillars has a first preset thickness, and the first preset thickness is less than the initial thickness of the wafer; the first surface of the wafer is any surface of the wafer along the second direction; Depositing insulating material in the grid-shaped etched grooves to form an insulating layer surrounding each of the silicon pillars; The silicon column and the insulating layer are etched to form a transistor column having the first step sidewall and the second step sidewall, and an etched groove located on the first step sidewall and the second step sidewall, so as to obtain the transistor forming region.

3. The method according to claim 2, characterized in that The etching of the silicon pillar and the insulating layer to form a transistor pillar having the first step sidewall and the second step sidewall, and an etching groove located on the first step sidewall and the second step sidewall, comprises: Partially etching the silicon pillar and both sides of the insulating layer along the third direction to remove the silicon pillar having a first preset thickness in the first direction and a second preset thickness in the second direction; and Removing the insulating layer having the first preset thickness in the first direction and the third preset thickness in the second direction, forming a transistor column having a step sidewall having a fourth preset thickness in the second direction, and an etched groove adjacent to the first step sidewall and the second step sidewall; Among them, the first preset thickness is less than half of the initial thickness of the silicon column in the first direction; the second preset thickness is less than the third preset thickness, and the sum of the second preset thickness and the fourth preset thickness is equal to the third preset thickness.

4. The method according to claim 3, characterized in that The step of sequentially forming a gate oxide layer and a gate having a step structure on the first step sidewall and the second step sidewall, respectively, comprises: Forming an initial gate oxide layer having the step structure on the first step sidewall and the second step sidewall of the transistor column respectively by in-situ oxidation; Depositing polysilicon material in each of the etched grooves to form a polysilicon layer; In the second direction, each of the initial gate oxide layers with a step structure and each of the polysilicon layers are etched simultaneously to remove a portion of the thickness of the initial gate oxide layer with a step structure and the polysilicon layer in the second direction to form the gate oxide layer with a step structure and the gate.

5. The method according to claim 4, characterized in that After forming the gate oxide layer and the gate, the method further comprises: The insulating material is deposited in each of the etched grooves to form the isolation layer.

6. The method according to claim 2, characterized in that Before forming the drain, the method further includes: Starting from the second side of the wafer, the wafer is thinned until the second end of the transistor column is exposed; wherein the second side of the wafer is a side opposite to the first side of the wafer.

7. The method according to claim 3, characterized in that The drain is formed at the second end of the transistor column, comprising: Ion implantation is performed on the second end of the transistor column to form the drain electrode having a fifth preset thickness in the second direction; wherein the fifth preset thickness is less than the fourth preset thickness.

8. A T-type double-channel transistor, characterized in that: The T-type double-channel transistor comprises: Double channel area; A source electrode, located at a first end of the double channel region; a drain electrode located at the second end of the dual channel region, wherein the first end and the second end are two opposite ends of the dual channel region in a second direction, and the second direction is a thickness direction of a wafer forming the dual channel region; the source electrode, the drain electrode and the dual channel region form a T-shaped structure; the dual channel region has a relatively exposed step sidewall in a first direction perpendicular to the second direction; and dual gate electrodes located at both sides of the dual channel region, and each of the gate electrodes corresponds to the dual channel region; A gate oxide layer having a step structure, located between the dual channel region and each of the gates; An isolation layer is located on one side of the dual gate along the second direction and exposes the dual channel region; wherein the sum of the thicknesses of the isolation layer, the gate and the step sidewalls of the dual channel region in the second direction is equal to the thickness of the T-type dual channel transistor in the second direction.

9. A method for forming a semiconductor device, characterized in that: The method comprises: At least one memory cell is formed, wherein each of the memory cells at least comprises: a T-type double-channel transistor; the T-type double-channel transistor comprises: a gate, a source and a drain; the T-type double-channel transistor is manufactured by the manufacturing method of the T-type double-channel transistor provided by any one of claims 1 to 7 above; forming a word line, wherein the word line is connected to the gate of the T-type double-channel transistor, the word line is used to provide a word line voltage, and the T-type double-channel transistor is controlled to be turned on or off by the word line voltage; A bit line is formed, wherein the bit line is connected to a source or a drain of the T-type double channel transistor, and the bit line is used to perform a read or write operation on the memory cell when the T-type double channel transistor is turned on.

10. A semiconductor device, characterized in that: include: At least one memory cell, a word line and a bit line, each of the memory cells at least comprising: a T-type double-channel transistor as claimed in claim 8; the T-type double-channel transistor at least comprising: a gate, a source and a drain; The word line is connected to the gate of the T-type double-channel transistor, and the word line is used to provide a word line voltage, and the T-type double-channel transistor is controlled to be turned on or off by the word line voltage; The bit line is connected to a source or a drain of the T-type double channel transistor, and the bit line is used to perform a read or write operation on the memory cell when the T-type double channel transistor is turned on.

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