Semiconductor structure and method for forming the same
By forming grooves with varying diameters and filling them with an air gap, the 'hammering effect' in semiconductor structures is mitigated, improving yield and reliability through reduced interference between active areas.
Patent Information
- Application Number
- CN202111067348.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-09-13
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2041-09-13
AI Technical Summary
Semiconductor structures, such as DRAM, suffer from the 'hammering effect' causing noise and interference between adjacent active areas, leading to charge loss and data errors, which affects yield and performance reliability.
Forming grooves with varying diameters and filling them with an air gap to isolate adjacent active areas, utilizing the lower dielectric constant of air to reduce interference.
Reduces interference between adjacent active areas, alleviating the hammering effect and enhancing the yield and performance reliability of semiconductor structures.
Smart Images
Figure CN113871342B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It is composed of multiple storage cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.
[0003] In semiconductor structures such as DRAM, each active area overlaps with two word lines (i.e., two word lines pass through the same active area). When one word line is activated and repeatedly refreshed, the following two effects will occur: on the one hand, noise or interference will be generated on the other word line passing through the same active area; on the other hand, before the active area adjacent to the activated word line is activated or refreshed, if the refresh frequency of the activated word line is too high, the active area adjacent to the activated word line will become fragile, resulting in charge loss or leakage problems. The above two effects will cause data errors in one or more active areas adjacent to the activated word line, resulting in the so-called row hammer effect.
[0004] Therefore, how to alleviate the hammering effect, reduce the mutual interference between adjacent active areas, and improve the yield and performance reliability of the semiconductor structure is a technical problem that needs to be solved urgently. Summary of the invention
[0005] The present invention provides a semiconductor structure and a method for forming the same, which are used to solve the problem that the semiconductor structure in the prior art is prone to produce a hammering effect, so as to reduce mutual interference between adjacent active areas and improve the yield and performance reliability of the semiconductor structure.
[0006] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising the following steps:
[0007] providing a substrate;
[0008] Etching the substrate to form grooves and active areas located between adjacent grooves, wherein the grooves include a first groove and a second groove located below the first groove and connected to the first groove, and the inner diameter of the first groove is greater than the inner diameter of the second groove;
[0009] The groove is filled to form a filling layer with an air gap in the groove.
[0010] Optionally, the specific steps of forming the grooves and the active area between adjacent grooves include:
[0011] forming a mask layer covering the substrate, wherein the mask layer has an opening exposing the substrate;
[0012] Etching the substrate along the opening to form first grooves and first sub-active regions located between adjacent first grooves;
[0013] The substrate is continuously etched along the first groove to form a second groove connected to the first groove and a second sub-active region located between adjacent second grooves below the first groove, wherein an inner diameter of the first groove is larger than an inner diameter of the second groove, and a width of the first sub-active region is smaller than a width of the second sub-active region.
[0014] Optionally, the depth of the first groove is 20% to 30% of the depth of the groove.
[0015] Optionally, before continuing to etch the substrate along the first groove, the method further includes the following steps:
[0016] A sidewall protection layer is formed to cover the sidewall of the first groove.
[0017] Optionally, the thickness of the sidewall protection layer is 1 / 5 to 1 / 4 of the width of the first sub-active region.
[0018] Optionally, after continuing to etch the substrate along the first groove, the method further includes the following steps:
[0019] The sidewall protection layer is removed.
[0020] Optionally, before filling the groove, the following steps are also included:
[0021] An adjustment layer is formed to cover the sidewall of the groove.
[0022] Optionally, the specific step of forming the adjustment layer covering the sidewall of the groove includes:
[0023] An atomic layer deposition process is used to form an adjustment layer covering the sidewall of the groove.
[0024] Optionally, the specific steps of forming a filling layer having an air gap in the groove include:
[0025] A filling material is deposited in the groove by a low-pressure chemical vapor deposition process to form the filling layer covering the surface of the adjustment layer and having an air gap.
[0026] Optionally, the material of the adjustment layer is the same as that of the filling layer.
[0027] Optionally, a top surface of the air gap is lower than a bottom surface of the first groove.
[0028] In order to solve the above problem, the present invention further provides a semiconductor structure, comprising:
[0029] substrate;
[0030] A groove located in the substrate, the groove comprising a first groove and a second groove located below the first groove and connected to the first groove, and the inner diameter of the first groove is greater than the inner diameter of the second groove;
[0031] A filling layer is located in the groove, and an air gap is provided in the filling layer;
[0032] The active area is located between adjacent grooves.
[0033] Optionally, the depth of the first groove is 20% to 30% of the depth of the groove.
[0034] Optionally, a top surface of the air gap is lower than a bottom surface of the first groove.
[0035] Optionally, the active area includes:
[0036] A first sub-active region, located between adjacent first grooves;
[0037] The second sub-active region is located between adjacent second grooves, the top surface of the second sub-active region is in contact with the bottom surface of the first sub-active region, and the width of the first sub-active region is smaller than that of the second sub-active region.
[0038] Optionally, also include:
[0039] The word line is located in the first sub-active region.
[0040] Optionally, a bottom surface of the word line is flush with a bottom surface of the first sub-active region; or
[0041] A bottom surface of the word line is higher than a bottom surface of the first sub-active region.
[0042] Optionally, also include:
[0043] The adjustment layer covers the side wall of the groove, and the filling layer covers the surface of the adjustment layer.
[0044] Optionally, the material of the adjustment layer is the same as that of the filling layer.
[0045] The semiconductor structure and the method for forming the same provided by the present invention form a groove which is wide at the top and narrow at the bottom between adjacent active areas, and form a filling layer with an air gap in the groove, and utilize the characteristic of air having a lower dielectric constant to isolate the adjacent active areas, thereby reducing the interference between the adjacent active areas during the operation of the semiconductor structure, alleviating the influence of the hammering effect, and improving the yield and performance reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] Attached Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention;
[0047] Attached Figure 2A-2N It is a schematic diagram of the main process structure in the process of forming a semiconductor structure in a specific embodiment of the present invention;
[0048] Attached Figure 3 It is a cross-sectional schematic diagram of a semiconductor structure provided by a specific embodiment of the present invention. DETAILED DESCRIPTION
[0049] The specific implementation manner of the semiconductor structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0050] This specific embodiment provides a method for forming a semiconductor structure. Figure 2A-2N FIG. 1 is a schematic diagram of the main process structure in the process of forming a semiconductor structure in a specific embodiment of the present invention. Figure 1 , Figure 2A-2N As shown, the method for forming a semiconductor structure provided in this specific embodiment includes the following steps:
[0051] Step S11, providing a substrate 20, such as Figure 2A and Figure 2B As shown, Figure 2B yes Figure 2A Cross-section along the AB direction.
[0052] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate 20 as a silicon substrate as an example. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI.
[0053] Step S12, etching the substrate 20 to form grooves and active areas between adjacent grooves, wherein the grooves include a first groove 22 and a second groove 26 located below the first groove 22 and connected to the first groove 22, and the inner diameter R1 of the first groove 22 is greater than the inner diameter R2 of the second groove 26. Fig.2I and Figure 2J As shown, Figure 2J yes Fig.2I Schematic diagram of the cross section along the AB direction.
[0054] Optionally, the specific steps of forming the grooves and the active area between adjacent grooves include:
[0055] A mask layer 21 covering the substrate 20 is formed, and the mask layer 21 has an opening 211 exposing the substrate 20. Figure 2A and Figure 2B As shown;
[0056] The substrate 20 is etched along the opening 211 to form first grooves 22 and first sub-active regions 23 located between adjacent first grooves 22. Figure 2C and Figure 2D As shown, Figure 2D yes Figure 2C Schematic diagram of the cross section along the AB direction;
[0057] The substrate 20 is further etched along the first groove 22 to form a second groove 26 communicating with the first groove 22 and a second sub-active region 25 located between adjacent second grooves 26. The inner diameter R1 of the first groove 22 is greater than the inner diameter R2 of the second groove 26. The width of the first sub-active region 23 is less than the width of the second sub-active region 25. Fig.2I and Figure 2J shown.
[0058] Specifically, a material such as polysilicon can be deposited on the surface of the substrate 20 by chemical vapor deposition, physical vapor deposition or atomic layer deposition to form the mask layer 21, and a plurality of openings 211 exposing the substrate 20 can be formed in the mask layer 21 by patterning the mask layer 21. Then, the substrate 20 is etched along the openings 211 to a preset depth by dry etching to form the first grooves 22. A first sub-active region 23 is formed between two adjacent first grooves 22. In the process of etching the substrate 20, SF 6 CF 4 , Cl 2 , CHF 3 , O 2 , Ar or a mixture of two or more gases is used as etching gas.
[0059] Optionally, the depth H1 of the first groove 22 is 20% to 30% of the depth of the groove.
[0060] The depth of the groove is the sum of the depth H1 of the first groove 22 and the depth H2 of the second groove 26 to be formed subsequently. The depth H1 of the first groove 22 may be the same as the depth of the buried word line to be formed subsequently.
[0061] Optionally, before continuing to etch the substrate 20 along the first groove 22, the following steps are further included:
[0062] A sidewall protection layer 24 is formed to cover the sidewall of the first groove 22. Figure 2E and Figure 2F As shown, Figure 2F yes Figure 2E Schematic diagram of the cross section along the AB direction.
[0063] Optionally, the thickness of the sidewall protection layer 24 is 1 / 5 to 1 / 4 of the width W of the first sub-active region 23 .
[0064] Specifically, after forming the first groove 22 and the first sub-active region 23, an atomic layer deposition process may be used to form NH 3 or N 2 and H 2 As the reaction gas, silicon nitride is deposited on the inner wall of the first groove 22, and the silicon nitride on the bottom of the first groove 22 is removed by a vertical downward etching process, thereby forming the sidewall protection layer 24 covering only the sidewall of the first groove 22. In the process of removing the silicon nitride on the bottom of the first groove 22 by the vertical downward etching process, SF 6 CF 4 , Cl 2 , CHF 3 , O 2 , Ar or a mixture of two or more gases as etching gas. The thickness of the sidewall protection layer 24 should not be too large, otherwise it will affect the characteristic size of the second groove 26 formed by subsequent etching; the thickness of the sidewall protection layer 24 should not be too small, otherwise it will not be able to effectively protect the sidewall of the first groove 22 in the subsequent process and affect the formation of the subsequent air gap. Based on this, in this specific embodiment, the thickness of the sidewall protection layer 24 is 1 / 5 to 1 / 4 of the width W of the first sub-active region 23.
[0065] Optionally, after continuing to etch the substrate 20 along the first groove 22, the following steps are further included:
[0066] Remove the sidewall protection layer 24, such as Fig.2I and Figure 2J shown.
[0067] Specifically, after forming the sidewall protection layer 24, the substrate 20 is further etched downward along the first groove 22 to form the second groove 26 communicating with the first groove 22 below the first groove 22. Figure 2G and Figure 2H As shown, Figure 2H yes Figure 2G Schematic diagram of the cross section along the AB direction. 3 PO 4 A mixed solution of 200 μm and water is used as an etching solution, and a wet etching process is used to remove the sidewall protection layer 24. After removing the mask layer 21, the following is obtained: Fig.2I and Figure 2J As shown. In the process of wet etching to remove the sidewall protection layer 24, the natural oxide layer on the inner wall of the second groove 26 can also be removed. Since the second groove 26 is formed by etching downward along the first groove 22 whose sidewall is covered with the sidewall protection layer 24, after removing the sidewall protection layer 24, the inner diameter R2 of the second groove 26 obtained is smaller than the inner diameter R1 of the first groove 22, and the difference between the inner diameter R1 of the first groove 22 and the inner diameter R2 of the second groove 26 is the thickness of the sidewall protection layer 24. Correspondingly, the width of the first sub-active area 23 is smaller than the width of the second sub-active area 25 connected to it and located therebelow. Therefore, there is a step at the junction of the first sub-active area 23 and the second sub-active area 25 (that is, the junction of the first groove 22 and the second groove 26), as shown in FIG. Figure 2J shown.
[0068] Step S13, filling the groove to form a filling layer 28 with an air gap 281 in the groove. Figure 2M and Figure 2N As shown, Figure 2N yes Figure 2M Schematic diagram of the cross section along the AB direction.
[0069] Optionally, before filling the groove, the following steps are also included:
[0070] An adjustment layer 27 is formed to cover the sidewall of the groove. Figure 2K and Figure 2L As shown, Figure 2L yes Figure 2K Schematic diagram of the cross section along the AB direction.
[0071] Optionally, the specific steps of forming the adjustment layer 27 covering the sidewall of the groove include:
[0072] An atomic layer deposition process is used to form an adjustment layer 27 covering the sidewall of the groove.
[0073] The material of the adjustment layer 27 is an insulating material. Figure 2J After the structure shown, an atomic layer deposition process can be used to deposit LTO520 (aminosilane gas) / O 2 or N zero / O 2 Silicon dioxide is deposited as a reaction gas on the inner wall of the groove (including the first groove 22 and the second groove 26) and the top surface of the substrate 20 to form the adjustment layer 27. Afterwards, the adjustment layer 27 on the top surface of the substrate 20 and the bottom surface of the second groove 26 is removed, so that the remaining adjustment layer 27 only covers the side wall of the first groove 22, the side wall of the second groove 26, and the surface of the step at the junction of the first groove 22 and the second groove 26. In this specific embodiment, the adjustment layer 27 is formed before the filling layer 28 is formed, and the thickness of the adjustment layer 27 is used to adjust the size of the air gap 281 in the filling layer 28 finally formed. The size of the air gap 281 includes the height of the air gap 281 and / or the width of the air gap 281 (i.e., the thickness of the air gap 281). For example, the greater the thickness of the adjustment layer 27, the smaller the size of the formed air gap 281.
[0074] Optionally, the specific steps of forming the filling layer 28 having the air gap 281 in the groove include:
[0075] A filling material is deposited in the groove by a low pressure chemical vapor deposition (LPCVD) process to form the filling layer 28 covering the surface of the adjustment layer 27 and having an air gap 281 .
[0076] Specifically, an insulating material such as silicon dioxide is deposited in the groove by a low-pressure chemical vapor deposition process. Since the groove is wide at the top and narrow at the bottom (i.e., the active area is narrow at the top and wide at the bottom), the rate of silicon dioxide deposition by the low-pressure chemical vapor deposition process is relatively fast, and the low-pressure chemical vapor deposition process itself will cause a sealing effect due to the different coverage of the step area, i.e., the first groove 22 is filled first before the second groove 26 is filled and the top opening of the first groove 22 is closed, resulting in the formation of the air gap 281 in the filling layer 28 in the second groove 26. The formation of the air gap 281 can effectively avoid electrical interference between adjacent active areas and reduce the hammering effect.
[0077] Taking the filling layer 28 as an example, the material of silicon dioxide can be LTO520 / O 2 As a reaction gas, the reaction temperature is 600° C. to 700° C., and the gas pressure during the reaction is 0.1 Torr to 1 Torr.
[0078] In order to simplify the process steps and reduce the process cost, optionally, the material of the adjustment layer 27 is the same as the material of the filling layer 28. For example, the material of the adjustment layer 27 and the material of the filling layer 28 are both silicon dioxide.
[0079] Optionally, a top surface of the air gap 281 is lower than a bottom surface of the first groove 22 .
[0080] Specifically, due to the limitation of the deposition characteristics of the low pressure chemical vapor deposition process itself, the top surface of the air gap 281 is lower than the bottom surface of the first groove 22 , that is, the air gap 281 is only located in the second groove 26 .
[0081] In addition, this specific embodiment also provides a semiconductor structure, Figure 3 Schematic diagram of a cross-sectional view of a semiconductor structure provided by a specific embodiment of the present invention. The semiconductor structure provided by this specific embodiment can be used as follows Figure 1 , Figure 2A-2N The semiconductor structure is formed by the method of forming the semiconductor structure shown in FIG. Figure 2A-2N and Figure 3 As shown, the semiconductor structure comprises:
[0082] Substrate 20;
[0083] A groove located in the substrate 20, the groove comprising a first groove 22 and a second groove 26 located below the first groove 22 and connected to the first groove 22, and an inner diameter R1 of the first groove 22 is greater than an inner diameter R2 of the second groove 22;
[0084] A filling layer 28 is located in the groove, and an air gap 281 is formed in the filling layer 28;
[0085] The active area is located between adjacent grooves.
[0086] Optionally, the depth H1 of the first groove 22 is 20% to 30% of the depth of the groove.
[0087] Optionally, a top surface of the air gap 281 is lower than a bottom surface of the first groove 22 .
[0088] Optionally, the active area includes:
[0089] A first sub-active region 23 is located between adjacent first grooves 22;
[0090] The second sub-active region 25 is located between adjacent second grooves 26 , the top surface of the second sub-active region 25 is in contact with the bottom surface of the first sub-active region 23 , and the width of the first sub-active region 23 is smaller than that of the second sub-active region 25 .
[0091] Optionally, the semiconductor structure further includes:
[0092] The word line is located in the first sub-active region 23 .
[0093] Optionally, the bottom surface of the word line is flush with the bottom surface of the first sub-active region 23; or
[0094] The bottom surface of the word line is higher than the bottom surface of the first sub-active region 23 .
[0095] Optionally, the semiconductor structure further includes:
[0096] The adjustment layer 27 covers the sidewall of the groove, and the filling layer 28 covers the surface of the adjustment layer 27 .
[0097] Optionally, the material of the adjustment layer 27 is the same as that of the filling layer 28 .
[0098] The semiconductor structure and the method for forming the same provided in this specific embodiment form a groove that is wide at the top and narrow at the bottom between adjacent active areas, and form a filling layer with an air gap in the groove, thereby utilizing the characteristic of air having a lower dielectric constant to isolate the adjacent active areas, thereby reducing the interference between adjacent active areas during the operation of the semiconductor structure, alleviating the impact of the hammering effect, and improving the yield and performance reliability of the semiconductor structure.
[0099] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for forming a semiconductor structure, characterized in that: The steps include: providing a substrate; Etching the substrate to form grooves and active areas located between adjacent grooves, wherein the grooves include a first groove and a second groove located below the first groove and connected to the first groove, and the inner diameter of the first groove is greater than the inner diameter of the second groove; forming an adjustment layer covering the sidewall of the groove; Depositing a filling material in the groove by a low-pressure chemical vapor deposition process to form a filling layer covering the surface of the adjustment layer and having an air gap; The material of the adjustment layer is the same as that of the filling layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming the grooves and the active area between adjacent grooves include: forming a mask layer covering the substrate, wherein the mask layer has an opening exposing the substrate; Etching the substrate along the opening to form first grooves and first sub-active regions located between adjacent first grooves; The substrate is continuously etched along the first groove to form a second groove connected to the first groove and a second sub-active region located between adjacent second grooves below the first groove, wherein an inner diameter of the first groove is larger than an inner diameter of the second groove, and a width of the first sub-active region is smaller than a width of the second sub-active region.
3. The method for forming a semiconductor structure according to claim 2, wherein: The depth of the first groove is 20% to 30% of the depth of the groove.
4. The method for forming a semiconductor structure according to claim 2, wherein: Before continuing to etch the substrate along the first groove, the method further includes the following steps: A sidewall protection layer is formed to cover the sidewall of the first groove.
5. The method for forming a semiconductor structure according to claim 4, characterized in that: The thickness of the sidewall protection layer is 1 / 5 to 1 / 4 of the width of the first sub-active region.
6. The method for forming a semiconductor structure according to claim 4, characterized in that: After the substrate is continuously etched along the first groove, the following steps are further included: The sidewall protection layer is removed.
7. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming the adjustment layer covering the sidewall of the groove include: An atomic layer deposition process is used to form an adjustment layer covering the sidewall of the groove.
8. The method for forming a semiconductor structure according to claim 1, wherein: A top surface of the air gap is lower than a bottom surface of the first groove.
9. A semiconductor structure, characterized in that: include: substrate; A groove located in the substrate, the groove comprising a first groove and a second groove located below the first groove and connected to the first groove, and the inner diameter of the first groove is greater than the inner diameter of the second groove; A filling layer is located in the groove, and an air gap is provided in the filling layer; An adjustment layer covers the sidewall of the groove, and the filling layer covers the surface of the adjustment layer; An active area, located between adjacent grooves; The material of the adjustment layer is the same as that of the filling layer.
10. The semiconductor structure according to claim 9, characterized in that: The depth of the first groove is 20% to 30% of the depth of the groove.
11. The semiconductor structure according to claim 9, characterized in that: A top surface of the air gap is lower than a bottom surface of the first groove.
12. The semiconductor structure according to claim 9, characterized in that: The active region comprises: A first sub-active region, located between adjacent first grooves; The second sub-active region is located between adjacent second grooves, the top surface of the second sub-active region is in contact with the bottom surface of the first sub-active region, and the width of the first sub-active region is smaller than that of the second sub-active region.
13. The semiconductor structure according to claim 12, characterized in that: Also includes: The word line is located in the first sub-active region.
14. The semiconductor structure according to claim 13, characterized in that: The bottom surface of the word line is flush with the bottom surface of the first sub-active region; or A bottom surface of the word line is higher than a bottom surface of the first sub-active region.