A FPGA continuous integration development method and system for SSI devices

Abstract

The present invention provides an FPGA development method, the method comprising the following steps: step 100: receiving an input HDL source file and a user constraint file, performing OOC synthesis, generating a logic netlist, and encapsulating it into a DCP file; step 200: receiving the DCP file generated in step 100, calling a cross-SLR interface circuit automatic generation script to generate a cross-SLR interface circuit; step 300: performing overall layout and routing, and encapsulating the output result into a DCP file; step 400: generating a bitstream file from the DCP file generated in step 300, configuring an FPGA device, and running and real-time debugging the FPGA device. Based on the embodiments of the present invention, the difficulty of deploying large-scale logic designs in FPGA devices can be significantly reduced, so that designers do not need to manually perform cumbersome cross-SLR design iterations and local layout and routing adjustments, which is conducive to the mapping and rapid deployment of large-scale logic designs in SSI-type FPGA cloud environments and local environments.

Description

Technical Field

[0001] The present invention relates to the field of FPGA design, and in particular to an FPGA continuous integration development method and system for SSI devices. Background Art

[0002] FPGA (Field Programmable Gate Array) plays an increasingly important role in electronic information systems. With the continuous development of chip design and manufacturing, FPGA design is becoming more and more complex, and designers are increasingly demanding the amount of on-chip logic resources of FPGA devices. In recent decades, relying on Moore's Law, each new generation of chip manufacturing process can almost double the amount of logic resources. However, with the recent slowdown of Moore's Law, the release time of new process nodes has been continuously postponed. It is difficult to meet the growing needs of the industry by simply using the early FPGA design and manufacturing ideas. At the same time, in the field of chip manufacturing engineering, as the size of the chip itself increases, its yield rate will drop sharply. The increase in the difficulty of large-area wafer production has also led to a sharp increase in the cost of large single-chip FPGA chips. Due to manufacturability and cost reasons, many logic designs have to be split into multiple independent FPGAs for implementation, and the inherent IO number restrictions, PCB signal delays and signal integrity problems of board-level circuits also make it difficult to efficiently coordinate multiple FPGAs at the board level.

[0003] Stacked Silicon Interconnect (SSI) technology is a new FPGA chip architecture developed by mainstream FPGA manufacturers to break the limitations of Moore's Law and increase the amount of on-chip logic resources while taking into account the cost of chip devices. For example, Xilinx's Versal Premium series, Virtex UltraScale+, Virtex UltraScale, Kintex UltraScale, and Virtex-7 series all use SSI technology, which can provide FPGA developers with a wide range of resources and functions to fully meet various cutting-edge needs. Figure 1As shown in the figure, the stacked silicon interconnect technology allows FPGA manufacturers to combine and package multiple easy-to-manufacture FPGA dies (also known as Super Logic Regions, SLRs) into a whole based on the advantage of small chip manufacturing cost. With the help of inter-silicon interconnect technology and new chip packaging technology, multiple easy-to-manufacture FPGA dies (also known as Super Logic Regions, SLRs) are combined and packaged into a whole through microbumps and through-silicon vias, thereby providing the capacity and bandwidth of large single-chip FPGAs while improving the manufacturability of the chip as much as possible, reducing batch manufacturing costs and production time cycles, and thus meeting the growing FPGA market demand. In order to support user logic design across SLRs, the SSI type FPGA chips in the Xilinx UltraScale+ series are internally set with dedicated resources such as SLL (SuperLong Line) and Laguna (a unit in the FPGA chip dedicated to bridging different SLRs, including transceiver triggers connected to SLLs). In recent years, mainstream cloud computing service providers at home and abroad have begun to deploy SSI-type FPGA devices. For example, AWS (Amazon Web Services) has currently deployed Xilinx's UltraScale+VU9P series of FPGA devices, which contain multiple SLR areas and are SSI-type. Xilinx's latest large-scale FPGA devices basically use SSI technology. It can be foreseen that in the future FPGA cloud market, FPGA application scenarios using SSI technology will become more and more extensive.

[0004] Whether in the cloud or in local FPGA application environments, SSI technology is rapidly gaining popularity. Although the emergence of SSI technology has basically solved the problem of balancing the total amount of logic resources and chip costs, in SSI devices, the various SLR areas packaged as a whole are still relatively independent in terms of clock resources, data timing paths, etc. Therefore, when a large logic netlist is mapped to multiple SLRs, the connections across SLRs still require designers to make delicate fine-tuning to obtain the best implementation performance. However, for junior and intermediate FPGA developers, the timing constraints and layout and routing adjustment optimization design for SSI devices are still difficult to master and are prone to errors. These design thresholds have also largely limited the popularity of SSI-type devices in domestic and foreign FPGA cloud environments and local environments. Summary of the invention

[0005] In view of the above problems, according to a first aspect of the present invention, a FPGA development method is proposed, the method comprising the steps of:

[0006] Step 100: receiving input HDL source files and user constraint files, performing OOC synthesis, generating a logic netlist, and packaging it into a DCP (Design CheckPoint) file;

[0007] Step 200: receiving the DCP file generated in step 100, and calling the cross-SLR interface circuit automatic generation script to generate the cross-SLR interface circuit;

[0008] Step 300: Perform overall layout and routing, and encapsulate the output results into a DCP file;

[0009] Step 400: Generate a bitstream file from the DCP file generated in step 300, configure the FPGA device, and run and debug the FPGA device in real time.

[0010] In one embodiment of the present invention, the automatic generation of scripts across the SLR interface circuit in step 200 includes:

[0011] According to the user logic working clock frequency and the maximum clock frequency information allowed by the SLL, determine the transmission frequency multiplication factor N, where N is a positive integer;

[0012] Generate a cross-SLR interface circuit, the circuit is used to increase the SLL line frequency to N times the user logic frequency, and perform N-to-1 serial-to-parallel conversion from the SLR area input and output lines to the SLL lines;

[0013] Determine the logical connection relationship between various units across the SLR interface circuit;

[0014] Perform logical and physical routing across the SLR interface circuits.

[0015] In one embodiment of the present invention, the method further includes: feeding back the analysis report generated in steps 100 to 400 to the user.

[0016] In one embodiment of the present invention, step 400 further includes: providing a user with a measured on-chip logic waveform data report.

[0017] In one embodiment of the present invention, the generated cross-SLR interface circuit includes a clock generation unit, an SLL line, an N-phase selection controller and a selector, wherein

[0018] The clock generation unit is used to generate the frequency of the user logic and the frequency for the SLL line;

[0019] The SLL line is used to connect the SLR module;

[0020] The N phase selection controller is used to control the selector to implement serial-to-parallel conversion;

[0021] The selector is used for serial-to-parallel conversion to convert parallel signals on multiple output lines into serial signals on one SLL line, and to convert a serial signal on one SLL line into parallel signals on multiple input lines.

[0022] In one embodiment of the present invention, the generated cross-SLR interface circuit also includes multiple serially connected D flip-flops and multiple parallel connected D flip-flops, wherein the SLL line uses the serially connected D flip-flops for clock multiplication to accelerate the data transmission rate based on time division multiplexing.

[0023] In one embodiment of the present invention, it also includes:

[0024] In step 100, OOC synthesis is performed using VIVADO running in a container in a cloud environment to generate a logic netlist;

[0025] In step 200, RapidWright runs in a container in a cloud environment, receives the DCP file generated in step 100 and calls a cross-SLR interface circuit automatic generation script;

[0026] In step 300, overall layout and routing is performed using VIVADO running in a container in a cloud environment;

[0027] In step 400, VIVADO is used to run in a container in a cloud environment to generate a bitstream file from the DCP file generated in step 300.

[0028] In one embodiment of the present invention, it also includes: using a continuous integration tool to detect changes in code files in the design repository, and when a cloud platform user changes the logic design code or layout and routing constraint file of the FPGA, steps 100 to 400 including executing an automated generation script are automatically triggered.

[0029] According to a second aspect of the present invention, there is provided a computer-readable storage medium, in which one or more computer programs are stored. When the computer programs are executed, they are used to implement the FPGA development method of the present invention.

[0030] According to a third aspect of the present invention, there is provided a computing system, comprising: a storage device, and one or more processors; wherein the storage device is used to store one or more computer programs, and the computer programs are used to implement the FPGA development method of the present invention when executed by the processors.

[0031] Compared with the prior art, the FPGA continuous integration development method and system for SSI devices of the present invention provides an automated optimization solution, which significantly reduces the difficulty of deploying large-scale logic designs in FPGA devices, and enables designers to perform tedious cross-SLR design iterations and local layout and routing adjustments manually, thereby lowering the development threshold and facilitating the mapping and rapid deployment of large-scale logic designs in SSI-type FPGA cloud environments and local environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings herein are incorporated into and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0033] Figure 1 The stacked silicon interconnect technology is shown;

[0034] FIG. 2( a ) shows a flow chart of an automation script of the present invention;

[0035] Figure 2(b) shows the various input and output files of each software in each stage

[0036] Figure 3 The cross-SLR interface circuit automatic generation script execution process is shown;

[0037] Figure 4 Shown is a cross-SLR interface module circuit generated by a cross-SLR interface circuit automation generation script;

[0038] Figure 5 A schematic diagram showing integration with continuous integration tools. DETAILED DESCRIPTION

[0039] In response to the problems raised in the background technology, the inventors conducted research and proposed a FPGA continuous integration development method and system for SSI devices. The present invention is applicable to network-based cloud environments and also to local offline development environments without networks. The operation process of EDA-assisted interactive tools for FPGA underlying hardware details is scripted and automated. Figure 2(a) shows a flowchart of the automation script. In summary, it includes four stages: in the first stage, VIVADO receives HDL source files and user constraint files to synthesize various sub-modules; in the second stage, RapidWright performs wiring and calls the internal preset cross-SLR interface circuit automation generation script to generate the cross-SLR interface module circuit; in the third stage, VIVADO is started again to perform overall layout and wiring; in the fourth stage, a bitstream file is generated, the FPGA is configured, and the FPGA device is operated and debugged in real time. Figure 2(b) shows in detail the various input and output files of the EDA software in each stage. The following will describe the above four stages in detail with reference to Figure 2(b):

[0040] Phase 1

[0041] The user pushes the HDL source file and the user constraint file into the VIVADO environment for OOC (Out Of Context, context-independent, that is, each sub-module in the design hierarchy is processed separately) synthesis, and then generates a logic netlist and performs phased evaluation and analysis. According to one embodiment of the present invention, if the design file provided by the user is not synthesizable or cannot meet the constraints in the OOC synthesis stage, VIVADO will eventually give feedback to the user to assist the iterative design at this stage. If the constraints are met, the output logic netlist result of this stage is finally packaged as a DCP file and transmitted to the next stage.

[0042] According to one embodiment of the present invention, at this stage, VIVADO can run in a container in a cloud environment.

[0043] Phase II

[0044] According to one embodiment of the present invention, in the RapidWright tool environment, the logic netlist information generated after VIVADO OOC synthesis in the first stage is transferred to the DCP file entry of the RapidWright tool.

[0045] Considering that the number of SLL resources in the mainstream SSI type FPGA devices in the industry is often small, they are scarce resources in the design across SLR areas. It is necessary to save SLL resources as much as possible while ensuring performance and stability.

[0046] By extracting the post-synthesis logic netlist information of the first stage, reading the FPGA device model and the area that the user logic netlist needs to map, and then determining the required number of SLL resources based on the actual amount of logic resources in each SLR of the device.

[0047] After RapidWright is started, the internal preset cross-SLR interface circuit automatic generation script is called. Figure 3 The automatic generation script execution flow of the cross-SLR interface circuit according to an embodiment of the present invention is shown. According to the flow, it first calculates the transmission multiplication factor N of the SLL line, that is, the multiple N by which the SLL frequency can be increased, N is a positive integer, so that the number of required SLL lines becomes one-N; finally, a cross-SLR interface circuit is generated, which is used to increase the SLL line frequency by N times and complete the N-to-1 serial-to-parallel conversion of the input and output lines of the SLR area to the SLL line; then the logical connection relationship between each unit of the cross-SLR interface circuit is determined, the logic wiring is completed, and finally the physical layout and wiring mapping of the cross-SLR interface circuit is performed. The value of N needs to be determined in combination with the speed grade of the device itself, the working clock frequency of the user logic (located in the SLR area), and other information. In order to better explain the method of taking the value of N, a specific implementation case is described: for example, for an FPGA device at a certain speed grade, the maximum SLL transmission clock frequency allowed is 600MHz, and the user logic working clock frequency is 150MHz, then the required multiplication factor N=600 / 150=4. The automatically generated script determines the optimal transmission multiplication factor N based on the user logic operating clock frequency and the maximum clock frequency allowed by the SLL, where N = the maximum clock frequency allowed by the SLL / user logic operating clock frequency. If the division result is not an integer, it is rounded down so that the actual operating clock frequency on the SLL does not exceed the maximum clock frequency of the SLL.

[0048] According to a specific implementation case described above, by increasing the operating frequency on the SLL line by 4 times, each line can transmit N times the data, while the overall cross-SLR data transmission bandwidth remains unchanged, thereby reducing the number of required SLL lines to one quarter, significantly saving SLL resources.

[0049] In order to more clearly describe the design and implementation method of the embodiment, Figure 4 The schematic diagram of the structure of the cross-SLR interface module circuit of the present invention is shown. Figure 4Except for the two SLR internal logic areas (represented as SLR1 and SLR2 in the figure), all parts are cross-SLR interface module circuits. The clock generation unit generates two frequencies CLK_0 and CLK_SLR. CLK_0 is the user logic operating frequency, that is, the SLR internal frequency, which is used for SLR1 and SLR2. CLK_SLR is N times CLK_0 and is used for SLL lines. SLL lines use serial D flip-flops to enhance signals. Figure 4 S1, S2, S3, S4, S5, and S6 are serial D flip-flops, and the clock input used by the serial D flip-flops is CLK_SLR. At the edge of the SLR area, the N-to-1 conversion of the SLR area input and output lines to the SLL lines is performed using an N:1 selector controlled by an N phase selection controller. The figure shows two N:1 selectors Sel1 and Sel2, Sel1 is used for SLR1, and Sel2 is used for SLR2.

[0050] The N:1 selector is used to realize serial-to-parallel conversion, converting parallel signals on multiple output lines into serial signals on one SLL line, and also used to convert serial signals on one SLL line into parallel signals on multiple input lines. The N:1 selector selects a specific input and output line at a certain moment, which is controlled by the N phase selection controller. The working clock frequency of the N phase selection controller is CLK_SLR, which is used to provide the N:1 selector with a control signal at the selection end. The control signal controls the N:1 selector (Sel1 or Sel2) to specifically determine which line among the N lines is selected. The N:1 selector itself can be pure combinational logic, without clock frequency signal access, so its actual working frequency is the same as that of the N phase selection controller, which is CLK_SLR. The N:1 selector (Sel1 or Sel2) selects one of the N input lines (or output lines) in turn at the frequency of CLK_SLR, so the frequency of these N input lines (or output lines) is CLK_0.

[0051] The serially arranged D flip-flops (S1, S2, S3, S4, S5, S6, hereinafter referred to as serial D flip-flops) are used to improve the signal driving capability and the signal quality across SLRs, and their number is independent of N. The D flip-flops between the N:1 selector and the SLR region (SLR1 or SLR2) also have multiple D flip-flops arranged in parallel, namely P11, P12, P13, P14 and P21, P22, P23, P24 in the figure, hereinafter referred to as parallel flip-flops.

[0052] The N phase selection controller operates at the CLK_SLR clock frequency and generates a set of control signals for the N:1 selector. For example, the Se end of the selector Sel1 will select the Q end data of the P11, P12, P13, and P14 triggers in sequence at the beat of CLK_SLR, and send it to the D end of the D trigger S1 to complete the parallel-to-serial work.

[0053] The physical location of the serial D flip-flop is at the edge of the SLR (or can be regarded as the "SLR edge logic area") and is still implemented on the SLR die.

[0054] According to one embodiment of the present invention, at this stage RapidWright can run in a container in a cloud environment.

[0055] According to one embodiment of the present invention, the output result of this stage will be packaged as a DCP file and transmitted to the next stage.

[0056] Phase 3

[0057] Load and start the VIVADO environment again, perform overall layout and routing, analyze and evaluate the overall design, and generate a phased analysis report. If the overall layout and routing constraints cannot be met at this stage, the report will be fed back to the user to continue design adjustments and iterations at this stage. The output results of this stage will be packaged as a DCP file and transmitted to the next stage.

[0058] According to one embodiment of the present invention, at this stage, VIVADO can run in a container in a cloud environment.

[0059] Stage 4

[0060] VIVADO converts the DCP file generated in the third stage into a bitstream file (i.e., .bit configuration file), uses the bitstream file to configure the FPGA device, and runs and debugs the FPGA device in real time. Preferably, in this stage, the user is provided with reports such as the measured on-chip logic waveform data for further design optimization or cloud deployment in the later stage.

[0061] According to one embodiment of the present invention, this stage can be performed in a local environment or a cloud environment.

[0062] Continuous Integration (CI) is the process of automatically detecting, pulling, building, and unit testing source code changes with the help of continuous integration tools. The basic idea of ​​continuous integration is to use continuous integration tools to monitor whether there are changes in one or more remote source code repositories. When changes are pushed to the remote repository, the tool will automatically detect the changes, download a copy, build, and run any required unit tests to provide feedback to developers as soon as possible.

[0063] Preferably, according to an embodiment of the present invention, the above four stages are further integrated with a continuous integration tool (GitLab-CI is used as an example for illustration). Figure 5As shown, with the help of the GitLab-CI tool, the code file changes in the GitLab design repository will be detected through automated scripts. When the cloud platform user changes the FPGA's logic design code or layout and routing constraint files, a complete workflow (i.e. the first to fourth stages mentioned above) will be automatically triggered until a bitstream file that can be configured on the FPGA physical device is generated. At the same time, the analysis reports at each stage will also be fed back to the cloud platform user for reference.

[0064] To enable any person of ordinary skill in the art to implement or use the present disclosure, the above description is centered around the present disclosure. It is obvious to those of ordinary skill in the art that various modifications are made to the present disclosure, and the general principles defined herein may also be applied to other variations without departing from the spirit or scope of the present disclosure. In addition, unless otherwise stated, all or part of any aspect and / or embodiment may be used together with all or part of any other aspect and / or embodiment. Therefore, the present disclosure is not limited to the examples and designs described herein, but is consistent with the broadest range of principles and novel features disclosed herein.

Claims

1. A FPGA development method, the method comprising the steps of: Step 100: receiving input HDL source files and user constraint files, performing OOC synthesis, generating a logic netlist, and packaging it into a DCP file; Step 200: receiving the DCP file generated in step 100, and calling the cross-SLR interface circuit automatic generation script to generate the cross-SLR interface circuit; Step 300: Perform overall layout and routing, and encapsulate the output result into a DCP file; Step 400: Generate a bitstream file from the DCP file generated in step 300, configure the FPGA device, and run and debug the FPGA device in real time; The automatic generation of scripts across the SLR interface circuit in step 200 includes: According to the user logic working clock frequency and the maximum clock frequency information allowed by the SLL, determine the transmission frequency multiplication factor N, where N is a positive integer; Generate a cross-SLR interface circuit, the circuit is used to increase the SLL line frequency to N times the user logic frequency, and perform N-to-1 serial-to-parallel conversion from the SLR area input and output lines to the SLL lines; Determine the logical connection relationship between various units across the SLR interface circuit; Perform logical and physical routing of cross-SLR interface circuits; The generated cross-SLR interface circuit includes a clock generation unit, an SLL line, an N-phase selection controller and a selector, wherein: The clock generation unit is used to generate the frequency of the user logic and the frequency for the SLL line; The SLL line is used to connect the SLR module; The N phase selection controller is used to control the selector to implement serial-to-parallel conversion; The selector is used for serial-to-parallel conversion to convert parallel signals on multiple output lines into serial signals on one SLL line, and to convert a serial signal on one SLL line into parallel signals on multiple input lines.

2. The method according to claim 1, further comprising: The analysis report generated in steps 100 to 400 is fed back to the user.

3. The method according to claim 1, wherein: Step 400 also includes: providing a user with a measured on-chip logic waveform data report.

4. The method according to claim 1, wherein the generated cross-SLR interface circuit further comprises a plurality of serially connected D flip-flops and a plurality of parallelly connected D flip-flops, wherein the SLL line uses the serially connected D flip-flops for clock multiplication to accelerate the data transmission rate based on time division multiplexing.

5. The method according to any one of claims 1 to 4, further comprising: In step 100, OOC synthesis is performed using VIVADO running in a container in a cloud environment to generate a logic netlist; In step 200, RapidWright runs in a container in a cloud environment, receives the DCP file generated in step 100 and calls a cross-SLR interface circuit automatic generation script; In step 300, overall layout and routing is performed using VIVADO running in a container in a cloud environment; In step 400, VIVADO is used to run in a container in a cloud environment to generate a bitstream file from the DCP file generated in step 300.

6. The method according to claim 5, further comprising: Utilize continuous integration tools to detect changes in code files in the design repository. When a cloud platform user changes the logic design code or layout and routing constraint files of the FPGA, steps 100 to 400, including the execution of automated generation scripts, are automatically triggered.

7. A computer-readable storage medium, storing one or more computer programs, wherein the computer programs are used to implement the method according to any one of claims 1 to 6 when executed.

8. A computing system comprising: storage device, and one or more processors; The storage device is used to store one or more computer programs, and the computer programs are used to implement the method according to any one of claims 1 to 6 when executed by the processor.

Images