Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, comprising: forming an initial pseudo-gate structure on a substrate; forming a source-drain doping layer in the substrate on both sides of the initial pseudo-gate structure; forming an initial conductive layer on the source-drain doping layer, the initial conductive layer covering the sidewalls and top surface of the source-drain doping layer; and removing the initial pseudo-gate structure. By directly forming the initial conductive layer on the source-drain doping layer after forming the source-drain doping layer, the process steps of first forming a dielectric layer and then etching the dielectric layer are avoided, the process steps are effectively reduced, and the manufacturing cost and manufacturing cycle are reduced. In addition, since the initial conductive layer is directly formed on the source-drain doping layer, the formed initial conductive layer can cover the sidewalls and top surface of the source-drain doping layer, effectively increasing the contact area between the initial conductive layer and the source-drain doping layer, reducing the contact resistance between the initial conductive layer and the source-drain doping layer, and improving the performance of the semiconductor structure finally formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration, for example, flash memory is used as a storage device in electronic devices such as digital cameras, laptops or tablet computers. Therefore, reducing the size of flash memory cells and thereby reducing the cost of flash memory is one of the directions of technological development. For the NOR gate electrically erasable tunneling oxide flash memory, a self-aligned electrical contact process can be used to manufacture the conductive structure on the surface of the source region and the drain region, thereby meeting the demand for manufacturing a smaller size flash memory.

[0003] However, even if the conductive structure on the surface of the source region or the drain region is manufactured using a self-aligned electrical contact process, the performance of the formed semiconductor structure still needs to be improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0005] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: forming an initial dummy gate structure on a substrate, wherein the initial dummy gate structure extends along a first direction; forming a source-drain doping layer in the substrate on both sides of the initial dummy gate structure; after the source-drain doping layer, forming an initial conductive layer on the source-drain doping layer, wherein the initial conductive layer covers the side walls and top surfaces of the source-drain doping layer; after forming the initial conductive layer, removing the initial dummy gate structure.

[0006] Optionally, the initial dummy gate structure includes: a dummy gate dielectric layer, a dummy gate layer located on the dummy gate dielectric layer, and a first protection layer located on the dummy gate layer.

[0007] Optionally, after forming the initial dummy gate structure and before forming the source-drain doping layer, the method further includes: forming a sidewall on the substrate, wherein the sidewall is located on a sidewall of the initial dummy gate structure.

[0008] Optionally, after forming the initial conductive layer and before removing the initial dummy gate structure, the method further includes: forming a dielectric layer on the substrate, wherein the dielectric layer covers the initial dummy gate structure and side walls of the initial conductive layer.

[0009] Optionally, a first opening is formed between adjacent initial conductive layers, and after the first opening is formed, the method further includes: forming an initial gate structure in the first opening.

[0010] Optionally, the initial gate structure includes: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a second protection layer located on the gate layer.

[0011] Optionally, after forming the initial gate structure, it also includes: etching away part of the initial conductive layer to form a conductive layer and a first isolation opening located in the dielectric layer, the first isolation opening penetrates the conductive layer along a second direction, and the first direction is perpendicular to the second direction; forming a first isolation structure in the first isolation opening.

[0012] Optionally, after forming the initial gate structure, it also includes: etching and removing part of the initial gate structure to form a gate structure and a second isolation opening located in the dielectric layer, the second isolation opening passing through the gate structure along the second direction; forming a second isolation structure in the second isolation opening.

[0013] Optionally, after forming the gate structure and the conductive layer, the method further includes: forming a first conductive plug and a second conductive plug, wherein the first conductive plug contacts the gate structure, and the second conductive plug contacts the conductive layer.

[0014] Optionally, the gate structure includes a first region and a second region arranged along the first direction, the conductive layer is located on both sides of the first region of the gate structure, the first conductive plug contacts the first region of the gate structure, and the second conductive plug contacts the conductive layer.

[0015] Optionally, the second conductive plug is located on a portion of the top surface of the gate structure, and the second conductive plug is in contact with the sidewall spacer.

[0016] Optionally, the initial conductive layer includes: a contact layer located on the surface of the source-drain doped layer exposed, and a metal layer located on the contact layer.

[0017] Optionally, the initial conductive layer further includes: a third protective layer located on the metal layer.

[0018] Optionally, the method for forming the contact layer includes: forming an initial contact layer on the surface of the source-drain doped layer exposed; and annealing the initial contact layer to form the contact layer.

[0019] Optionally, the annealing process includes: an annealing time of 5s to 30s; and an annealing temperature of 600°C to 1000°C.

[0020] Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate; a gate structure located on the substrate, the gate structure extending along a first direction; a source-drain doped layer located in the substrate on both sides of the gate structure; and a conductive layer located on the source-drain doped layer, the conductive layer covering the side walls and top surface of the source-drain doped layer.

[0021] Optionally, the gate structure includes: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a second protection layer located on the gate layer.

[0022] Optionally, the method further includes: a first conductive plug and a second conductive plug, wherein the first conductive plug contacts the gate structure, and the second conductive plug contacts the conductive layer.

[0023] Optionally, the gate structure includes a first region and a second region arranged along the first direction, the conductive layer is located on both sides of the first region of the gate structure, the first conductive plug contacts the first region of the gate structure, and the second conductive plug contacts the conductive layer.

[0024] Optionally, the second conductive plug is located on a portion of the top surface of the gate structure, and the second conductive plug is in contact with a sidewall spacer located on a sidewall of the gate structure.

[0025] Optionally, it also includes: a dielectric layer located on the substrate, the dielectric layer covering the conductive layer and the side walls of the gate structure; a first isolation structure and a second isolation structure located in the dielectric layer, the first isolation structure contacts the side walls of the gate structure, and the second isolation structure contacts the side walls of the conductive layer.

[0026] Optionally, the conductive layer includes: a contact layer located on the surface of the source-drain doped layer exposed, and a metal layer located on the contact layer.

[0027] Optionally, the conductive layer further includes: a third protective layer located on the metal layer.

[0028] Optionally, the first conductive plug is located on a top surface of a portion of the conductive layer, and the first conductive plug is in contact with the third protective layer.

[0029] Optionally, the material of the contact layer includes nickel silicon, titanium silicon or cobalt silicon.

[0030] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0031] In the formation method of the technical solution of the present invention, after forming the source-drain doped layer and before removing the initial pseudo-gate structure, an initial conductive layer is directly formed on the source-drain doped layer, avoiding the process steps of first forming a dielectric layer and then etching the dielectric layer to form an opening, effectively reducing the process steps, reducing the manufacturing cost and the manufacturing cycle. In addition, since the initial conductive layer is directly formed on the source-drain doped layer, the formed initial conductive layer can cover the sidewall and top surface of the source-drain doped layer, effectively increasing the contact area between the initial conductive layer and the source-drain doped layer, reducing the contact resistance between the initial conductive layer and the source-drain doped layer, and thus improving the performance of the semiconductor structure finally formed.

[0032] Furthermore, the second conductive plug is located on a portion of the top surface of the gate structure, and the second conductive plug is in contact with the side wall, so that the formed second conductive plug is a self-aligned structure. In the process of forming the second conductive plug, the accuracy of the photomask opening is reduced, thereby effectively reducing the process difficulty.

[0033] Furthermore, the gate structure includes a first area and a second area arranged along the first direction, and the conductive layer is located on both sides of the first area of ​​the gate structure. By contacting the first conductive plug with the first area of ​​the gate structure and the second conductive plug with the conductive layer, the distance between the first conductive plug and the second conductive plug can be effectively reduced, thereby improving the integration of the elements of the semiconductor structure finally formed.

[0034] In the structure of the technical solution of the present invention, a conductive layer is located on the source-drain doped layer, and the conductive layer covers the side wall and top surface of the source-drain doped layer, thereby effectively increasing the contact area between the conductive layer and the source-drain doped layer, reducing the contact resistance between the conductive layer and the source-drain doped layer, and thereby improving the performance of the semiconductor structure finally formed.

[0035] Furthermore, the second conductive plug is located on a portion of the top surface of the gate structure, and the second conductive plug is in contact with the side wall, so that the formed second conductive plug is a self-aligned structure. In the process of forming the second conductive plug, the accuracy of the photomask opening is reduced, thereby effectively reducing the process difficulty.

[0036] Furthermore, the gate structure includes a first area and a second area arranged along the first direction, and the conductive layer is located on both sides of the first area of ​​the gate structure. By contacting the first conductive plug with the first area of ​​the gate structure and the second conductive plug with the conductive layer, the distance between the first conductive plug and the second conductive plug can be effectively reduced, thereby improving the integration of the elements of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 and Figure 2 It is a schematic diagram of the structure of a semiconductor structure;

[0038] Figures 3 to 15 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] As described in the background art, the performance of the formed semiconductor structure still needs to be improved.

[0040] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0041] Please refer to Figure 1 , providing a substrate 100; forming a dummy gate structure (not shown) on the substrate 100, wherein the dummy gate structure extends along a first direction; forming a source-drain doping layer 101 in the substrate 100 on both sides of the dummy gate structure; forming an etch stop layer 102 behind the source-drain doping layer 101, wherein the etch stop layer 102 covers the sidewalls and top surface of the source-drain doping layer 101; forming a dielectric layer 103 on the substrate 100, wherein the dielectric layer 103 covers the etch stop layer 102 and the sidewalls of the dummy gate structure.

[0042] Please refer to Figure 2 After forming the dielectric layer 103, the dielectric layer 103 and the etch stop layer 102 are etched until the top surface of the source-drain doped layer 101 is exposed, and an opening (not shown) is formed in the dielectric layer 103; a conductive layer 104 is formed in the opening, and the conductive layer 104 is located on the top surface of the source-drain doped layer 101.

[0043] In the above embodiment, an etch stop layer 102 and a dielectric layer 103 are first formed on the source / drain doping layer 101, and after the etch stop layer 102 and the dielectric layer 103 are formed, the dielectric layer 103 and the etch stop layer 102 are etched and removed to form the opening, and then the conductive layer 104 is formed in the opening.

[0044] However, the above process forms the dielectric layer 103 first, and then etches the dielectric layer 103 to form the opening after the dielectric layer 103 is formed, so that the process of forming the conductive layer 104 is relatively cumbersome and complicated, which increases the production cycle and production cost. In addition, when etching the dielectric layer 103, the dielectric layer 103 covered by the sidewall of the source-drain doped layer 101 is difficult to be completely etched, so that the surface of the source-drain doped layer 101 cannot be completely exposed, so that the conductive layer 104 formed subsequently can only contact the top surface and part of the sidewall surface of the source-drain doped layer 101, reducing the contact area between the conductive layer 104 and the source-drain doped layer 101, so that the contact resistance between the conductive layer 104 and the source-drain doped layer 101 increases, thereby affecting the performance of the semiconductor structure finally formed.

[0045] On this basis, the present invention provides a semiconductor structure and a method for forming the same. After forming the source-drain doped layer, an initial conductive layer is directly formed on the source-drain doped layer, thereby avoiding the subsequent steps of etching the dielectric layer and forming an etching stop layer, effectively reducing the process steps, and reducing the manufacturing cost and manufacturing cycle. In addition, the initial conductive layer formed can cover the sidewalls and top surface of the source-drain doped layer, effectively increasing the contact area between the initial conductive layer and the source-drain doped layer, reducing the contact resistance between the initial conductive layer and the source-drain doped layer, and thus improving the performance of the semiconductor structure finally formed.

[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Figures 3 to 15 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0048] Please refer to Figure 3 and Figure 4 , Figure 4 yes Figure 3 A cross-sectional view along line BB in FIG. 1 shows a substrate.

[0049] In this embodiment, the substrate includes: a base 200 and a plurality of mutually separate fins 201 located on the base 200 , wherein the fins 201 extend along a second direction X.

[0050] In this embodiment, the method for forming the base 200 and the fins 201 includes: providing an initial substrate (not shown), patterning and etching the initial substrate, and forming the base 200 and a plurality of separate fins 201 on the base 200 .

[0051] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0052] In this embodiment, the material of the fin 201 is silicon; in other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0053] Please continue to refer to Figure 4 , an isolation layer 202 is formed on the substrate, and the isolation layer 202 covers a portion of the sidewall of the fin 201 .

[0054] The method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate 200 ; and etching away a portion of the initial isolation layer to form the isolation layer 202 , wherein the top surface of the isolation layer 202 is lower than the top surface of the fin 201 .

[0055] The material of the isolation layer 202 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride. In this embodiment, the material of the isolation layer 202 is silicon oxide.

[0056] Please refer to Figure 5 and Figure 6 , Figure 6 yes Figure 5 In the cross-sectional view along line CC, an initial dummy gate structure 203 is formed on the substrate, and the initial dummy gate structure 203 extends along the first direction Y.

[0057] In this embodiment, the first direction Y is perpendicular to the second direction X, the initial dummy gate structure 203 spans across the fin 201 , and the initial dummy gate structure 203 covers a portion of the sidewall and top surface of the fin 201 .

[0058] In this embodiment, the initial dummy gate structure 203 includes: a dummy gate dielectric layer, a dummy gate layer located on the dummy gate dielectric layer, and a first protection layer located on the dummy gate layer.

[0059] In this embodiment, the material of the dummy gate dielectric layer includes a high-K dielectric material.

[0060] The material of the dummy gate layer includes polysilicon or amorphous silicon. In this embodiment, the material of the dummy gate layer 203 is polysilicon.

[0061] In this embodiment, the material of the first protective layer is silicon nitride.

[0062] Please continue to refer to Figure 5After the initial dummy gate structure 203 is formed, a sidewall spacer 204 is formed on the substrate, and the sidewall spacer 204 is located on the sidewall of the initial dummy gate structure 203 .

[0063] The material of the sidewall spacer 204 includes one or more combinations of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the sidewall spacer 204 is silicon nitride.

[0064] Please refer to Figure 7 , Figure 7 and Figure 5 In accordance with the viewing direction, source-drain doping layers 205 are formed in the substrate on both sides of the initial dummy gate structure 203.

[0065] In this embodiment, the method for forming the source-drain doped layer 205 includes: etching the fin 201 using the initial pseudo-gate structure 203 and the side wall 204 as a mask to form a source-drain opening (not shown) in the fin 201; forming an epitaxial layer (not shown) in the source-drain opening using an epitaxial growth process; and in-situ doping the epitaxial layer during the epitaxial growth process to introduce source-drain ions into the epitaxial layer to form the source-drain doped layer 205.

[0066] In this embodiment, the top or sidewall of the source / drain doping layer 205 protrudes from the surface of the fin 201 .

[0067] Please refer to Figure 8 and Fig. 9 , Fig. 9 yes Figure 8 In the cross-sectional view along line DD, after the source-drain doping layer 205 , an initial conductive layer 206 is formed on the source-drain doping layer 205 , and the initial conductive layer 206 covers the sidewalls and the top surface of the source-drain doping layer 205 .

[0068] By directly forming the initial conductive layer 206 on the source-drain doped layer 205 after forming the source-drain doped layer 205 and before removing the initial pseudo-gate structure 203, the process steps of first forming a dielectric layer and then etching the dielectric layer to form an opening are avoided, which effectively reduces the process steps, reduces the manufacturing cost and the manufacturing cycle. In addition, since the initial conductive layer 206 is directly formed on the source-drain doped layer 205, the formed initial conductive layer 206 can cover the sidewall and top surface of the source-drain doped layer 205, effectively increasing the contact area between the initial conductive layer 206 and the source-drain doped layer 205, reducing the contact resistance between the initial conductive layer 206 and the source-drain doped layer 205, and thus improving the performance of the semiconductor structure finally formed.

[0069] In this embodiment, the initial conductive layer 206 includes: a contact layer located on the surface of the source-drain doped layer 205 exposed, a metal layer located on the contact layer, and a third protective layer located on the metal layer.

[0070] In this embodiment, the contact layer reduces the contact resistance between the metal layer and the source / drain doped layer 205, and the method for forming the contact layer includes: forming an initial contact layer (not shown) on the exposed surface of the source / drain doped layer 205; and annealing the initial contact layer to form the contact layer.

[0071] In this embodiment, the annealing process includes: an annealing time of 5s to 30s; and an annealing temperature of 600°C to 1000°C.

[0072] Please refer to Fig.10 , Fig.10 and Figure 8 In accordance with the viewing direction, after the initial conductive layer 206 is formed, a dielectric layer 207 is formed on the substrate, and the dielectric layer 207 covers the initial dummy gate structure 203 and the sidewalls of the initial conductive layer 206.

[0073] In this embodiment, the method for forming the dielectric layer 207 includes: forming an initial dielectric layer (not shown) on the isolation layer 202, the initial dielectric layer covering the initial conductive layer 206 and the initial pseudo-gate structure 203; and planarizing the initial dielectric layer until the top surfaces of the initial pseudo-gate structure 203 and the initial conductive layer 206 are exposed, thereby forming the dielectric layer 207.

[0074] In this embodiment, the material of the dielectric layer 207 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0075] Please refer to Fig.11 After forming the dielectric layer 207 , the initial dummy gate structure 203 is removed, and a first opening 208 is formed between adjacent initial conductive layers 206 .

[0076] In this embodiment, the first opening 208 is used to provide space for subsequently forming a gate structure.

[0077] In this embodiment, the process of removing the initial dummy gate structure 203 is a wet etching process; in other embodiments, the process of removing the initial dummy gate structure may also be a dry etching process.

[0078] Please refer to Fig.12 After forming the first opening 208 , an initial gate structure 209 is formed in the first opening 208 .

[0079] In this embodiment, the initial gate structure 209 includes: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a second protection layer located on the gate layer.

[0080] In this embodiment, the material of the gate dielectric layer includes a high-K dielectric material.

[0081] The material of the gate layer includes metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the material of the gate layer is tungsten.

[0082] In this embodiment, the material of the second protection layer is silicon nitride.

[0083] Please refer to Fig.13 After forming the initial gate structure 209, a portion of the initial conductive layer 206 is etched away to form a conductive layer 210 and a first isolation opening (not marked) located in the dielectric layer 207, wherein the first isolation opening penetrates the conductive layer 210 along the second direction X; a first isolation structure 211 is formed in the first isolation opening; a portion of the initial gate structure 209 is etched away to form a gate structure 212 and a second isolation opening (not marked) located in the dielectric layer 207, wherein the second isolation opening penetrates the gate structure along the second direction X; a second isolation structure 213 is formed in the second isolation opening.

[0084] In this embodiment, the initial gate structure 209 and the initial conductive layer 206 are etched simultaneously using the same photomask; in other embodiments, the initial gate structure and the initial conductive layer may be etched step by step using different photomasks.

[0085] Electrical isolation and insulation are achieved by the first isolation structure 211 and the second isolation structure 213 , thereby preventing short circuits between adjacent gate structures 212 and adjacent conductive layers 210 .

[0086] In this embodiment, the first isolation structure 211 and the second isolation structure 213 are made of silicon oxide.

[0087] Please refer to Fig.14 and 15 , Fig.15 yes Fig.14In the cross-sectional view along line EE, after the gate structure 212 and the conductive layer 210 are formed, a first conductive plug 214 and a second conductive plug 215 are formed, wherein the first conductive plug 214 contacts the gate structure 212 and the second conductive plug 215 contacts the conductive layer 210.

[0088] In this embodiment, the gate structure 212 includes a first region I and a second region II arranged along the first direction Y, the conductive layer 210 is located on both sides of the first region I of the gate structure 212, the first conductive plug 214 is in contact with the first region I of the gate structure 212, and the second conductive plug 215 is in contact with the conductive layer 210.

[0089] By making the first conductive plug 214 contact the first region I of the gate structure 212 and the second conductive plug 215 contact the conductive layer 210, the distance between the first conductive plug 214 and the second conductive plug 215 can be effectively reduced, thereby improving the integration of the components of the finally formed semiconductor structure.

[0090] In this embodiment, the second conductive plug 215 is located on a portion of the top surface of the gate structure 212 , and the second conductive plug 215 is in contact with the spacer 204 .

[0091] The second conductive plug 215 is located on a portion of the top surface of the gate structure 212, and the second conductive plug 215 is in contact with the side wall 204, so that the formed second conductive plug 215 is a self-aligned structure. In the process of forming the second conductive plug 215, the accuracy of the mask opening is reduced, thereby effectively reducing the process difficulty.

[0092] The first conductive plug 214 and the second conductive plug 215 are made of metal, including tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the first conductive plug 214 and the second conductive plug 215 are made of tungsten.

[0093] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig.14 , including: a substrate; a gate structure 212 located on the substrate, the gate structure 212 extending along a first direction Y; a source-drain doped layer 205 located in the substrate on both sides of the gate structure 212; a conductive layer 210 located on the source-drain doped layer 205, the conductive layer 210 covering the sidewalls and top surface of the source-drain doped layer 205; a dielectric layer 207 located on the substrate, the dielectric layer 207 covering the conductive layer 210 and the sidewalls of the gate structure 212.

[0094] The conductive layer 210 is located on the source-drain doped layer 205, and the conductive layer 210 covers the side walls and top surface of the source-drain doped layer 205, thereby effectively increasing the contact area between the conductive layer 210 and the source-drain doped layer 205, reducing the contact resistance between the conductive layer 210 and the source-drain doped layer 205, and thus improving the performance of the semiconductor structure finally formed.

[0095] In this embodiment, the gate structure 212 includes: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a second protection layer located on the gate layer.

[0096] In this embodiment, the sidewall spacer 204 is located on the sidewall of the gate structure 212 .

[0097] In this embodiment, the first conductive plug 214 and the second conductive plug 215 are further included. The first conductive plug 214 is in contact with the gate structure 212 , and the second conductive plug 215 is in contact with the conductive layer 210 .

[0098] In this embodiment, the gate structure 212 includes a first region I and a second region II arranged along the first direction Y, the conductive layer 210 is located on both sides of the first region I of the gate structure 212, the first conductive plug 214 is in contact with the first region I of the gate structure 210, and the second conductive plug 215 is in contact with the conductive layer 210.

[0099] By making the first conductive plug 214 contact the first region I of the gate structure 212 and the second conductive plug 215 contact the conductive layer 210, the distance between the first conductive plug 214 and the second conductive plug 215 can be effectively reduced, thereby improving the integration of the components of the finally formed semiconductor structure.

[0100] In this embodiment, the second conductive plug 215 is located on a portion of the top surface of the gate structure 212 , and the second conductive plug 215 is in contact with the spacer 204 .

[0101] The second conductive plug 215 is located on a portion of the top surface of the gate structure 212, and the second conductive plug 215 is in contact with the side wall 204, so that the formed second conductive plug 215 is a self-aligned structure. In the process of forming the second conductive plug 215, the accuracy of the mask opening is reduced, thereby effectively reducing the process difficulty.

[0102] In this embodiment, it also includes: a first isolation structure 211 and a second isolation structure 213 located in the dielectric layer 207 , the first isolation structure 211 contacts the side wall of the gate structure 212 , and the second isolation structure 213 contacts the side wall of the conductive layer 210 .

[0103] In this embodiment, the substrate includes: a base 200 and a plurality of mutually discrete fins 201 located on the base 200, wherein the fins 201 extend along a second direction X, and the first direction Y is perpendicular to the second direction X; the gate structure 212 spans the fins 201, and the gate structure 212 covers a portion of the sidewalls and top surface of the fins 201; the source-drain doping layer 205 is located in the fins 201 on both sides of the gate structure 212.

[0104] In this embodiment, the top or sidewall of the source / drain doping layer 205 protrudes from the surface of the fin 201 .

[0105] In this embodiment, the present invention further includes: an isolation layer 202 located on the substrate, the isolation layer 202 covers a portion of the sidewall of the fin 201 , and the gate structure 212 is located on the isolation layer 202 .

[0106] In this embodiment, the conductive layer 210 includes: a contact layer located on the surface of the source-drain doped layer 205 exposed, and a metal layer located on the contact layer.

[0107] In this embodiment, the conductive layer further includes: a third protective layer located on the metal layer.

[0108] In this embodiment, the first conductive plug 214 is located on a portion of the top surface of the conductive layer 210 , and the first conductive plug 214 is in contact with the third protection layer.

[0109] In this embodiment, the material of the contact layer is titanium silicon. In other embodiments, the material of the contact layer may also be nickel silicon or cobalt silicon.

[0110] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming an initial dummy gate structure on a substrate, wherein the initial dummy gate structure extends along a first direction; forming a source-drain doped layer in the substrate on both sides of the initial dummy gate structure; After the source-drain doping layer, an initial conductive layer is formed on the source-drain doping layer, wherein the initial conductive layer covers all side walls and top surfaces of the source-drain doping layer; After forming the initial conductive layer, removing the initial dummy gate structure; After forming the initial conductive layer and before removing the initial dummy gate structure, the method further includes: A dielectric layer is formed on the substrate, wherein the dielectric layer covers the sidewalls of the initial pseudo gate structure and the initial conductive layer; wherein: The width dimension of the source-drain doped layer close to the substrate is smaller than the maximum width dimension of the source-drain doped layer; The method for forming the dielectric layer comprises: forming an initial dielectric layer, the initial dielectric layer covering the initial conductive layer and the initial dummy gate structure; and flattening the initial dielectric layer until the top surfaces of the initial dummy gate structure and the initial conductive layer are exposed to form the dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The initial dummy gate structure includes: a dummy gate dielectric layer, a dummy gate layer located on the dummy gate dielectric layer, and a first protection layer located on the dummy gate layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: After forming the initial dummy gate structure and before forming the source-drain doping layer, the method further includes: forming a sidewall on the substrate, wherein the sidewall is located on a sidewall of the initial dummy gate structure.

4. The method for forming a semiconductor structure according to claim 3, wherein: A first opening is formed between adjacent initial conductive layers, and after the first opening is formed, the method further includes: forming an initial gate structure in the first opening.

5. The method for forming a semiconductor structure according to claim 4, wherein: The initial gate structure includes: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a second protection layer located on the gate layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: After forming the initial gate structure, it also includes: etching away part of the initial conductive layer to form a conductive layer and a first isolation opening located in the dielectric layer, the first isolation opening penetrates the conductive layer along a second direction, and the first direction is perpendicular to the second direction; forming a first isolation structure in the first isolation opening.

7. The method for forming a semiconductor structure according to claim 6, wherein: After forming the initial gate structure, the method further includes: etching and removing a portion of the initial gate structure to form a gate structure and a second isolation opening located in the dielectric layer, wherein the second isolation opening penetrates the gate structure along the second direction; and forming a second isolation structure in the second isolation opening.

8. The method for forming a semiconductor structure according to claim 7, wherein: After forming the gate structure and the conductive layer, the method further includes: forming a first conductive plug and a second conductive plug, wherein the first conductive plug contacts the gate structure, and the second conductive plug contacts the conductive layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The gate structure includes a first region and a second region arranged along the first direction, the conductive layer is located at both sides of the first region of the gate structure, the first conductive plug contacts the first region of the gate structure, and the second conductive plug contacts the conductive layer.

10. The method for forming a semiconductor structure according to claim 8, wherein: The second conductive plug is located on a portion of the top surface of the gate structure, and the second conductive plug is in contact with the spacer.

11. The method for forming a semiconductor structure according to claim 1, wherein: The initial conductive layer includes: a contact layer located on the surface of the source-drain doped layer exposed, and a metal layer located on the contact layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The initial conductive layer further includes: a third protective layer located on the metal layer.

13. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the contact layer includes: forming an initial contact layer on the surface of the source-drain doping layer exposed; and annealing the initial contact layer to form the contact layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The annealing process includes: an annealing time of 5s to 30s; and an annealing temperature of 600°C to 1000°C.

15. A semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 1 to 14, characterized in that: include: substrate; A gate structure located on the substrate, the gate structure extending along a first direction; Source and drain doping layers located in the substrate on both sides of the gate structure; A conductive layer located on the source-drain doped layer, the conductive layer covers all side walls and top surfaces of the source-drain doped layer; wherein, The method for forming the conductive layer includes: etching and removing a portion of the initial conductive layer to form the conductive layer and a first isolation opening located in the dielectric layer, wherein the first isolation opening penetrates the conductive layer along a second direction, and the first direction is perpendicular to the second direction.

16. The semiconductor structure according to claim 15, characterized in that: The gate structure includes: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a second protection layer located on the gate layer.

17. The semiconductor structure according to claim 15, wherein: Also includes: A first conductive plug and a second conductive plug, wherein the first conductive plug contacts the gate structure, and the second conductive plug contacts the conductive layer.

18. The semiconductor structure according to claim 17, wherein: The gate structure includes a first region and a second region arranged along the first direction, the conductive layer is located at both sides of the first region of the gate structure, the first conductive plug contacts the first region of the gate structure, and the second conductive plug contacts the conductive layer.

19. The semiconductor structure according to claim 17, wherein: The second conductive plug is located on a portion of the top surface of the gate structure, and the second conductive plug is in contact with a sidewall spacer located on a sidewall of the gate structure.

20. The semiconductor structure according to claim 15, wherein: Also includes: a dielectric layer located on the substrate, the dielectric layer covering the conductive layer and the sidewalls of the gate structure; A first isolation structure and a second isolation structure are located in the dielectric layer, the first isolation structure contacts the side wall of the gate structure, and the second isolation structure contacts the side wall of the conductive layer.

21. The semiconductor structure according to claim 17, wherein: The conductive layer includes: a contact layer located on the surface of the source-drain doped layer exposed, and a metal layer located on the contact layer.

22. The semiconductor structure according to claim 21, wherein: The conductive layer further includes: a third protective layer located on the metal layer.

23. The semiconductor structure according to claim 22, characterized in that: The first conductive plug is located on a portion of the top surface of the conductive layer, and the first conductive plug is in contact with the third protection layer.

24. The semiconductor structure according to claim 21, wherein: The material of the contact layer includes nickel silicon, titanium silicon or cobalt silicon.

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