Chip and control method

Abstract

The present application discloses a chip and a control method, wherein the chip includes a cache, a flash memory and a processor, wherein the cache or the flash memory is used to store target data, and when the chip is in a preset clock mode, the processor is used to preferentially obtain the target data from the cache; and when the target data cannot be obtained from the cache, the flash memory is controlled to enter a working mode, and after the target data is obtained from the flash memory, the flash memory is controlled to enter a low power consumption mode. The present application can reduce the overall power consumption of the chip read operation.

Description

Technical Field

[0001] The present application relates to the technical field of microcontrollers, and in particular to a chip and a control method. Background Art

[0002] SoC (System on Chip), also known as system on chip, is a micro system. In low-power applications, such as low-power read operations, a low-speed clock is often used as the SoC operating frequency to reduce power consumption. At this operating frequency, the dynamic power consumption and static power consumption of the logic circuit of the SoC are very low, but the overall power consumption of the SoC is often at a high level, making the overall power consumption of the SoC not low in low-speed working mode. Summary of the invention

[0003] The embodiments of the present application provide a chip and a control method, which can reduce the overall power consumption of chip reading operations.

[0004] In a first aspect, an embodiment of the present application provides a chip, including: a cache, a flash memory, and a processor, wherein the cache or the flash memory is used to store target data;

[0005] When the chip is in a preset clock mode,

[0006] The processor is used to preferentially obtain the target data from the cache; and when the target data cannot be obtained from the cache, control the flash memory to enter a working mode, and after obtaining the target data from the flash memory, control the flash memory to enter a low power consumption mode.

[0007] Optionally, the chip further includes a control module;

[0008] The processor is configured to send a first read request for the target data;

[0009] the cache being configured to send a second read request for the target data to the control module after the processor fails to obtain the target data from the cache according to the first read request;

[0010] The control module is used to control the flash memory to enter a working mode according to the second read request, and after reading the target data from the flash memory, control the flash memory to enter a low power consumption mode and send the target data to the cache.

[0011] Optionally, the control module includes:

[0012] A controller, configured to send a first power supply control instruction according to the second read request;

[0013] a power management unit, configured to control the flash memory to enter a working mode according to the first power supply control instruction, and send a read permission instruction to the controller;

[0014] The controller is further configured to read the target data from the flash memory according to the read permission instruction, send the target data to the cache, and send a second power supply control instruction to the power management unit;

[0015] The power management unit is further configured to adjust the power supply voltage to the flash memory according to the second power supply control instruction so that the flash memory enters the low power consumption mode.

[0016] Optionally, the power management unit is further configured to adjust the power supply voltage of the flash memory according to the second power supply control instruction so that the flash memory enters the low power consumption mode, including:

[0017] The power management unit is further configured to cut off power to the flash memory or adjust the voltage of the flash memory to a preset voltage according to the second power supply control instruction, wherein the preset voltage is lower than a normal operating voltage of the flash memory.

[0018] Optionally, the cache, the flash memory and the processor are integrated into one module.

[0019] Optionally, the cache and the processor are integrated into one module, and the flash memory is arranged outside the module.

[0020] Optionally, the cache is a cache memory or a buffer register.

[0021] In a second aspect, an embodiment of the present application provides a chip control method, which is applied to the chip as described above, and the method includes:

[0022] When the chip is in a preset clock mode, the processor preferentially obtains the target data from the cache, and when the processor fails to obtain the target data from the cache, the processor controls the flash memory to enter a working mode, and after obtaining the target data from the flash memory, controls the flash memory to enter a low power consumption mode.

[0023] Optionally, the method further includes:

[0024] The processor sends a first read request for the target data to the cache;

[0025] If the processor fails to obtain the target data from the cache, the cache sends a second read request for the target data to the control module;

[0026] The control module controls the flash memory to enter a working mode according to the second read request;

[0027] The control module reads the target data from the flash memory, sends the target data to the cache, and controls the flash memory to enter the low power consumption mode.

[0028] Optionally, the method further includes:

[0029] The controller sends a first power supply control instruction to the power management unit according to the second read request;

[0030] The power management unit controls the flash memory to enter a working mode according to the first power supply control instruction, and sends a read permission instruction to the controller;

[0031] The controller reads the target data from the flash memory according to the read permission instruction, sends the target data to the cache, and sends a second power supply control instruction to the power management unit;

[0032] The power management unit adjusts the power supply voltage to the flash memory according to the second power supply control instruction so that the flash memory enters the low power consumption mode.

[0033] Optionally, the power management module adjusts the power supply voltage of the flash memory according to the second power supply control instruction so that the flash memory enters the low power consumption mode, including:

[0034] The power management module cuts off power to the flash memory or adjusts the voltage of the flash memory to a preset voltage according to the second power supply control instruction, where the preset voltage is lower than a normal operating voltage of the flash memory.

[0035] In an embodiment of the present application, the chip may include a cache, a flash memory, and a processor. The cache and the flash memory may store target data. When the chip is in a preset clock mode, the processor preferentially obtains the target data from the cache. When the target data fails to be obtained from the cache, the processor controls the flash memory to enter the working mode, and then obtains the target data from the flash memory, and controls the flash memory to enter the low power mode after obtaining the target data. That is, in an embodiment of the present application, the target data is preferentially obtained from the cache with high speed and low power consumption. When the target data is stored in the cache, it is not necessary to read the target data from the flash memory with slow speed and high power consumption. At this time, the flash memory is in the low power mode. Only when the target data is not stored in the cache, the processor will obtain the target data from the flash memory. At this time, the flash memory will be controlled to enter the working mode from the low power mode, and after obtaining the target data from the flash memory, the flash memory will be controlled to enter the low power mode. The flash memory can remain in the low power mode most of the time. Therefore, the embodiment of the present application can reduce the overall power consumption of the chip read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The technical solution and beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0037] Figure 1 It is a schematic diagram of the structure of the chip provided in Example 1 of the present application.

[0038] Figure 2 This is another structural schematic diagram of the chip provided in Example 2 of the present application.

[0039] Figure 3 It is a logic control diagram of the chip provided in the embodiment of the present application.

[0040] Figure 4 It is another logic control diagram of the chip provided in the embodiment of the present application.

[0041] Figure 5 This is another structural diagram of the chip provided in Example 2 of this application.

[0042] Figure 6 It is a flow chart of the chip control method provided in Example 3 of the present application.

[0043] Figure 7 It is a flow chart of another chip control method provided in Example 4 of the present application. DETAILED DESCRIPTION

[0044] Please refer to the drawings, where the same component symbols represent the same components. The principle of the present application is illustrated by implementing it in an appropriate computing environment. The following description is based on the illustrated specific embodiments of the present application, which should not be considered as limiting other specific embodiments of the present application that are not described in detail herein.

[0045] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of a chip provided in the first embodiment of the present application. The chip 100 may include: a cache 101, a flash memory 102, and a processor 103. The cache 101 and the flash memory 102 may store target data, and the processor 103 may obtain the target data from the cache 101 or the flash memory 102.

[0046] Due to the development of integrated circuit multi-process integration technology and application-oriented system-on-chip (SoC), a complex electronic system can be realized on a single integrated circuit chip, such as mobile phone chips, digital TV chips, DVD chips, etc. In low-power applications, such as low-power read operations, in order to reduce power consumption, a low-speed clock is often used as the SoC operating frequency. At this operating frequency, the dynamic power consumption and static power consumption of the logic circuit of the SoC are very low, but in order to maintain the operation of the SoC, part of the SoC's memory (such as non-volatile memory) must be in a working state to ensure that the CPU can execute the program smoothly. When this type of memory is in a working state, even if there is no read or write operation, it still requires a certain amount of working current to maintain its working state, resulting in the overall power consumption of the SoC in the low-speed clock working mode is still high.

[0047] In this embodiment, the cache 101 can be a cache memory or a buffer register. The cache memory and the buffer register have relatively small capacity but much higher speed than the main memory, close to the speed of the CPU, and thus have lower power consumption. The flash memory 102 is a non-volatile memory (NVM for short). When the current is turned off, the data stored in the non-volatile memory will not disappear. Compared with the cache 101, the flash memory 102 has a lower read and write speed and much higher power consumption. It is understandable that the priority of the cache 101 is higher than that of the flash memory 102. When the processor 103 reads data, it gives priority to reading from the cache 101, which can reduce power consumption.

[0048] It should be noted that the target data can be preferentially stored in the cache 101 to speed up the reading speed of the chip. When the cache 101 is full of other data or the preset data format stored in the cache 101 has been set in advance, if the data format of the target data is different from the preset data format, the target data is stored in the flash memory 102. When the storage space of the cache 101 is insufficient, a part of the target data (data A) can be stored in the cache 101, and the other part of the target data (data B) can be stored in the flash memory 102.

[0049] When the processor 103 reads the target data, it first reads from the cache 101 with a high priority, which can reduce power consumption. When the target data is not stored in the cache 101, it is read from the flash memory 102. For example, when the chip 100 is in a preset clock mode, when the target data is stored in the cache 101, the processor 103 can directly read the target data from the cache 101, which not only has a fast data reading speed, but also can reduce the power consumption of data reading. At the same time, since there is no need to read the target data from the flash memory 102, the flash memory 102 can be in a low power consumption mode at this time to reduce the overall power consumption of the chip.

[0050] For another example, when the target data is stored in the flash memory 102, after the processor 103 fails to obtain the target data from the cache 101, the processor 103 can control the flash memory 102 to enter the working mode from the low power mode, and then can read the target data from the flash memory 102. After reading the target data from the flash memory 102, the processor 103 can control the flash memory 102 to enter the low power mode to reduce the overall power consumption of the chip.

[0051] For another example, when the storage space of cache 101 is insufficient, a part of the target data (assuming data A) is stored in cache 101, and another part of the target data (assuming data B) is stored in flash memory 102, after confirming that cache 101 only stores data A, processor 103 can read data A from cache 101, and control flash memory 102 to enter working mode from low power mode, and then read data B from flash memory 102, and after obtaining data B from flash memory 102, control flash memory 102 to enter low power mode, and synthesize data A and data B into target data. Flash memory 102 is in working mode only when reading and writing, and is in low power mode most of the time, thereby reducing the overall power consumption of chip read and write operations.

[0052] It should be noted that the clock mode can be divided by clock frequency, and different clock frequencies result in different working states of the chip 100. For example, at a high-speed clock frequency, the chip is in a normal working state, and at a low-speed clock frequency, the chip can be in a low-power state such as sleep. In this embodiment, the preset clock mode is a low-speed clock mode. For example, the clock frequency of the preset clock mode can be 32KHz, and the chip 100 is in a low-power application state in the preset clock mode.

[0053] It can be understood that, in the embodiment of the present application, the chip 100 may include a cache 101, a flash memory 102, and a processor 103. The cache 101 and the flash memory 102 may store target data, and when the chip 100 is in a preset clock mode, the processor 103 preferentially obtains the target data from the cache 101, and when the processor 103 fails to obtain the target data from the cache 101, the processor 103 controls the flash memory 102 to enter the working mode, and then obtains the target data from the flash memory 102, and controls the flash memory 102 to enter the low power consumption mode after obtaining the target data. That is, in the embodiment of the present application, the target data is preferentially obtained from the high-speed cache with low power consumption. When the target data is stored in the cache 101, it is not necessary to read the target data from the slow and high-power flash memory 102. At this time, the flash memory 102 is in a low-power mode. Only when the target data is not stored in the cache 101, the processor 103 will obtain the target data from the flash memory 102. At this time, the flash memory 102 will be controlled to switch from the low-power mode to the working mode, and after obtaining the target data from the flash memory 102, the flash memory 102 will be controlled to enter the low-power mode. The flash memory 102 can remain in the low-power mode most of the time. Therefore, the embodiment of the present application can reduce the overall power consumption of the chip 100 read operation.

[0054] See also Figure 2 , Figure 2 1 is a schematic diagram of the structure of a chip provided in the second embodiment of the present application. The chip 100 may include: a cache 101, a flash memory 102, a processor 103 and a control module 104. The cache 101 and the flash memory 102 may store target data. In one of the connection modes, the processor 103 may be connected to the cache 101, the cache 101 may be connected to the control module 104, and the control module 104 may be connected to the flash memory 102.

[0055] In this embodiment, the processor 103 sends a first read request for the target data to the cache 101. After receiving the first read request, if the cache 101 does not store the target data, the cache 101 may send a second read request for the target data to the control module 104. The control module 104 controls the flash memory 102 to enter the working mode according to the second read request, and after reading the target data from the flash memory 102, controls the flash memory 102 to enter the low power consumption mode and sends the target data to the cache 101. Of course, after receiving the first read request, if the cache 101 stores the target data, the processor 103 may read the target data directly from the cache 101.

[0056] In this embodiment, after receiving the second read request sent by the cache 101, the control module 104 can control the flash memory 102 to enter the working mode, and after reading the target data from the flash memory 102, control the flash memory 102 to enter the low power consumption mode. As some examples, the low power consumption mode can be a low voltage holding state or a power-off state. For example, after receiving the second read request sent by the cache 101, if the flash memory 102 is in the low voltage holding state, the control module 104 can control the flash memory 102 to return to the normal working voltage; for another example, after receiving the second read request sent by the cache 101, if the flash memory 102 is in the power-off state, the control module 104 can control the flash memory 102 to be powered on so that the flash memory 102 enters the working mode.

[0057] For example, see Figure 3 , Figure 3 It is a logic control diagram of the chip 100 provided in the embodiment of the present application in the low-speed clock mode. The processor 103 sends a first read request for the target data to the cache 101. When the target data is not stored in the cache 101, it indicates a "miss", and the control module 104 sends a second read request to the flash memory 102 to restore the normal working voltage of the flash memory 102 and enter the working mode. After the flash memory 102 enters the working mode, the control module 104 can read the target data from the flash memory 102, and then control the flash memory 102 to enter a low voltage holding state, for example, controlling the power supply voltage of the flash memory 102 to be a preset voltage threshold, and the preset voltage threshold is lower than the normal working voltage of the flash memory 102. After obtaining the target data, the control module 104 can send the target data to the cache 101, so that the processor 103 can obtain the target data from the cache 101. When the target data is stored in the cache 101, it indicates a "hit", and the processor 103 directly obtains the target data from the cache 101, and the flash memory 102 is still in a low power consumption mode of a low voltage holding state. In this embodiment, the flash memory 102 is in a low voltage holding state when not being accessed, which consumes less power than normal operation, thereby reducing the overall power consumption of the chip 100 in a read operation in a low-speed clock mode. At the same time, the recovery time from the low voltage state to the normal operating voltage is short, thereby improving the working efficiency of the chip.

[0058] For example, see Figure 4 , Figure 4 is another logic control diagram of the chip 100 provided in the embodiment of the present application in the low-speed clock mode. Figure 3 The difference is that in this embodiment, the flash memory 102 is in a power-off state when not being accessed. Compared with the low voltage holding state, completely powering off can greatly reduce its power consumption during the non-access period. Thus, the overall power consumption of the chip 100 in the read operation in the low-speed clock mode can be greatly reduced.

[0059] As an example, see Figure 2 In this embodiment, the control module 104 may further include a controller 1041 and a power management unit 1042. In one connection mode, the controller 1041 is connected to the cache 101 and the flash memory 102 respectively, and the power management unit 1042 is connected to the flash memory 102 and the controller 1041. The controller 1041 may send a first power supply control instruction to the power management unit 1042 according to the second read request. For example, the first power supply control instruction may be a request power supply instruction to enable the flash memory 102 to enter the working mode from the low power consumption mode. The power management unit 1042 may control the flash memory 102 to enter the working mode according to the first power supply control instruction, and send a read permission instruction to the controller 1041. For example, the read permission instruction may be a signal indicating that the flash memory 102 has been powered on to enable the flash memory 102 to enter the working mode. The controller 1041 may access the flash memory 102 according to the read permission instruction, read the target data from the flash memory 102, send the target data to the cache 101, and send a second power supply control instruction to the power management unit 1042. For example, the second power supply control instruction may be a request power off instruction or a low voltage maintenance instruction to enable the flash memory 102 to enter the low power consumption mode. The power management unit 1042 may adjust the supply voltage to the flash memory 102 according to the second power supply control instruction to enable the flash memory 102 to enter the low power consumption mode.

[0060] In order to further reduce the overall power consumption of chip 100 under the preset clock mode, a large-capacity cache memory can also be used as cache 101. For example, the capacity of cache 101 can be 8M, 16M or 32M, etc. The use of a large-capacity cache 101 can reduce the frequency of processor 103 accessing flash memory 102, thereby reducing the number of times the flash memory 102 is powered on, and the target data can be read directly from the cache 101, which not only achieves the purpose of reducing the overall power consumption of chip 100 during read operations, but also improves the efficiency of program execution.

[0061] It should be noted that, as an example, the cache 101, the flash memory 102 and the processor 103 are integrated into one module, and its structure diagram is as follows: Figure 2 As shown, the SoC can have a built-in flash memory 102, and the chip reading speed of this structure is faster. As another example, the cache 101 and the processor 103 can be integrated into a SoC module, and the flash memory 102 is set outside the SoC module. The structure diagram is as shown in FIG. Figure 5As shown, the flash memory 102 can be set outside the SoC, but the power management unit 1042 can still perform power control. The flash memory 102 is set outside the SoC. Although the chip processing speed is reduced, it can adapt to different application scenarios. Therefore, different chip structures in this embodiment can meet different application scenarios and balance different requirements for power consumption and speed.

[0062] It can be understood that, in the embodiment of the present application, the chip 100 may include a cache 101, a flash memory 102, a processor 103 and a control module 104, and the control module 104 may also include a controller 1041 and a power management unit 1042. The processor 103 may send a first read request for target data to the cache 101, and when the cache 101 does not store the target data, it may send a second read request for the target data to the controller 1041; the controller 1041 may send a first power supply control instruction to the power management unit 1042 according to the second read request; the power management unit 1042 may control the flash memory 102 to enter the working mode according to the first power supply control instruction, and send a read permission instruction to the controller 1041; the controller 1041 may read the target data from the flash memory 102 according to the read permission instruction, send the target data to the cache 101, and send a second power supply control instruction to the power management unit 1042. The power management unit 1042 can adjust the power supply voltage of the flash memory 102 according to the second power supply control instruction to make the flash memory 102 enter a power-off state or a low-voltage holding state, and the cache 101 sends the target data to the processor 103 .

[0063] In the embodiment of the present application, when the target data is stored in the cache 101, it is not necessary to read the target data from the flash memory 102. At this time, the flash memory 102 is in a low voltage holding state or a power-off state. Only when the target data is not stored in the cache 101, the processor 103 will obtain the target data from the flash memory 102. At this time, the flash memory 102 will be controlled by the control module 104 to enter the working mode from the low voltage holding state or the power-off state, and after obtaining the target data from the flash memory 102, the flash memory 102 will be controlled by the control module 104 to enter the low voltage holding state or the power-off state. The flash memory 102 can be kept in a low power consumption mode of a low voltage state or a power-off state for most of the time. Therefore, the embodiment of the present application can reduce the overall power consumption of the read and write operations of the chip 100.

[0064] An embodiment of the present application also provides a chip control method, which can be applied to the chips of the above embodiments, and the method includes: when the chip is in a preset clock mode, the processor preferentially obtains target data from the cache, and when the processor fails to obtain the target data from the cache, the processor controls the flash memory to enter the working mode, and after obtaining the target data from the flash memory, controls the flash memory to enter the low power consumption mode.

[0065] In one embodiment, see Figure 6 , Figure 6 : is a flow chart of a chip control method provided in the third embodiment of the present application, and the method may include:

[0066] 601. The processor sends a first read request for target data to the cache.

[0067] In this embodiment, the priority of the cache is higher than that of the flash memory. When the processor needs to obtain the target data, it preferentially sends the first read request for the target data to the cache memory. For example, the cache memory may be a cache memory or a buffer register, and the flash memory may be a non-volatile memory (such as Flash). When the processor reads the data, it preferentially sends the first read request for the target data to the cache memory to read the target data from the cache memory.

[0068] 602. If the processor fails to obtain the target data from the cache, the cache sends a second read request for the target data to the control module.

[0069] It should be noted that the target data is preferentially stored in the cache to speed up data reading; when the cache is full of other data or the preset data format for cache storage has been set in advance, if the data format of the target data is different from the preset data format, the target data is stored in the flash memory. When the storage space of the cache is insufficient, part of the target data (data A) can be stored in the cache, and the other part of the target data (data B) can be stored in the flash memory.

[0070] When the processor reads the target data, it first reads from the high-priority cache. When the target data is not stored in the cache, it reads from the flash memory. For example, when the chip is in the preset clock mode, when the target data is stored in the cache, the processor can read the target data directly from the cache to speed up the data reading speed. Compared with reading the target data from the flash memory, reading the target data from the cache consumes less power. At the same time, since the target data does not need to be read from the flash memory, the flash memory can be in low power mode at this time, thereby reducing the overall power consumption of the chip.

[0071] For another example, when the target data is stored in the flash memory, after the processor confirms that the target data is not stored in the cache, that is, after failing to obtain the target data from the cache, it can control the flash memory to enter the working mode from the low power mode, and then read the target data from the flash memory. After reading the target data from the flash memory, the flash memory can be controlled to enter the low power mode to reduce the overall power consumption of the chip.

[0072] For another example, when the cache storage space is insufficient, part of the target data (assumed to be data A) is stored in the cache, and the other part of the target data (assumed to be data B) is stored in the flash memory, the processor can read data A from the cache after confirming that the cache only stores data A, and control the flash memory to enter the working mode from the low power mode, and then read data B from the flash memory, and after obtaining data B from the flash memory, control the flash memory to enter the low power mode, and synthesize data A and data B into the target data.

[0073] In this embodiment, when the processor needs to obtain target data, it may preferentially send a first read request for the target data to the cache. If the cache does not store the target data, the cache sends a second read request for the target data to the control module.

[0074] 603. The control module controls the flash memory to enter a working mode according to the second read request.

[0075] For example, after receiving the second read request sent by the cache, the control module can control the flash memory to enter the working mode from the low power mode. For example, after receiving the second read request sent by the cache, if the flash memory is in a low voltage holding state, the control module can control the flash memory to return to the working voltage. For another example, after receiving the second read request sent by the cache, if the flash memory is in a power-off state, the control module can control the flash memory to be powered on so that the flash memory enters the working mode.

[0076] 604. The control module reads the target data from the flash memory, sends the target data to the cache, and controls the flash memory to enter a low power consumption mode.

[0077] For example, after the flash memory switches from the low-power mode to the working mode, the control module can read the target data from the flash memory and send the target data to the cache so that the processor can obtain the target data from the cache. Then the control module controls the flash memory to enter the low-power mode. For example, the control module can control the power supply voltage of the flash memory to be a preset voltage threshold, which is lower than the working voltage of the flash memory, so that the flash memory is in a low-voltage holding state, thereby reducing the overall power consumption of the chip reading operation. At the same time, the recovery time from the low-voltage state to the working voltage is short, thereby improving the working efficiency of the chip. For another example, the control module can control the flash memory to be in a power-off state. Complete power off can greatly reduce its power consumption during the period when it is not accessed, thereby reducing the overall power consumption of the chip reading operation.

[0078] In the embodiment of the present application, when the target data is stored in the cache, the target data is directly read from the cache. At this time, the flash memory is in low power consumption mode. Only when the target data is not stored in the cache, the processor will obtain the target data from the flash memory. At this time, the control module will control the flash memory to enter the working mode from the low power consumption mode, and after obtaining the target data from the flash memory, the control module will control the flash memory to enter the low power consumption mode. The flash memory can remain in the low power consumption mode most of the time. Therefore, the embodiment of the present application can reduce the overall power consumption of the chip read and write operations.

[0079] In one embodiment, see Figure 7 , Figure 7 : is a flowchart of a chip control method provided in the fourth embodiment of the present application, and the method may include:

[0080] 701. The processor sends a first read request for target data to the cache.

[0081] For the specific implementation of 701, please refer to the embodiment of 601, which will not be repeated here.

[0082] 702. If the processor fails to obtain the target data from the cache, the cache sends a second read request for the target data to the controller.

[0083] It should be noted that the target data is preferentially stored in the cache to speed up the data reading speed; when the cache is full of other data or the preset data format of the cache storage has been set in advance, if the data format of the target data is different from the preset data format, the target data is stored in the flash memory. When the cache receives a first read request for the target data sent by the processor, if the cache does not store the target data, the cache sends a second read request for the target data to the controller.

[0084] 703. The controller sends a first power supply control instruction to the power management unit according to the second read request.

[0085] For example, after receiving the second read request sent by the cache, the controller may send a first power supply control instruction to the power management unit. For example, the first power supply control instruction may be a power supply request instruction to enable the flash memory to enter the working mode from the low power consumption mode.

[0086] 704. The power management unit controls the flash memory to enter a working mode according to the first power supply control instruction, and sends a read permission instruction to the controller.

[0087] For example, after receiving the first power supply control instruction, the power management unit can provide an operating voltage to the flash memory so that the flash memory enters the working mode from the low power consumption mode, and at the same time, the power management unit can also send a read permission instruction to the controller to allow the controller to read the target data from the flash memory. The read permission instruction can be a signal indicating that the flash memory has been powered on and entered the working mode.

[0088] 705. The controller reads the target data from the flash memory according to the read permission instruction, sends the target data to the cache, and sends a second power supply control instruction to the power management unit.

[0089] For example, after receiving the read permission instruction sent by the power management unit, the controller can read the target data from the flash memory and send the target data to the cache, so that the processor can read the target data from the cache. At the same time, the controller can also send a second power supply control instruction to the power management unit. For example, the second power supply control instruction can be a request power off instruction or a low voltage maintenance instruction to put the flash memory into a low power consumption mode.

[0090] 706. The power management unit adjusts the power supply voltage to the flash memory according to the second power supply control instruction to make the flash memory enter a low power consumption mode.

[0091] For example, after receiving the second power supply control instruction sent by the controller, the power management unit adjusts the power supply voltage to the flash memory so that the flash memory enters a low power consumption mode. For example, the power management unit can control the power supply to the flash memory, and the power supply voltage is a preset voltage threshold, and the preset voltage threshold is lower than the working voltage of the flash memory, so that the flash memory is in a low voltage holding state, thereby reducing the overall power consumption of the chip reading operation. At the same time, the recovery time from the low voltage state to the working voltage is short, thereby improving the working efficiency of the chip. For another example, the power management unit can control not to supply power to the flash memory so that the flash memory is in a power-off state. Complete power off can greatly reduce its power consumption during the period when it is not accessed, thereby reducing the overall power consumption of the chip reading operation.

[0092] In the embodiment of the present application, when the target data is stored in the cache, the target data is directly read from the cache. At this time, the flash memory is in low power consumption mode. Only when the target data is not stored in the cache, the processor will obtain the target data from the flash memory through the controller, and control the flash memory from the low power consumption mode to the working mode through the power management unit, and after obtaining the target data from the flash memory, control the flash memory to enter the low power consumption mode through the power management unit, and the flash memory can be kept in the low power consumption mode most of the time. Therefore, the embodiment of the present application can reduce the overall power consumption of the chip read and write operations.

[0093] In the above embodiments, the description of each embodiment has its own emphasis. For the part that is not described in detail in a certain embodiment, please refer to the detailed description of the chip above, and will not be repeated here.

[0094] The chip control method provided in the embodiment of the present application belongs to the same concept as the chip in the above embodiment. Any method provided in the chip control method embodiment can be run on the chip. The specific implementation process of the chip control method is detailed in the chip embodiment and will not be repeated here.

[0095] The above is a detailed introduction to a chip and a control method provided in an embodiment of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A chip comprising a cache, a flash memory, a processor and a control module, wherein the cache or the flash memory is used to store target data, characterized in that: When the chip is in a preset clock mode, the processor is used to send a first read request for the target data, wherein the target data includes a first part stored in the cache and a second part stored in the flash memory; the cache being configured to send, according to the first read request, a second read request for a second portion of the target data to the control module after the processor obtains the first portion of the target data from the cache; The control module comprises: A controller, configured to send a first power supply control instruction according to the second read request; a power management unit, configured to control the flash memory to enter a working mode according to the first power supply control instruction, and send a read permission instruction to the controller; The controller is further configured to read a second portion of the target data from the flash memory according to the read permission instruction, and send a second power supply control instruction to the power management unit; The power management unit is further used to adjust the voltage of the flash memory to a preset voltage according to the second power supply control instruction, wherein the preset voltage is lower than the normal working voltage of the flash memory; The processor is further configured to synthesize the first part and the second part of the target data into the target data.

2. The chip according to claim 1, characterized in that: The cache, the flash memory and the processor are integrated into one module.

3. The chip according to claim 1, characterized in that: The cache and the processor are integrated in one module, and the flash memory is arranged outside the module.

4. The chip according to any one of claims 1 to 3, characterized in that: The cache is a cache memory or a buffer register.

5. A chip control method, applied to the chip according to any one of claims 1 to 4, characterized in that: The method comprises: When the chip is in a preset clock mode, the processor sends a first read request for the target data to the cache, wherein the target data includes a first portion stored in the cache and a second portion stored in the flash memory; After the processor obtains the first portion of the target data from the cache, the cache sends a second read request for the second portion of the target data to the control module; The controller sends a first power supply control instruction to the power management unit according to the second read request; The power management unit controls the flash memory to enter a working mode according to the first power supply control instruction, and sends a read permission instruction to the controller; The controller reads the second part of the target data from the flash memory according to the read permission instruction, and sends a second power supply control instruction to the power management unit; The power management unit adjusts the voltage of the flash memory to a preset voltage according to the second power supply control instruction, wherein the preset voltage is lower than a normal working voltage of the flash memory; The processor further combines the first portion and the second portion of the target data into the target data.

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