Highly adaptable signal transmission circuit

Abstract

The present invention relates to a highly adaptable signal transmission circuit. It includes a signal transmission circuit body, the signal transmission circuit body includes a PMOS tube P1 and a PMOS tube P2, the source end of the PMOS tube P1 receives an input signal A, the drain end of the PMOS tube P1 and the drain end of the PMOS tube PM2 are connected to each other to obtain a signal transmission output end, and an output signal Y is obtained through the signal transmission output end; the source end of the PMOS tube P2 receives an input signal B; and also includes a signal transmission control circuit, the input end of the signal transmission control circuit is connected to a control signal VIN, the signal transmission control circuit is also adaptively connected to the PMOS tube P1 and the PMOS tube P2, when the control signal VIN is at a high level, the signal transmission control circuit controls the PMOS tube P1 and the PMOS tube P2 to be in a shut-off state at the same time, so that the output signal Y of the signal transmission output end is in a floating state. The present invention can improve the adaptability of signal transmission and ensure the signal transmission reliability of the signal transmission circuit.

Description

Technical Field

[0001] The invention relates to a signal transmission circuit, in particular to a signal transmission circuit with high adaptability. Background Art

[0002] The signal transmission circuit specifically refers to a circuit capable of signal transmission. Generally, the signals to be transmitted by the signal transmission circuit include input signal A and input signal B, and the signal transmission state of the signal transmission circuit is controlled by the control signal VIN. Specifically, when the control signal VIN is at a high level, the output signal Y of the signal transmission circuit is in a floating state; when the control signal VIN is at a low level, the output signal Y of the signal transmission circuit follows the input signal A or the input signal B.

[0003] At present, it is found in the study of the working process of the signal transmission circuit that when the output signal Y of the signal transmission circuit needs to be in a floating state, the control signal VIN needs to be not only in a high level state, but also needs to make the maximum voltage of the control signal VIN greater than the input signal A or the input signal B. Otherwise, the output signal Y of the signal transmission circuit cannot be in a floating state. Therefore, the transmission characteristics of the existing signal transmission circuit have poor adaptability and are difficult to meet the needs of actual work. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a highly adaptable signal transmission circuit, which can improve the adaptability of signal transmission and ensure the signal transmission reliability of the signal transmission circuit.

[0005] According to the technical solution provided by the present invention, the highly adaptable signal transmission circuit includes a signal transmission circuit body, the signal transmission circuit body includes a PMOS tube P1 and a PMOS tube P2, the source end of the PMOS tube P1 receives an input signal A, the drain end of the PMOS tube P1 and the drain end of the PMOS tube PM2 are connected to each other to obtain a signal transmission output end, and an output signal Y is obtained through the signal transmission output end; the source end of the PMOS tube P2 receives an input signal B;

[0006] It also includes a signal transmission control circuit, the input end of which is connected to the control signal VIN. The signal transmission control circuit is also adaptively connected to the PMOS tube P1 and the PMOS tube P2. When the control signal VIN is at a high level, the signal transmission control circuit controls the PMOS tube P1 and the PMOS tube P2 to be in the off state at the same time, so that the output signal Y at the signal transmission output end is in a floating state.

[0007] The signal transmission control circuit includes a first signal transmission control subcircuit and a second signal transmission control subcircuit, wherein the corresponding input ends of the first signal transmission control subcircuit and the second signal transmission control subcircuit are both connected to the control signal VIN, the output end of the first signal transmission control subcircuit is connected to the gate end of the PMOS tube P1 and the source end of the PMOS tube P1, and the output end of the second signal transmission control subcircuit is connected to the gate end of the PMOS tube P2 and the source end of the PMOS tube P2.

[0008] The signal transmission control first sub-circuit includes an inverter INV2, an input end of the inverter INV2 is connected to the control signal VIN, an output end of the inverter INV2 is connected to the gate end of the PMOS tube P3, a drain end of the PMOS tube P3 is connected to the gate end of the PMOS tube P1, and a source end of the PMOS tube P3 is connected to the source end of the PMOS tube P1 through a resistor R7.

[0009] The signal transmission control second sub-circuit includes an inverter INV1, an input end of the inverter INV1 is connected to the control signal VIN, an output end of the inverter INV1 is connected to the gate end of the PMOS tube P4, a drain end of the PMOS tube P4 is connected to the gate end of the PMOS tube P2, and a source end of the PMOS tube P4 is connected to the source end of the PMOS tube P2 through a resistor R6.

[0010] The signal transmission circuit body further includes an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and an NMOS tube N4, wherein the gate end of the NMOS tube N1 is connected to the gate end of the NMOS tube N2, the drain end of the NMOS tube N1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to one end of the resistor R3, the resistor R7 and the source end of the PMOS tube P1;

[0011] The source terminal of the NMOS tube N1 is connected to the drain terminal of the NMOS tube N3, the gate terminal of the PMOS tube P1 and the drain terminal of the PMOS tube P3, and the gate terminal of the NMOS tube N3 is connected to the other end of the resistor R3; the drain terminal of the NMOS tube N3 is connected to the drain terminal of the NMOS tube N4, the input terminal of the inverter IN1, the input terminal of the inverter INV2 and one end of the resistor R5;

[0012] The drain terminal of the NMOS tube N4 is connected to the source terminal of the NMOS tube N2, the gate terminal of the PMOS tube P2 and the source terminal of the PMOS tube P4, the drain terminal of the NMOS tube N2 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R4, the resistor R6 and the source terminal of the PMOS tube P2, and the other end of the resistor R4 is connected to the gate terminal of the NMOS tube N4.

[0013] The advantages of the present invention are as follows: when the control signal VIN is at a low level, the output signal Y follows the input signal A or the input signal B; when the control signal VIN is at a high level, the first sub-circuit can be controlled by signal transmission to make the PMOS tube P1 in an off state, and the second sub-circuit can be controlled by signal transmission to make the PMOS tube P2 also in an off state. When both the PMOS tube P1 and the PMOS tube P2 are in an off state, the output signal Y is in a floating state. At this time, there is no need to consider the size relationship between the maximum level of the control signal VIN and the input signal A or the input signal B, thereby improving the adaptability of signal transmission and ensuring the signal transmission reliability of the signal transmission circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a circuit schematic diagram of the present invention. DETAILED DESCRIPTION

[0015] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0016] In order to improve the adaptability of signal transmission and ensure the signal transmission reliability of the signal transmission circuit, the present invention includes a signal transmission circuit body, the signal transmission circuit body includes a PMOS tube P1 and a PMOS tube P2, the source end of the PMOS tube P1 receives an input signal A, the drain end of the PMOS tube P1 and the drain end of the PMOS tube PM2 are connected to each other to obtain a signal transmission output end, and an output signal Y is obtained through the signal transmission output end; the source end of the PMOS tube P2 receives an input signal B;

[0017] It also includes a signal transmission control circuit, the input end of which is connected to the control signal VIN. The signal transmission control circuit is also adaptively connected to the PMOS tube P1 and the PMOS tube P2. When the control signal VIN is at a high level, the signal transmission control circuit controls the PMOS tube P1 and the PMOS tube P2 to be in the off state at the same time, so that the output signal Y at the signal transmission output end is in a floating state.

[0018] Specifically, the signal transmission circuit body can adopt the existing commonly used form, and the specific implementation of the signal transmission circuit can be selected according to needs, which will not be repeated here. Generally, the output stage of the signal transmission circuit includes a PMOS tube P1 and a PMOS tube P2, wherein the source terminal of the PMOS tube P1 is connected to the input signal A, and the source terminal of the PMOS tube P2 receives the input signal B. The specific conditions of the input signal A and the input signal B are consistent with the existing ones, and are well known to the personnel in this technical field, and will not be repeated here. The drain terminal of the PMOS tube P1 and the drain terminal of the PMOS tube P2 are interconnected to form the signal transmission output terminal of the entire signal transmission circuit body, that is, the output signal Y can be obtained through the signal transmission output terminal, and the specific conditions of obtaining the output signal Y are consistent with the existing ones, and are well known to the personnel in this technical field, and will not be repeated here.

[0019] When the output signal Y is required to be in a floating state, in order to ensure the reliability of the output signal Y in a floating state obtained through the signal transmission output end, in the embodiment of the present invention, a signal transmission control circuit is also included, wherein the signal transmission control circuit is controlled by the control signal VIN, and the signal transmission control circuit is adaptively connected to the PMOS tube P1 and the PMOS tube P2. In specific operation, when the control signal VIN is at a high level, the signal transmission control circuit controls the PMOS tube P1 and the PMOS tube P2 to be in a turned-off state at the same time. Since the PMOS tube P1 and the PMOS tube P2 are both in a turned-off state, the output signal Y at the signal transmission output end is in a floating state. Of course, when the control signal VIN is at a low level, the PMOS tube P1 and the PMOS tube P2 are both in a conducting state, and the output signal Y follows the input signal A or the input signal B, that is, when the control signal VIN is at a low level, the signal transmission control circuit will not affect the specific working mode of the signal transmission circuit body. At this time, the specific working mode of the signal transmission circuit body is consistent with the existing one, so as to meet the transmission needs of the input signal A or the input signal B.

[0020] Furthermore, the signal transmission control circuit includes a first signal transmission control sub-circuit and a second signal transmission control sub-circuit, wherein the corresponding input ends of the first signal transmission control sub-circuit and the second signal transmission control sub-circuit are both connected to the control signal VIN, the output end of the first signal transmission control sub-circuit is connected to the gate end of the PMOS tube P1 and the source end of the PMOS tube P1, and the output end of the second signal transmission control sub-circuit is connected to the gate end of the PMOS tube P2 and the source end of the PMOS tube P2.

[0021] In the embodiment of the present invention, the signal transmission control circuit includes a first signal transmission control subcircuit and a second signal transmission control subcircuit, that is, the first signal transmission control subcircuit is connected and coordinated with the PMOS tube P1, and the second signal transmission control subcircuit is connected and coordinated with the PMOS tube P2. The specific coordination manner between the first signal transmission control subcircuit and the PMOS tube P1 and the second signal transmission control subcircuit and the PMOS tube P2 is specifically described below.

[0022] like Figure 1 As shown, the signal transmission control first sub-circuit includes an inverter INV2, an input end of the inverter INV2 is connected to the control signal VIN, an output end of the inverter INV2 is connected to the gate end of the PMOS tube P3, a drain end of the PMOS tube P3 is connected to the gate end of the PMOS tube P1, and a source end of the PMOS tube P3 is connected to the source end of the PMOS tube P1 through a resistor R7.

[0023] At the same time, the signal transmission control second sub-circuit includes an inverter INV1, an input end of the inverter INV1 is connected to the control signal VIN, an output end of the inverter INV1 is connected to the gate end of the PMOS tube P4, a drain end of the PMOS tube P4 is connected to the gate end of the PMOS tube P2, and a source end of the PMOS tube P4 is connected to the source end of the PMOS tube P2 through a resistor R6.

[0024] In the embodiment of the present invention, when the control signal VIN is at a high level, the level loaded to the gate terminal of the PMOS tube P3 can be at a low level after the action of the inverter INV2, and at the same time, the level loaded to the gate terminal of the PMOS tube P4 can also be at a low level after the action of the inverter INV1; when the gate terminal is at a low level, the PMOS tube P3 and the PMOS tube P4 are in a conducting state at the same time.

[0025] When the PMOS tube P3 is in the on state, the voltage at the gate end of the PMOS tube P1 is consistent with the input signal A. At this time, according to the voltage relationship between the gate end of the PMOS tube P1 and the source end of the PMOS tube P1, the PMOS tube P1 is in the off state; at the same time, when the PMOS tube P4 is in the on state, the voltage at the gate end of the PMOS tube P2 is consistent with the input signal B, that is, the PMOS tube P2 is also in the off state. When both the PMOS tube P1 and the PMOS tube P2 are turned off, the output signal Y is in a floating state.

[0026] In specific implementation, when the control signal VIN is at a low level, the level of the gate terminal of the PMOS tube P3 is at a high level through the action of the inverter INV2, and at the same time, through the action of the inverter INV1, the level of the gate terminal of the PMOS tube P4 is also at a high level. At this time, it is known to those skilled in the art that the PMOS tube P3 and the PMOS tube P4 are both in the off state. When the PMOS tube P3 and the PMOS tube P4 are both in the off state, the working states of the PMOS tube P1 and the PMOS tube P2 are directly controlled by the control signal VIN, that is, the normal operation of the signal transmission circuit body will not be affected. At this time, the output signal Y follows the input signal A or the output signal B.

[0027] Furthermore, the signal transmission circuit body further includes an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and an NMOS tube N4, wherein the gate end of the NMOS tube N1 is connected to the gate end of the NMOS tube N2, the drain end of the NMOS tube N1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to one end of the resistor R3, the resistor R7 and the source end of the PMOS tube P1;

[0028] The source terminal of the NMOS tube N1 is connected to the drain terminal of the NMOS tube N3, the gate terminal of the PMOS tube P1 and the drain terminal of the PMOS tube P3, and the gate terminal of the NMOS tube N3 is connected to the other end of the resistor R3; the drain terminal of the NMOS tube N3 is connected to the drain terminal of the NMOS tube N4, the input terminal of the inverter IN1, the input terminal of the inverter INV2 and one end of the resistor R5;

[0029] The drain terminal of the NMOS tube N4 is connected to the source terminal of the NMOS tube N2, the gate terminal of the PMOS tube P2 and the source terminal of the PMOS tube P4, the drain terminal of the NMOS tube N2 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R4, the resistor R6 and the source terminal of the PMOS tube P2, and the other end of the resistor R4 is connected to the gate terminal of the NMOS tube N4.

[0030] In the embodiment of the present invention, NMOS tubes N1, NMOS tubes N2, NMOS tubes N3 and NMOS tubes N4 are connected and matched with PMOS tubes P1 and PMOS tubes P2 to form a required signal transmission circuit body; the other end of the resistor R5 is connected to the control signal VIN. Figure 1It can be seen that when the control signal VIN is at a low level, according to the NMOS characteristics: the NMOS tubes N1 and NMOS tubes N2 are in the off state, the NMOS tubes N3 and NMOS tubes N4 are turned on, and the low-level control signal VIN is loaded to the gate end of the PMOS tube P1. At this time, the PMOS tube P1 is in the on state; similarly, the low-level control signal VIN is loaded to the gate end of the PMOS tube P2, and the PMOS tube P2 is also in the on state, so that the state of the output signal Y follows the input signal A or the input signal B.

[0031] In summary, when the control signal VIN is at a low level, the output signal Y follows the input signal A or the input signal B; when the control signal VIN is at a high level, the first sub-circuit can be controlled by signal transmission to make the PMOS tube P1 in an off state, and the second sub-circuit can be controlled by signal transmission to make the PMOS tube P2 also in an off state. When both the PMOS tube P1 and the PMOS tube P2 are in the off state, the output signal Y is in a floating state. At this time, there is no need to consider the relationship between the maximum level of the control signal VIN and the input signal A or the input signal B, thereby improving the adaptability of signal transmission and ensuring the signal transmission reliability of the signal transmission circuit.

Claims

1. A highly adaptable signal transmission circuit, comprising a signal transmission circuit body, wherein the signal transmission circuit body comprises a PMOS tube P1 and a PMOS tube P2, wherein a source terminal of the PMOS tube P1 receives an input signal A, a drain terminal of the PMOS tube P1 and a drain terminal of the PMOS tube PM2 are connected to each other to obtain a signal transmission output terminal, and an output signal Y is obtained through the signal transmission output terminal; a source terminal of the PMOS tube P2 receives an input signal B; wherein: It also includes a signal transmission control circuit, the input end of the signal transmission control circuit is connected to the control signal VIN, and the signal transmission control circuit is also adaptively connected to the PMOS tube P1 and the PMOS tube P2. When the control signal VIN is at a high level, the signal transmission control circuit controls the PMOS tube P1 and the PMOS tube P2 to be in a turned-off state at the same time, so that the output signal Y at the signal transmission output end is in a floating state; The signal transmission control circuit includes a first signal transmission control subcircuit and a second signal transmission control subcircuit, wherein the corresponding input terminals of the first signal transmission control subcircuit and the second signal transmission control subcircuit are both connected to the control signal VIN, the output terminal of the first signal transmission control subcircuit is connected to the gate terminal of the PMOS tube P1 and the source terminal of the PMOS tube P1, and the output terminal of the second signal transmission control subcircuit is connected to the gate terminal of the PMOS tube P2 and the source terminal of the PMOS tube P2; The first signal transmission control subcircuit includes an inverter INV2, an input end of the inverter INV2 is connected to the control signal VIN, an output end of the inverter INV2 is connected to the gate end of the PMOS tube P3, a drain end of the PMOS tube P3 is connected to the gate end of the PMOS tube P1, and a source end of the PMOS tube P3 is connected to the source end of the PMOS tube P1 through a resistor R7; The signal transmission control second sub-circuit includes an inverter INV1, an input end of the inverter INV1 is connected to the control signal VIN, an output end of the inverter INV1 is connected to the gate end of the PMOS tube P4, a drain end of the PMOS tube P4 is connected to the gate end of the PMOS tube P2, and a source end of the PMOS tube P4 is connected to the source end of the PMOS tube P2 through a resistor R6.

2. The highly adaptable signal transmission circuit according to claim 1, characterized in that: The signal transmission circuit body further includes an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and an NMOS tube N4, wherein the gate end of the NMOS tube N1 is connected to the gate end of the NMOS tube N2, the drain end of the NMOS tube N1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to one end of the resistor R3, the resistor R7 and the source end of the PMOS tube P1; The source terminal of the NMOS tube N1 is connected to the drain terminal of the NMOS tube N3, the gate terminal of the PMOS tube P1 and the drain terminal of the PMOS tube P3, and the gate terminal of the NMOS tube N3 is connected to the other end of the resistor R3; the drain terminal of the NMOS tube N3 is connected to the drain terminal of the NMOS tube N4, the input terminal of the inverter IN1, the input terminal of the inverter INV2 and one end of the resistor R5; The drain terminal of the NMOS tube N4 is connected to the source terminal of the NMOS tube N2, the gate terminal of the PMOS tube P2 and the source terminal of the PMOS tube P4, the drain terminal of the NMOS tube N2 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R4, the resistor R6 and the source terminal of the PMOS tube P2, and the other end of the resistor R4 is connected to the gate terminal of the NMOS tube N4.

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