A multifunctional universal timing system based on standard 6U-VPX

Abstract

The invention discloses a multifunctional universal timing system based on standard 6U-VPX, comprising a front board and a rear board, which are connected via a backboard; the front board mainly comprises an embedded processor and an FPGA; the rear board comprises a high-precision satellite navigation timing and direction finding module, a Beidou short message module, a 1PPS+TOD output, a B code input and output, an NTP / PTP network port, a PTPE1 interface, a 10MHz output, an optical interface, an FPGA protocol conversion, an external clock input, etc. The invention provides a variety of high-precision timing functions and timekeeping functions such as BDS / GPS satellite navigation timing, network time protocol timing, high-precision time synchronization protocol timing, IRIG-B code timing, etc., and supports Beidou positioning, direction finding, short message communication, position reporting, etc.

Description

Technical Field

[0001] The invention relates to the field of satellite navigation timing, and in particular to a multifunctional universal timing system based on standard 6U-VPX. Background Art

[0002] Satellite navigation timing has many advantages such as high accuracy, wide coverage, all-day and all-weather, and is widely used in important fields such as electricity, finance, communications, and military. In complex environments such as aerospace and military communications, there is an increasing demand for the combination of master and slave, multiple timing methods, and timing and timekeeping. However, there is still a lack of corresponding equipment for multi-functional timing products that can flexibly meet different application scenarios. Summary of the invention

[0003] The purpose of the present invention is to solve the shortcomings in the prior art and to propose a multifunctional universal timing system based on standard 6U-VPX.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] A multifunctional universal timing system based on standard 6U-VPX comprises a front board and a rear board, the front board and the rear board perform signal conversion and transmission through a backboard, and the front board performs signal transmission with a front panel through RS232 and LAN; the characteristics are: the front board comprises an embedded processor and an FPGA, the FPGA provides a clock signal through a rubidium clock; the embedded processor and the FPGA perform bidirectional signal transmission; the rear board comprises a high-precision satellite navigation timing and direction finding module, a communication module, a clock isolation low-noise amplifier and an E1 interface waveform conversion interface, the high-precision satellite navigation timing and direction finding module outputs 1PPS and navigation telegrams to the front board FPGA through the backboard, the Beidou short message module interacts with the front board processor through the backboard, and the communication module is used for bidirectional signal transmission between the backboard and the rear panel.

[0006] A further improvement of the technical solution of the present invention is that: the front panel inputs information to the embedded processor through the RS232 interface and the LAN interface, and the embedded processor communicates bidirectionally with the backplane through the IPMB protocol, the SNMP protocol and the short message communication; the E1 interface waveform conversion interface converts the E1 signal of the rear plug-in board and transmits it to the PTP module of the FPGA; the Beidou short message module receives the Beidou short message information and sends it to the embedded processor for parsing and processing, and realizes the sending of the short message information through the antenna.

[0007] A further improvement of the technical solution of the present invention is that: the communication module includes two RS422s, a network port and an optical interface; one RS422 is used for unidirectional signal transmission of 1PPS+TDD information from the backplane to the rear panel, and the other RS422 is used for bidirectional transmission of B code between the backplane and the rear panel; the network port is used for bidirectional transmission of NTP / PTP messages between the backplane and the rear panel; the optical interface uses 1PPS+TOD converted by FPGA protocol for optical fiber timing.

[0008] The further improvement of the technical solution of the present invention is that: the FPGA includes a navigation message parsing module, a B code modulation and demodulation module, a time source selection module, an NTP module, a PTP module and a clock discipline and timekeeping module, the clock discipline and timekeeping module bidirectionally communicates with the rubidium clock 1PPS frequency, and the rubidium clock signal frequency is 10MHZ; the B code modulation and demodulation module receives and parses the external input B code, sends the obtained 1PPS+TOD to the time source selection module, and outputs the B code generated according to the clock discipline and timekeeping module information to the communication module interface in the rear plug-in board; the NTP module generates an NTP protocol message according to the 1PPS+TOD of the clock discipline and timekeeping module and sends it to the network port of the rear plug-in board; the PTP module receives the external PTP master clock message and parses it to obtain the 1PPS+TOD information, sends it to the time source selection module, and generates a PTP protocol message according to the 1PPS+TOD information of the timekeeping module and outputs it to the network port of the rear plug-in board, and the clock discipline and timekeeping module outputs a 10MHZ signal.

[0009] A further improvement of the technical solution of the present invention is that: the EMI bus is used for bidirectional signal transmission between the embedded processor and the FPGA, and the IPMB protocol is implemented by simulating two I2C buses of the embedded processor.

[0010] A further improvement of the technical solution of the present invention is that the time source selection module can set a manual / automatic time and frequency input source function, and the automatic setting is in accordance with the priority order of BDS / GPS, B code, PTP Ethernet, PTPE1 interface, internal frequency source and external frequency source.

[0011] A further improvement of the technical solution of the present invention is that the clock taming and punctuality module performs Kalman filtering on 1PPS according to 1PPS+TOD of the time source selection module, and then performs phase detection with 1PPS output by a high-stability rubidium clock, and tames the rubidium clock by combining the obtained phase difference with PID control.

[0012] Due to the adoption of the above technical solution, the technical progress achieved by the present invention is:

[0013] The FPGA processor has the characteristics of strong real-time performance, high control accuracy and high secondary development efficiency. The design of the plug-in board is conducive to system wiring and repair and replacement of damaged modules; RS422 and I2C buses make signal transmission efficient, and the rubidium clock provides a stable clock signal for the entire timing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a system structure diagram of the present invention. DETAILED DESCRIPTION

[0015] A multifunctional universal timing system based on standard 6U-VPX, comprising a front plug board and a rear plug board, the front plug board and the rear plug board perform signal conversion and transmission through a backboard, the front plug board performs signal transmission with the front panel through RS232 and LAN, the front panel inputs information to an embedded processor through an RS232 interface and a LAN interface, the embedded processor bidirectionally communicates with the backboard through an IPMB protocol and an SNMP protocol as well as short message communication, and the processed data of the rear plug board is output through the rear panel; the front plug board comprises an embedded processor and an FPGA, the FPGA provides a clock signal through a rubidium clock; the embedded processor and the FPGA perform bidirectional signal transmission; the rear plug board comprises a high-precision satellite navigation timing and direction finding module, a communication module, a clock isolation low noise amplifier and an E1 interface waveform conversion interface, the E1 interface waveform conversion interface performs signal conversion and transmission on the E1 signal of the rear plug board The PTP module for FPGA, the high-precision satellite navigation timing and direction finding module outputs 1PPS and navigation messages to the front-board FPGA through the backplane, the Beidou short message module interacts with the front-board processor through the backplane, the Beidou short message module receives the Beidou short message information and sends it to the embedded processor for parsing and processing, and sends the short message information through the antenna. The communication module is used for two-way signal transmission between the backplane and the rear panel, where the communication module includes two RS422, network port and optical interface; one RS422 is used for unidirectional signal transmission of 1PPS+TDD information from the backplane to the rear panel, and the other RS422 is used for bidirectional transmission of B code between the backplane and the rear panel; the network port is used for bidirectional transmission of NTP / PTP messages between the backplane and the rear panel; the optical interface uses 1PPS+TOD converted by FPGA protocol for optical fiber timing.

[0016] The FPGA in the system includes a navigation message parsing module, a B code modulation and demodulation module, a time source selection module, an NTP module, a PTP module and a clock discipline and punctuality module. The clock discipline and punctuality module communicates bidirectionally with the 1PPS frequency of the rubidium clock, and the clock signal frequency of the rubidium clock is 10MHZ; the B code modulation and demodulation module receives and parses the external input B code, sends the obtained 1PPS+TOD to the time source selection module, and outputs the B code generated according to the information of the clock discipline and punctuality module to the communication module interface in the rear plug-in board; the NTP module generates an NTP protocol message according to the 1PPS+TOD of the clock discipline and punctuality module and sends it to the network port of the rear plug-in board; the PTP module receives the external PTP master clock message and parses it to obtain the 1PPS+TOD information, sends it to the time source selection module, and generates a PTP protocol message according to the 1PPS+TOD information of the punctuality module and outputs it to the network port of the rear plug-in board, and the clock discipline and punctuality module outputs a 10MHZ signal. The time source selection module sets the time and frequency input source manually or automatically according to the parameter setting program of the embedded processor, and sends the selected time source 1PPS+TOD information to the clock discipline and punctuality module. When automatically set, it automatically selects according to the time source priority from high to low, and the default order is BDS / GPS, B code, PTP Ethernet, PTPE1 interface, internal frequency source, and external frequency source.

[0017] The clock taming and timekeeping module selects the 1PPS+TOD of the time source module, performs Kalman filtering on the 1PPS, and then performs phase discrimination with the 1PPS output by the high-stable rubidium clock. The obtained phase difference is combined with PID control to tame the high-stable rubidium clock. If there is no time source input, the timekeeping is performed, and the timekeeping accuracy is 120 minutes for taming, 72 hours and 25us. At the same time, the 1PPS output by the high-stable rubidium clock is combined with the TOD information and sent to each external timing unit, and the 10MHz signal of the high-stable rubidium clock is sent to the rear plug-in board through the backplane for external output.

[0018] When working, the specific signal transmission mode in the system is: one 1PPS+TOD signal is sent to the 422 interface of the rear plug-in board through the backplane for external 1PPS+TOD timing, one 1PPS+TOD signal is sent to the B code encoding and decoding module for B code encoding, and sent to the 422 interface of the rear plug-in board through the backplane for external B code timing, one 1PPS+TOD signal is sent to the NTP module to generate NTP message, and sent to the rear plug-in network port through the backplane for external NTP timing, one 1PPS+TOD signal is sent to the PTP module to generate PTP message, and sent to the rear plug-in network port through the backplane for external PTP timing, and at the same time, the PTPE1 signal is generated through the E1 conversion circuit for external PTP timing, and one 1PPS+TOD signal is sent to the NTP module to generate NTP message, and sent to the rear plug-in network port through the backplane for external PTP timing. The protocol is converted to the FPGA of the rear plug-in board, and then sent out through the optical module for external optical fiber timing. A 10MHz signal is transmitted to the rear plug-in board through the backplane for clock isolation and low-noise amplifier before external output; the Beidou short message module receives the RDSS information and sends it to the embedded processor of the front plug-in board through the backplane. The embedded processor parses the Beidou short message and sends it to other units through the backplane. The embedded processor converts the short message to be sent, generates a Beidou short message command and sends it to the Beidou short message module, which is sent out through the antenna; the embedded processor runs the management service program and the SNMP agent program, which can configure the timing parameters through the network and SNMP, and send the configuration data to the FPGA through the EMI bus. The embedded processor implements IPMB through two I2Cs to report and control the health status of the board.

[0019] Embodiment 1

[0020] The timing reference sources of this system can include BDS / GPS, B code, PTP Ethernet, PTPE1 interface, internal frequency source, and external frequency source. The external timing modes of this system include 1PPS+TOD, B code, NTP, PTP, etc. The high-precision satellite navigation timing and direction finding module receives GPS or Beidou signals, outputs positioning, direction finding and timing information, and sends it to the embedded processor and FPGA of the front board through the backplane. The embedded processor will parse the positioning and direction finding information and transmit it to other functional boards through the backplane. The FPGA obtains the time information through the navigation message parsing module and sends 1PPS+TOD to the time source selection module; the B code signal input by the rear board is transmitted to the B code encoding and decoding module of the FPGA through the backplane, and the 1PPS+TOD information is parsed and transmitted to the time source selection module.

[0021] The PTP timing information input from the network port of the rear board is transmitted to the PTP module of the FPGA through the backplane, and 1PPS+TOD is parsed out to the time source selection module. The PTP E1 timing signal input from the E1 interface of the rear board is transmitted to the E1 signal conversion circuit of the front board through the backplane for signal conversion, and then sent to the PTP module of the FPGA to parse 1PPS+TOD to the time source selection module.

[0022] The time source selection module sets the time and frequency input source manually or automatically according to the parameter setting program of the embedded processor, and sends the selected time source 1PPS+TOD information to the clock discipline and punctuality module. When automatically set, it automatically selects according to the time source priority from high to low, and the default order is BDS / GPS, B code, PTP Ethernet, PTPE1 interface, internal frequency source, and external frequency source.

[0023] The clock taming and timekeeping module selects the 1PPS+TOD of the time source module, performs Kalman filtering on the 1PPS, and then performs phase discrimination with the 1PPS output by the high-stable rubidium clock. The obtained phase difference is combined with PID control to tame the high-stable rubidium clock. If there is no time source input, the timekeeping is performed, and the timekeeping accuracy is 120 minutes for taming, 72 hours and 25us. At the same time, the 1PPS output by the high-stable rubidium clock is combined with the TOD information and sent to each external timing unit, and the 10MHz signal of the high-stable rubidium clock is sent to the rear plug-in board through the backplane for external output.

[0024] One 1PPS+TOD signal is sent to the 422 interface of the rear board through the backplane for external 1PPS+TOD timing. One 1PPS+TOD signal is sent to the B code encoding and decoding module for B code encoding, and is sent to the 422 interface of the rear board through the backplane for external B code timing. One 1PPS+TOD signal is sent to the NTP module to generate an NTP message, which is sent to the network port of the rear board through the backplane for external NTP timing. One 1PPS+TOD signal is sent to the PTP module to generate a PTP message, which is sent to the network port of the rear board through the backplane for external PTP timing. At the same time, a PTP E1 signal is generated through the E1 conversion circuit for external PTP timing. One 1PPS+TOD signal is sent to the FPGA of the rear board for protocol conversion, and then sent out through the optical module for external optical fiber timing. One 10MHz signal is transmitted to the rear board through the backplane for clock isolation and low-noise amplifier before external output.

[0025] The Beidou short message module receives RDSS information and sends it to the embedded processor of the front board through the backplane. The embedded processor parses the Beidou short message and sends it to other units through the backplane. The embedded processor converts the short message to be sent, generates a Beidou short message command and sends it to the Beidou short message module, which is then sent out through the antenna.

[0026] The embedded processor runs the management service program and SNMP agent program, which can configure the timing parameters through the network and SNMP, and send the configuration data to the FPGA through the EMI bus. The embedded processor implements IPMB through two I2C channels to report and control the health status of the board.

[0027] Functional indicators achieved by the present invention:

[0028] 1. The system has positioning function, including BDSB1 / B2 / B3C code positioning function and GPSL1 / L2 / L5 positioning function;

[0029] 2. With direction finding function;

[0030] 3. With 1PPS+TOD timing function;

[0031] 4. With NTP, PTP (1588V2) network timing function, PTP supports external network port and E1 interface, and PTP master / slave timing can be configured through SNMP protocol;

[0032] 5. With B code output timing function;

[0033] 6. With B code input timing function;

[0034] 7. With clock input and output functions;

[0035] 8. Equipped with Beidou short message communication function.

[0036] The performance indicators achieved by the present invention are:

[0037] 1. Positioning accuracy: horizontal ≤10m, vertical ≤10m;

[0038] 2. Speed ​​accuracy: ≤0.2m / s;

[0039] 3. Direction finding sensitivity: 0.2°, information update frequency 10Hz, 20Hz adjustable;

[0040] 4.1PPS output: 100Ω impedance, positive polarity; the punctual point is the signal front edge; pulse width 100ms, rising edge time ≤20ns, jitter ≤50ns, the output condition is that no signal is sent before the synchronization satellite, and the output is maintained after the satellite is lost after synchronization. The internal chassis is MLVDS level, and the rear plug board is RS422 level;

[0041] 5.TOD output: MLVDS level inside the chassis, 422 level on the backplane, 100Ω impedance;

[0042] 6. B code input and output: timing accuracy ≤1us, interface complies with GJB2291A-2008 standard, locking external reference B code time ≤5s, chassis internal backplane output is MLVDS level, rear board input and output is 422 level;

[0043] 7.NTP timing indicators: timing accuracy is better than 100us, NTP load is 1000 times / second, the interface is external network port and backplane interface;

[0044] 8.PTP timing indicators: The timing accuracy is better than 100ns. After 2-level switching (switch that does not support 1588 protocol), the timing accuracy is better than 100us. The interface supports external network port and E1 interface. The PTP load is more than 100 clients @ 8 messages / second.

[0045] 9. Timekeeping accuracy: 120 minutes, 72 hours 25us;

[0046] 10. The success rate of Beidou short message communication is greater than 90%. Polarization mode: S is right-hand circular polarization and L is left-hand circular polarization.

Claims

1. A multifunctional universal timing system based on standard 6U-VPX, comprising a front board and a rear board, wherein the front board and the rear board perform signal conversion and transmission via a backboard, and the front board performs signal transmission with a front panel via RS232 and LAN; characterized in that: The front board includes an embedded processor and an FPGA, and the FPGA provides a clock signal through a rubidium clock; the embedded processor and the FPGA perform bidirectional signal transmission; the rear board includes a high-precision satellite navigation timing and direction finding module, a communication module, a clock isolation low-noise amplifier, and an E1 interface waveform conversion interface. The high-precision satellite navigation timing and direction finding module outputs 1PPS and navigation messages to the front board FPGA through the backplane, and the Beidou short message module interacts with the front processor through the backplane. The communication module is used for bidirectional signal transmission between the backplane and the rear panel; The front panel inputs information to the embedded processor through the RS232 interface and the LAN interface, and the embedded processor communicates with the backplane bidirectionally through the IPMB protocol, the SNMP protocol and the short message communication; the E1 interface waveform conversion interface converts the E1 signal of the rear plug-in board and transmits it to the PTP module of the FPGA; the Beidou short message module receives the Beidou short message information and sends it to the embedded processor for analysis and processing, and realizes the sending of short message information through the antenna; The communication module includes two RS422s, a network port and an optical interface; one RS422 is used to transmit 1PPS+TDD information from the backplane to the rear panel in a one-way signal, and the other RS422 is used to perform bidirectional transmission of B code between the backplane and the rear panel; the network port is used to perform bidirectional transmission of NTP / PTP messages between the backplane and the rear panel; the optical interface uses the 1PPS+TOD converted by the FPGA protocol for optical fiber timing; The FPGA includes a navigation message parsing module, a B code modulation and demodulation module, a time source selection module, an NTP module, a PTP module and a clock discipline and timekeeping module. The clock discipline and timekeeping module communicates bidirectionally with the 1PPS frequency of the rubidium clock, and the clock signal frequency of the rubidium clock is 10MHZ; the B code modulation and demodulation module receives and parses the externally input B code, sends the obtained 1PPS+TOD to the time source selection module, and outputs the B code generated according to the information of the clock discipline and timekeeping module to the communication module interface in the rear plug-in board; the NTP module generates an NTP protocol message according to the 1PPS+TOD of the clock discipline and timekeeping module and sends it to the network port of the rear plug-in board; the PTP module receives the external PTP master clock message and parses it to obtain the 1PPS+TOD information, sends it to the time source selection module, and generates a PTP protocol message according to the 1PPS+TOD information of the timekeeping module and outputs it to the network port of the rear plug-in board, and the clock discipline and timekeeping module outputs a 10MHZ signal.

2. A multifunctional universal timing system based on standard 6U-VPX according to claim 1, characterized in that : The embedded processor and FPGA use EMI bus for bidirectional signal transmission, and the IPMB protocol is implemented by simulating two I2C buses of the embedded processor.

3. A multifunctional universal timing system based on standard 6U-VPX according to claim 1, characterized in that :The time source selection module can set the manual / automatic time and frequency input source function, and the automatic setting is based on the priority order of BDS / GPS, B code, PTP Ethernet, PTPE1 interface, internal frequency source and external frequency source.

4. A multifunctional universal timing system based on standard 6U-VPX according to claim 1, characterized in that The clock taming and punctuality module performs Kalman filtering on 1PPS according to 1PPS+TOD of the time source selection module, and then performs phase detection with 1PPS output by a high-stability rubidium clock, and tames the rubidium clock by combining the obtained phase difference with PID control.

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