A three-dimensional integrated structure, preparation and assembly method

Abstract

The present invention provides a three-dimensional integrated structure, preparation and assembly method, which can achieve miniaturization, improve integration, good mechanical stability, wide application range and high efficiency and low cost. It includes two sub-silicon substrates, one end of each sub-silicon substrate is provided with a fork finger structure; the fork finger structure includes a plurality of forks, each fork finger includes a fork finger head and a fork finger neck, one end of the fork finger neck is fixedly connected to one end of the fork finger head, the width of the fork finger head is greater than the width of the fork finger neck, the fork finger neck on one sub-silicon substrate and the fork finger head on another sub-silicon substrate are staggered and arranged to form a fork finger hinge structure; it also includes a support positioning structure, the support positioning structure includes a plurality of support positioning columns, one end of the sub-silicon substrate is provided with the fork finger structure and is arranged one by one to form two rows of support positioning column rows, the top of the support positioning column is provided with a welding cap, and in the folded state, the welding caps at the top of the corresponding support positioning columns are welded together to form welding points.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design and manufacturing and advanced packaging technology, and specifically relates to a three-dimensional integrated structure, preparation and assembly method. Background Art

[0002] At present, in two-dimensional multi-chip packaging, and three-dimensional multi-chip packaging of multi-chip stacking and package substrate stacking (PoP), the normal directions of multiple chip surfaces are the same or opposite, that is, the surfaces of each chip are generally parallel to each other, and then the surfaces of the package substrate carrying these chips are usually parallel to each other. However, for some sensor systems, in order to perform three-dimensional measurements, a three-axis sensor composed of three mutually orthogonal sensitive axes is required. For example, a nine-axis inertial measurement sensor used for guidance, navigation and control of a moving body needs to include a three-axis gyroscope, a three-axis acceleration sensor and a three-axis magnetic induction sensor (magnetometer) to measure important information such as acceleration, angular velocity, and posture of the moving body. At this time, it is necessary to make the normals of the three single-axis sensor chip surfaces mutually orthogonal to form a three-axis sensor. Since the surface of the package substrate carrying the chip is usually parallel to the surface of the chip carried, the problem of mutually perpendicular orthogonal between the chip surfaces can also be converted into the problem of mutually perpendicular orthogonal between the substrate surfaces.

[0003] In the Chinese patent "MEMS Navigation System Electronic Circuit Configuration" (patent application number 201410502611.6), three rigid circuit boards are used as X-axis, Y-axis and Z-axis sensor boards respectively. The three rigid circuit boards are interconnected by flexible cables. When installing, the three rigid circuit boards are fixed to three adjacent faces of a hexahedral bracket so that the three rigid circuit boards are perpendicular to each other. The three rigid circuit boards are respectively installed with inertial sensors. There are also flexible circuit boards that replace the flexible cables in the above patents to form a rigid-flexible hybrid circuit board. Finally, the three rigid circuit boards are respectively mounted on the three adjacent inner walls of the rectangular metal tube shell, and the sensor surface is mounted on the rigid circuit board to form a mutually perpendicular relationship. However, this method based on the installation of the rigid circuit board on a third-party orthogonal surface to achieve the orthogonality of the surface mounted sensors thereon has the disadvantages of low integration and large volume, which cannot meet the needs of miniaturized applications. The U.S. patents "THREE DIMENSIONAL FOLDED MEMS TECHNOLOGY FORMULTI-AXIS SENSOR SYSTEMS" (patent number US8368145 B2) and "THROUGH-WAFER INTERCONNECTSFOR MEMS DOUBLE-SIDED FABRICATION PROCESS (TWIDS)" (patent publication number US2016 / 0167958A1) disclose a three-dimensional foldable MEMS technology for a multi-axis sensor system. In this patent, different sensor monoliths and foldable structures, i.e., flexible and bendable hinges made of insulating materials, are integrated on the device layer (top silicon layer) of the same substrate. However, this technology requires that the preparation processes of the integrated sensors are the same or compatible, which severely limits the types and structures of sensors that can be integrated. In addition, from the implementation point of view, this technology is difficult to implement, and different sensor processes need to be compatible, which inevitably requires A compromise in process solutions must be made, and the optimal process cannot be achieved for each sensor, resulting in performance loss of a single sensor; in addition, the applicability of the vertical conductive interconnect hole structure described in the patent is very limited, and the vertical conductive interconnection function cannot be achieved for devices in which the electrodes prepared on the substrate are on the front side (upper surface) of the substrate; furthermore, the flexible and easy-to-bend hinges used in the patent are still flexible after the adjacent chips are bent and formed, and lack a rigid hard connection, and cannot limit the lateral relative movement of adjacent chips. The relative positions of adjacent chips will move or vibrate with external forces, which has a great impact on the measurement accuracy of the sensor. Summary of the invention

[0004] In order to solve the problems existing in the prior art, the present invention provides a three-dimensional integrated structure, preparation and assembly method, which can achieve miniaturization, improve integration, have good mechanical stability, a wide range of applications, and high efficiency and low cost.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A three-dimensional integrated structure includes two sub-silicon substrates, one end of each sub-silicon substrate is provided with an interdigital structure;

[0007] The interdigital structure comprises a plurality of interdigital fingers, each interdigital finger comprises a interdigital head and an interdigital neck, one end of the interdigital neck is fixedly connected to one end of the interdigital head, the width of the interdigital head is greater than the width of the interdigital neck, and the interdigital necks on one sub-silicon substrate and the interdigital heads on another sub-silicon substrate are arranged in an interdigital hinge structure in an interdigital manner;

[0008] It also includes a support positioning structure, the support positioning structure includes a plurality of support positioning columns, and two rows of support positioning columns are arranged one by one along one end of the sub-silicon substrate provided with the interdigital structure, and the top of the support positioning column is provided with a welding cap;

[0009] When the two sub-silicon substrates are folded along the interdigitated hinge structure, the welding caps at the top of the corresponding supporting positioning columns are welded together to form welding points, which are used to fix the relative positions of the two sub-silicon substrates and provide electrical connection between the two sub-silicon substrates.

[0010] Preferably, there are gaps between adjacent interdigits; and the distance between two adjacent interdigit heads on the same silicon substrate is greater than the width of the interdigit neck and less than the width of the interdigit head.

[0011] Preferably, the supporting and positioning columns are perpendicular to the surface of the silicon substrate, and the supporting and positioning column row is parallel to the interdigital hinge structure;

[0012] When the two sub-silicon substrates are in a folded state along the interdigitated hinge structure, the welding caps at the top ends of the two rows of corresponding support and positioning columns are in contact or close to each other.

[0013] Preferably, the shape of the forked fingers is rectangular, polygonal or circular.

[0014] Preferably, it also includes a flexible structure, and the flexible structure and the interdigital hinge structure are arranged alternately or the flexible structure is arranged along the folded edges of the two sub-silicon substrates.

[0015] Preferably, the flexible structure is connected to the metal redistribution layer on the lower surface of the silicon substrate, or is a part of the second metal redistribution layer and the fourth metal redistribution layer, or is a multilayer dielectric film composed of the metal interlayer dielectric in the second metal redistribution layer and the fourth metal redistribution layer, or is an organic film layer independent of the second metal redistribution layer and the fourth metal redistribution layer.

[0016] Preferably, the supporting positioning pillars and the flexible structure are respectively arranged on two opposite surfaces of a sub-silicon substrate.

[0017] A method for preparing a silicon substrate wafer with a three-dimensional integrated structure comprises the following steps:

[0018] A conductive blind hole embedded in the silicon substrate and having an axial direction perpendicular to the surface of the silicon substrate is prepared from one surface of the silicon substrate;

[0019] A multi-layer metal wiring layer electrically connected to the conductive blind hole is prepared on the opening surface of the conductive blind hole of the silicon substrate, and a pad or bump located on the top of the multi-layer metal wiring layer;

[0020] Temporarily bonding the completed wiring surface of the silicon substrate to the carrier board;

[0021] The bottom of the conductive blind hole filling material is exposed to form a TSV conductive through hole;

[0022] Prepare a multi-layer metal wiring layer connected to the bottom of the TSV conductive through hole, a pad or bump located on the top of the multi-layer metal wiring layer, and a support positioning column located on the opposite side edge of the multi-layer metal wiring layer;

[0023] The surface of the silicon substrate wafer is coated with photoresist, a top view of the interdigitated hinge is photoetched, and dry etching is performed until the silicon substrate is etched through, thereby completing the preparation of the interdigitated hinge structure formed by the interdigitated hinges;

[0024] After debonding, the carrier is removed to complete the preparation of the three-dimensional integrated silicon substrate wafer.

[0025] A method for assembling a three-dimensional integrated structure, comprising:

[0026] Assembling chips on the upper and lower surfaces of the prepared three-dimensional integrated structure silicon substrate;

[0027] Slicing and separating the two sub-silicon substrates, and folding the two sub-silicon substrates along the interdigitated hinge structure until the top ends of the corresponding support positioning pillars are in contact or close to each other;

[0028] The welding caps at the top ends of the corresponding supporting positioning columns are welded together to form welding points, thereby completing the assembly of a three-dimensional integrated structure.

[0029] Preferably, after the assembly is completed, reinforcing glue is applied to the outer corners of the interdigitated structures on the two sub-silicon substrates.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] The present invention realizes the movement and rotation of the relative positions of the space between the loaded chips through the spatial folding of the silicon substrate, so that the relative angle of the normal lines of the multi-chip surfaces meets the application requirements, including etching the opposite ends of the two sub-silicon substrates into self-locking interdigital structures, the rows of interdigital structures forming interdigital hinge structures, and the interdigital hinge structures serving as rotatable movable parts during the relative folding of the two sub-silicon substrates; and also including two rows of support positioning column row structures located on both sides of the interdigital hinge structures, the multiple support positioning columns in the two rows are arranged one by one, and when the two sub-silicon substrates are relatively folded to the final position, the welding caps at the top ends of the two corresponding support positioning columns are connected. The two sub-silicon substrates are touched or brought close to each other, and after remelting and welding, the relative positions of the two sub-silicon substrates are fixed to form a three-dimensional integrated structure. The fork-finger hinge structure with a self-locking function makes the relative movement distance between the two sub-silicon substrates in the horizontal plane very limited, which is beneficial when the silicon substrate is folded through the fork-finger hinge. The corresponding supporting positioning columns can be automatically aligned and welded to achieve micro-miniaturization and good mechanical stability. On the other hand, unless the two sub-silicon substrates move relative to each other in the vertical direction, they will not separate, so that after the silicon substrate is diced, the two sub-silicon substrates will not be easily separated, reducing the difficulty of three-dimensional assembly and low technical difficulty.

[0032] Furthermore, there are gaps between adjacent fingers. By controlling the spacing between the finger heads and finger necks in a pair of finger rows and the etched gaps between the opposite finger necks and finger heads, the lateral position offset of the two sub-silicon substrates when they are relatively rotated and folded can be controlled. At the same time, since silicon is a rigid material and has a thickness greater than 100μm, the finger hinge structure in the junction area of ​​the silicon substrates will not be deformed when the two sub-silicon substrates are relatively rotated and folded.

[0033] Furthermore, the distance between two adjacent fork fingers on the same sub-silicon substrate is greater than the width of the fork neck and less than the width of the fork finger, so that the two sub-silicon substrates can be locked with each other in the plane direction of the silicon substrate. Although they can be relatively rotated and folded, they will not easily detach, thereby achieving better mechanical stability.

[0034] The present invention can adopt secondary integration of finished chips. For finished chips, the finished chips can be tested first to determine whether they are qualified, and then the qualified finished chips are integrated on the silicon substrate. Unqualified finished chips can be eliminated in advance. Compared with monolithic integration, the influence of the preparation yield of the finished chips themselves on the integration yield is reduced, which is efficient and low-cost.

[0035] Furthermore, the ability to load chips on both the upper and lower surfaces of the silicon substrate improves the integration of multi-chip integration on the one hand, and on the other hand, due to the short interconnection length of the TSV holes, small delay and small interconnection loss, it is beneficial to ensure high-speed interconnection between the chips on the upper and lower surfaces of the silicon substrate, reduce power consumption and improve integration performance.

[0036] Furthermore, after assembly is completed, reinforcing glue is applied at the outer angles of the two rows of interdigitated hinges, which can provide the three-dimensional integrated structure with high overload resistance. The periodically crossed interdigitated hinge structure increases the contact area between the silicon material and the reinforcing glue, thereby improving the reinforcement efficiency.

[0037] In the present invention, except for the steps of spatial folding of the silicon substrate, contact welding of the supporting positioning pillars and hinge reinforcement, which are single-component operations, the rest are silicon substrate preparation, and process steps such as micro-assembly of multiple chips on the silicon substrate are all whole-wafer operations, with high yield and conducive to reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a partial top view of the three-dimensional integrated silicon substrate in Example 1 of the present invention (before wafer dicing);

[0039] Figure 2 It is a partial top view of the three-dimensional integrated silicon substrate in Example 1 of the present invention (after wafer dicing);

[0040] Figure 3 For the present invention Figure 2 Schematic diagram of the structure of the AA' section;

[0041] FIG. 4A to FIG. 4E This is a process flow chart of preparing a three-dimensional integrated silicon substrate wafer in Example 1 of the present invention;

[0042] FIG. 5A to FIG. 5D This is a process flow chart of three-dimensional integrated silicon substrate micro-assembly in Example 1 of the present invention;

[0043] Figure 6 It is a partial top view of the three-dimensional integrated silicon substrate in Example 2 of the present invention (before wafer dicing);

[0044] Figure 7 For the present invention Figure 6 Schematic diagram of the structure of the middle BB' section;

[0045] Figure 8 It is a partial schematic diagram of the three-dimensional integrated silicon substrate after folding and bonding in Example 2 of the present invention;

[0046] Fig. 9 This is a partial enlarged view of the three-dimensional integrated interdigital structure of the present invention;

[0047] Fig.10 It is a flowchart of a three-dimensional integrated structure silicon substrate wafer preparation process in a specific embodiment of the present invention;

[0048] Fig.11 It is a flowchart of the assembly process of the three-dimensional integrated structure of the present invention.

[0049] In the figure, silicon substrate 1, first substrate 1a, second substrate 1b, fork 2, fork neck 20, fork head 200, flexible strip 3, support positioning column 4, support positioning column body 40, solder joint 9, solder cap 10, first metal rewiring layer 5a, second metal rewiring layer 7a, third metal rewiring layer 5b, fourth metal rewiring layer 7b, TSV conductive through hole 6, conductive blind hole 60, carrier 8, chips 11-15. DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention; the following embodiments are only embodiments of a part of the present invention, rather than all embodiments, and are not intended to limit the scope of the present invention.

[0051] The present invention discloses a three-dimensional integrated structure, comprising two silicon sub-substrates, namely a first substrate 1a and a second substrate 1b, wherein one end of each silicon sub-substrates is provided with an interdigital structure; the interdigital structure comprises a plurality of interdigits 2, such as Fig. 9 As shown, each fork finger 2 includes a fork finger head 200 and a fork finger neck 20, one end of the fork finger neck 20 is fixedly connected to one end of the fork finger head 200, the width of the fork finger head 200 is greater than the width of the fork finger neck 20, and the fork finger neck 20 on one sub-silicon substrate and the fork finger head 200 on another sub-silicon substrate are staggered and arranged to form a fork finger hinge structure; it also includes a support positioning structure, the support positioning structure includes a plurality of support positioning columns 4, one end of the sub-silicon substrate provided with the fork finger structure is arranged one by one at intervals to form two rows of support positioning column rows, and the top of the support positioning column 4 is provided with a welding cap 10;

[0052] The two sub-silicon substrates (i.e., the first substrate 1a and the second substrate 1b) are folded along the interdigitated hinge structure, and the corresponding welding caps 10 at the top of the supporting positioning columns 4 are welded together to form welding points 9, thereby fixing the relative positions of the two sub-silicon substrates (i.e., the first substrate 1a and the second substrate 1b) and providing electrical connections between the two sub-silicon substrates (i.e., the first substrate 1a and the second substrate 1b).

[0053] The interdigital hinge structure of the present invention has a self-locking function, and there is a gap between adjacent interdigits 2; the interdigit heads 200 are relatively large in size, and the interdigit necks 20 are slender. The distance between two adjacent interdigit heads 200 on the same silicon substrate is greater than the width of the interdigit necks 20 and less than the width of the interdigit heads 200. Adjacent interdigit necks 20 clamp the interdigit heads 200 of the opposite interdigits 2, and adjacent interdigit heads 200 clamp the interdigit necks 20 of the opposite interdigits 2, and they are locked with each other.

[0054] Furthermore, the shape of the interdigital head 200 can be rectangular, polygonal, or circular, but is not limited thereto.

[0055] Furthermore, the row of supporting and positioning columns is parallel to the interdigitated hinge structure, which can ensure that each group of corresponding supporting and positioning columns 4 can be in contact or approximately in contact with each other at the same time, so as to ensure the normal progress of subsequent welding and fixation and achieve mechanical stability.

[0056] Furthermore, a first metal rewiring layer 5a is laid on the upper surface of the first substrate 1a, a second metal rewiring layer 7a is laid on the lower surface of the first substrate 1a, a third metal rewiring layer 5b is laid on the upper surface of the second substrate 1b, and a fourth metal rewiring layer 7b is laid on the lower surface of the second substrate 1b.

[0057] Furthermore, the two rows of support and positioning columns of the present invention are electrically interconnected through the first metal rewiring layer 5a and the third metal rewiring layer 5b and the TSV conductive via 6, and the second metal rewiring layer 7a and the electrically connected fourth metal rewiring layer 7b. At least one chip is assembled on the first substrate 1a, and at least one chip is assembled on the second substrate 1b. The chip on the first substrate 1a and the chip on the second substrate 1b are electrically interconnected through welding between the welding caps 10 of the support and positioning columns 4.

[0058] The present invention realizes the movement and rotation of the spatial relative positions between the chips loaded thereon by spatial folding of the silicon substrate 1, so that the relative angles of the normal lines of the multi-chip surfaces meet the application requirements, including etching one end of two sub-silicon substrates 1a and 1b into self-locking fork finger 2 structures, and the rows of fork finger 2 structures constitute a fork finger hinge structure, and the fork finger hinge structure serves as a rotatable movable part during the relative folding process of the first substrate 1a and the second substrate 1b; and two rows of support positioning column row structures located on both sides of the fork finger hinge structure, and the multiple support positioning columns 4 in the two rows are arranged in a one-to-one correspondence. When the first substrate 1a and the second substrate 1b are folded to the final position relative to each other, the welding caps 10 at the top ends of the two rows of corresponding support positioning columns 4 are in contact or approximately in contact, that is, close to each other, and after remelting and welding, the relative positions of the first substrate 1a and the second substrate 1b are fixed to form a three-dimensional integrated structure; wherein the head of the fork finger 2 is in the shape of a large rectangular disk, and the neck of the fork finger 2 is thinner. In two adjacent fingers 2 in the same row connected to the same sub-silicon substrate, the finger neck 20 clamps the finger head 200 of the finger 2 connected to the corresponding sub-silicon substrate, and the finger head 200 clamps the finger neck 20 of the finger 2 connected to the corresponding sub-silicon substrate, that is, in a pair of fingers 2, the adjacent finger necks 20 clamp the finger heads 200 of the opposite fingers 2, and the adjacent finger heads 200 clamp the finger necks 20 of the opposite fingers 2, which are locked with each other to form a self-locking finger hinge structure. The finger hinge structure with a self-locking function, on the one hand, makes the relative movement distance between the first substrate 1a and the second substrate 1b in the horizontal plane very limited, which is conducive to the automatic alignment of the corresponding supporting positioning columns 4 when the silicon substrate 1 is folded through the finger hinge. On the other hand, unless the first substrate 1a and the second substrate 1b move relative to each other in the vertical direction, they will not be separated, so that after the silicon substrate 1 is diced, the first substrate 1a and the second substrate 1b will not be easily separated, reducing the difficulty of three-dimensional assembly.

[0059] The present invention has universal applicability to finished chips made of different materials and different processes. There are no special requirements for the process used by the chip itself, and the chip process is not required to be the same or similar, and the chip process is not required to be compatible. It can be a sensor chip, a digital chip, an analog chip, a radio frequency chip, a passive integrated chip, etc. of different processes, but not limited to this; there are no special requirements for the material of the chip itself, which can be silicon, GaAs, InP, SiC, GaN, Ge, GeSi, aluminum niobate, glass, ceramics and other materials, but not limited to this; the upper and lower surfaces of the silicon substrate 1 can be mounted with chips, and there are no special requirements for the external pin form of the chip, which can be wire bonding or micro-bump array bonding, but not limited to this; there are no special requirements for the size of the chip. Different chips can choose the best process according to their own characteristics to achieve the best performance and cost performance. At the same time, the present invention can adopt secondary integration of finished chips. For finished chips, the finished chips can be tested first to determine whether the finished chips are qualified, and then the qualified finished chips are integrated on the silicon substrate 1, and unqualified products in the finished chips can be eliminated in advance. Compared with monolithic integration, the influence of the finished chip preparation yield on the integration yield is reduced, and it is efficient and low-cost.

[0060] Furthermore, the ability to load chips on both the upper and lower surfaces of the silicon substrate 1 improves the integration of multi-chip integration on the one hand, and on the other hand, due to the short interconnection length of the TSV hole, small delay and small interconnection loss, it is beneficial to ensure high-speed interconnection between the chips on the upper and lower surfaces of the silicon substrate 1, reduce power consumption and improve integration performance.

[0061] Furthermore, since the thermal expansion coefficient of silicon is relatively matched with that of other semiconductor materials, glass or ceramics, the chips mounted on the upper and lower surfaces of the silicon substrate 1 are preferably bare chips, which have higher integration and higher integrated functional density than packaged chips.

[0062] Furthermore, before the silicon substrate 1 is wafer-diced, the finger hinge structure is an isolated hollow area of ​​the silicon substrate 1, and the area it occupies is very small relative to the area of ​​the silicon substrate 1, so the silicon substrate 1 can still maintain sufficient strength and can be operated in the form of a whole wafer during the removal of the bond with the carrier 8 and the subsequent film-laminating process before dicing.

[0063] Furthermore, there are gaps between adjacent fingers 2. By controlling the spacing between the finger heads 200 and the finger necks 20 in a pair of fingers 2 and the etched gaps between the opposite finger necks 20 and the finger heads 200, the lateral position offset when the first substrate 1a and the second substrate 1b are relatively rotated and folded can be controlled. At the same time, since silicon is a rigid material with a thickness of not less than 100 μm, the finger hinge structure in the interface area of ​​the silicon substrate 1 will not be deformed when the first substrate 1a and the second substrate 1b are relatively rotated and folded.

[0064] Preferably, the air gap distance between adjacent interdigits 2 in the arrangement direction is 20-50 μm.

[0065] Furthermore, the distance between two adjacent fork heads 200 on the same silicon substrate is greater than the width of the fork neck 20 and less than the width of the fork head 200, so that the first substrate 1a and the second substrate 1b can be locked with each other in the plane direction of the silicon substrate 1. Although they can be relatively rotated and folded, they will not easily detach, thereby achieving better mechanical stability.

[0066] Preferably, the shape of the interdigital head 200 can be rectangular, polygonal, or circular, but is not limited thereto.

[0067] Furthermore, the minimum gap size between the fork finger head 200 and the opposite sub-silicon substrate is related to the thickness of the silicon substrate 1. It is necessary to ensure that when the first substrate 1a or the second substrate 1b is rotated through the fork finger hinge structure, the top of the fork finger head 200 will not touch the top side wall of the opposite sub-silicon substrate. If the gap size between the fork finger head 200 and the opposite sub-silicon substrate is too large, the length of the fork neck 20 will increase, the strength of the fork finger 2 will be weakened, and it will cause a waste of area on the silicon substrate 1.

[0068] Furthermore, the support and positioning columns 4 are perpendicular to the surface of the silicon substrate 1. By adjusting the height of the support and positioning columns 4 and the distance between the support and positioning columns 4 and the edge of the interdigital hinge, the angle between the first substrate 1a and the second substrate 1b when folded can be adjusted. The two rows of support and positioning columns are electrically connected to the first metal rewiring layer 5a and the third metal rewiring layer 5b, respectively, that is, electrically connected to the chip integrated on the substrate. By welding between the column caps at the top of the support and positioning columns 4, the electrical connection between the first substrate 1a and the second substrate 1b is realized, thereby realizing the electrical connection between the integrated chips on the substrate.

[0069] Preferably, the support and positioning columns 4 may be arranged at equal intervals, or at non-equal intervals according to electrical design requirements.

[0070] Preferably, the supporting positioning column 4 can be set to the electrical properties of ground-signal-ground or ground-signal-signal-ground, and a matching design of characteristic impedances such as single-ended 50 ohms and differential 100 ohms can be performed to support low-loss transmission of high-frequency and high-speed signals between the first substrate 1a and the second substrate 1b.

[0071] Furthermore, a flexible structure 3 is included for controlling the self-locking between the two sub-silicon substrates. The function of the flexible structure 3 is to further prevent the first substrate 1a and the second substrate 1b from making relative vertical movements along the surface normal direction thereof, resulting in mutual detachment.

[0072] Preferably, the flexible structures 3 may be arranged at equal intervals or unequal intervals along the folded edges of the first substrate 1a and the second substrate 1b, or may be arranged alternately with the interdigital hinge structures.

[0073] Preferably, the flexible structure 3 can be connected to the metal rewiring layers 7a and 7b on the lower surface of the silicon substrate 1, can be a part of the second metal rewiring layer 7a and the fourth metal rewiring layer 7b, can be a multilayer dielectric film composed of the metal interlayer dielectric in the second and fourth metal rewiring layers 7a and 7b, can contain metal lines, and can also be an organic film layer independent of the second and fourth metal rewiring layers 7a and 7b, but is not limited to this.

[0074] Furthermore, the flexible structure 3 has no overlapping part with the interdigital hinge structure, so that when the first substrate 1a and the second substrate 1b are folded along the interdigital hinge structure, the flexible structure 3 will not affect the relative rotation between the two rows of interdigital hinges.

[0075] Furthermore, the supporting positioning column 4 and the flexible structure 3 are respectively arranged on two opposite surfaces of a sub-silicon substrate. After the first substrate 1a and the second substrate 1b are folded, if the angle is an inner angle, the flexible structure 3 is located at the outer angle of the angle. The advantage is that the flexible structure 3 has more space and a larger bending radius, thereby reducing the requirements for the flexibility and minimum bending radius of the flexible structure 3, reducing the force on the edge contact points of the flexible structure 3 and the first substrate 1a and the second substrate 1b, and avoiding the risk of the flexible structure 3 being delaminated from the edge silicon substrate 1 to a certain extent.

[0076] The present invention provides a three-dimensional integrated structure, and the specific preparation method includes a three-dimensional integrated silicon substrate wafer preparation method (such as Fig.10 As shown) and a three-dimensional integrated structure assembly method (as shown Fig.11 The details are as follows:

[0077] Step 1, preparing a conductive blind hole 60 embedded in the silicon substrate 1 and having an axial direction perpendicular to the surface of the silicon substrate 1 from one surface of the sheet silicon substrate 1;

[0078] Furthermore, the conductive blind hole 60 can be a vertical hole with a hole wall perpendicular to the surface of the silicon substrate 1, or an inclined hole with a hole wall inclined to the surface of the silicon substrate 1, that is, the hole bottom size is smaller than the hole mouth size; the conductive blind hole 60 can be a solid hole that is completely filled inside the hole, or a hollow hole with a metal layer attached to the hole wall; the filling material of the conductive blind hole 60 can be metal, alloy, conductive medium, multi-layer composite material, but is not limited thereto.

[0079] Preferably, the conductive blind via 60 is a vertical solid via filled with metal.

[0080] Step 2, prepare the second and fourth metal rewiring layers 7a and 7b, and pads or bumps on the top thereof, on the opening surface of the conductive blind via 60 of the silicon substrate 1. The metal lines in the second and fourth metal rewiring layers 7a and 7b and the pads or bumps on the top are electrically connected to the conductive blind via 60;

[0081] Step 3, temporarily bonding the surface after the above process to the carrier 8, and exposing the bottom of the filling material of the conductive blind hole 60 by thinning, polishing, etching and other processes on the other surface of the silicon substrate 1, so as to form a TSV conductive through hole 6;

[0082] Step 4, preparing the first and third metal redistribution layers 5a and 5b connecting the bottom of the TSV conductive via 6 and the pads or bumps located on the top thereof;

[0083] Step 5, first prepare an electroplating seed layer on the surface of the first and third metal rewiring layers 5a and 5b, then coat the electroplating seed layer with a thickness greater than the height of the support and positioning column 4, remove the photoresist at the position of the support and positioning column 4 and expose the electroplating seed layer underneath, forming a cavity with the same diameter as the support and positioning column 4, then electroplate a metal column and a welding cap 10 from bottom to top on the electroplating seed layer in the cavity, after removing the photoresist, corrode the electroplating seed layer on the remaining surface, form the support and positioning column 4, and through the first and third metal rewiring layers 5a and 5b, the pad or bump on the top thereof and the support and positioning column 4 are electrically connected to the TSV conductive through hole 6;

[0084] Step 6, coating the surface of the silicon substrate 1 wafer with photoresist, and forming a top view of the interdigital hinge on the photoresist film layer by photolithography and development, wherein the photoresist at the gap between the interdigital fingers 2 and the gap between the interdigital fingers 2 and the substrate is removed, so that the surface of the silicon substrate 1 at this position is exposed, and the surface of the other substrate wafers is still covered with photoresist;

[0085] Step 7, etching away the silicon substrate 1 at the exposed position from top to bottom by dry etching, until the silicon substrate 1 is etched through, thereby completing the preparation of the interdigital hinge formed by the interdigital fingers 2;

[0086] Step 8, after releasing the bonding, remove the carrier 8 to complete the preparation of the three-dimensional integrated silicon substrate wafer.

[0087] like Fig.11 As shown, the present invention also provides a three-dimensional integrated structure assembly method, comprising the following steps:

[0088] Assembling chips on the upper and lower surfaces of the silicon substrate 1 of the prepared three-dimensional integrated structure;

[0089] Slice and separate the first substrate 1a and the second substrate 1b, and fold the first substrate 1a and the second substrate 1b along the interdigitated hinge structure until the top ends of the corresponding support and positioning pillars 4 are in contact or close to each other;

[0090] The welding caps 10 at the top ends of the corresponding supporting positioning columns 4 are welded together to form welding points 9, thereby completing the assembly of a three-dimensional integrated structure.

[0091] Furthermore, at least one chip is assembled on the first substrate 1a, and at least one chip is assembled on the second substrate 1b, and the chip on the first substrate 1a and the chip on the second substrate 1b are electrically interconnected through welding between the welding caps 10 supporting the positioning pillars 4. Chips can be assembled on the upper and lower surfaces of the first substrate 1a, and the chips on the upper and lower surfaces are electrically interconnected through the first metal rewiring layer 5a, TSV conductive vias 6, and the second metal rewiring layer 7a; chips can be assembled on the upper and lower surfaces of the second substrate 1b, and the chips on the upper and lower surfaces are electrically interconnected through the third metal rewiring layer 5b, TSV conductive vias 6, and the fourth metal rewiring layer 7b.

[0092] Preferably, the chip assembled on the substrate may be assembled in a wire bonding manner or in a flip-flop bonding manner, but is not limited thereto.

[0093] Preferably, in addition to bare chips, the substrate may also be assembled with packaged chips, components formed by packaging multiple chips, and passive components such as resistors, capacitors, and inductors, but is not limited thereto.

[0094] Preferably, the above-mentioned multiple chips can be chip-to-wafer assembly on the entire three-dimensional integrated silicon substrate wafer, because the first substrate 1a and the second substrate 1b on the three-dimensional integrated silicon substrate wafer are connected into one piece and have a certain strength. At this time, the process of assembling first and then dicing is adopted.

[0095] Preferably, the above-mentioned multiple chips can be assembled from chips to substrates on a single three-dimensional integrated silicon substrate. In this case, the first substrate 1a and the second substrate 1b are first cut into a larger substrate that is connected into one piece, and then the chips are assembled. Finally, the first substrate 1a and the second substrate 1b are separated by a second cut, thereby releasing the interdigitated hinge structure between the first substrate 1a and the second substrate 1b.

[0096] Furthermore, the solder joints 9 can be welded by reflow soldering, vacuum soldering, laser soldering and other methods. The solder joints 9 achieve mechanical fixation of the position between the first substrate 1a and the second substrate 1b, forming an electrical connection channel between the first substrate 1a and the second substrate 1b, so that the chip on the first substrate 1a and the chip on the second substrate 1b are electrically interconnected through the supporting positioning column 40 and the solder joints 9.

[0097] Furthermore, after assembly is completed, reinforcing glue is applied at the outer angle of the interdigitated structure on the two sub-silicon substrates to improve the high overload resistance of the three-dimensional integrated structure. The periodically crossed interdigitated hinge structure increases the contact area between the silicon material and the reinforcing glue, thereby improving the reinforcement efficiency.

[0098] In the present invention, except for the steps of spatial folding of the silicon substrate 1, contact welding of the supporting positioning pillars 4 and hinge reinforcement, which are single-component operations, the rest are silicon substrate 1 preparation, and process steps such as micro-assembly of multiple chips on the silicon substrate 1 are all whole-wafer operations, which has high yield and is conducive to reducing costs.

[0099] Example 1

[0100] A specific method for preparing a three-dimensional integrated structure in this embodiment 1 is as follows:

[0101] Step 1, such as Figure 4A As shown, a conductive blind hole 60 embedded in the silicon substrate 1 and axially perpendicular to the surface of the silicon substrate 1 is prepared from one surface of the sheet silicon substrate 1, and filled with metal;

[0102] Step 2, such as Figure 4B As shown, the second and fourth metal rewiring layers 7a and 7b and the pads located on the top thereof are prepared on the opening surface of the conductive blind hole 60 of the silicon substrate 1;

[0103] Step 3, such as Figure 4C As shown, the surface after the above process is temporarily bonded to the glass carrier 8, and the bottom of the metal filling material of the conductive blind hole 60 is exposed by thinning, polishing, etching and other processes on the other surface of the silicon substrate 1, so as to form a TSV conductive through hole 6;

[0104] Step 4, such as Figure 4D As shown, the first and third metal rewiring layers 5a and 5b connected to the bottom of the TSV conductive via 6 and the pad located on the top thereof are prepared, the number of layers of the first and second metal rewiring layers 5a and 7a are the same as the number of layers of the third and fourth metal rewiring layers 5b and 7b, respectively, and the UBM layer is prepared on the first and third metal rewiring layers 5a and 5b;

[0105] Step 5, preparing support and positioning pillars 4 on the opposite sides of the upper surface metal rewiring layer by thick glue patterning electroplating;

[0106] Step 6, coating the surface of the silicon substrate 1 wafer with photoresist, and forming a pattern of the interdigitated hinge structure on the photoresist film layer by photolithography and development;

[0107] Step 7, such as Figure 4E As shown, the silicon substrate 1 at the above-mentioned exposed position is etched away from top to bottom by dry etching method until the silicon substrate 1 is etched through, thereby completing the preparation of the interdigital hinge structure;

[0108] Step 8, such as Figure 3 As shown, after the temporary bonding is debonded by laser, the glass carrier 8 is removed to complete the preparation of the three-dimensional integrated silicon substrate wafer.

[0109] A specific assembly method of a three-dimensional integrated structure in this embodiment 1 is as follows:

[0110] Step 1, such as Figure 5A As shown, chips 11-15 are assembled on the upper and lower surfaces of the silicon substrate 1 of the three-dimensional integrated structure according to the design requirements, wherein the chips 11 and 12 are assembled on the first metal rewiring layer 5a of the first substrate 1a, the chip 15 is assembled on the second metal rewiring layer 7a of the first substrate 1a, the chip 13 is assembled on the third metal rewiring layer 5b of the second substrate 1b, and the chip 14 is assembled on the fourth metal rewiring layer 7b of the second substrate 1b;

[0111] Step 2, such as Figure 5B As shown, the first substrate 1a and the second substrate 1b on which the chip is assembled are folded along the interdigitated hinge structure in the middle until the welding caps 10 at the tops of the supporting positioning pillars 4 are in contact or nearly in contact, as shown in FIG. Figure 5C In this embodiment 1, when the welding caps 10 are in contact, the angle between the first substrate 1a and the second substrate 1b is close to 90 degrees, that is, the first substrate 1a and the second substrate 1b are approximately perpendicular to each other.

[0112] Step 3, using laser welding to melt and weld the two welding caps 10 together to form welding points 9 between the supporting positioning columns 4, so as to complete the mechanical fixation of the relative positions of the first substrate 1a and the second substrate 1b. Figure 5D shown.

[0113] Step 4, applying reinforcing glue along the diagonal angle between the first substrate 1a and the second substrate 1b where the support positioning column 4 is located, that is, the intersection angle of the fork fingers 2, to further mechanically reinforce the folded structure of the first substrate 1a and the second substrate 1b.

[0114] Example 2

[0115] like Figure 6 , 7 and 8, the specific preparation method of a three-dimensional integrated structure in this embodiment 2 is as follows:

[0116] Step 1, such as Figure 4A As shown, a conductive blind hole 60 embedded in the silicon substrate 1 and axially perpendicular to the surface of the silicon substrate 1 is prepared from one surface of the sheet silicon substrate 1, and filled with metal;

[0117] Step 2, such as Figure 4BAs shown, the second and fourth metal rewiring layers 7a and 7b and the pads located on the top thereof are prepared on the opening surface of the conductive blind hole 60 of the silicon substrate 1;

[0118] Step 3, preparing a flexible strip, which is a multilayer dielectric film composed of the metal interlayer dielectric in the second and fourth metal rewiring layers 7a and 7b, and arranged at the folded edge of the first substrate 1a and the second substrate 1b;

[0119] Step 3, such as Figure 4C As shown, the surface after the above process is temporarily bonded to the glass carrier 8, and the bottom of the conductive blind hole metal filling material is exposed by thinning, polishing, etching and other processes on the other surface of the silicon substrate 1 to form a TSV conductive through hole 6;

[0120] Step 4, such as Figure 4D As shown, the first and third metal rewiring layers 5a and 5b connecting the bottom of the TSV conductive via 6 and the pad located on the top thereof are prepared;

[0121] Step 5, preparing support and positioning pillars 4 on the opposite sides of the upper surface metal rewiring layer by thick glue patterning electroplating;

[0122] Step 6, coating the surface of the silicon substrate 1 wafer with photoresist, forming a pattern of the interdigitated hinge structure on the photoresist film layer by photolithography and development, and exposing the vertical corresponding part of the flexible strip;

[0123] Step 7, such as Figure 4E As shown, the silicon substrate 1 at the above-mentioned exposed position is etched away from top to bottom by dry etching method until the silicon substrate 1 is etched through, thereby completing the preparation of the interdigital hinge structure and the preparation of the flexible strip;

[0124] Step 8, such as Figure 7 As shown, after the temporary bonding is debonded by laser, the glass carrier 8 is removed to complete the preparation of the three-dimensional integrated silicon substrate wafer.

Claims

1. A three-dimensional integrated structure, characterized in that: It comprises two sub-silicon substrates, and one end of each sub-silicon substrate is provided with an interdigital structure; The interdigital structure comprises a plurality of interdigital fingers (2), each interdigital finger (2) comprises an interdigital finger head (200) and an interdigital finger neck (20), one end of the interdigital finger neck (20) is fixedly connected to one end of the interdigital finger head (200), the width of the interdigital finger head (200) is greater than the width of the interdigital finger neck (20), and the interdigital finger necks (200) on one sub-silicon substrate and the interdigital finger heads (200) on another sub-silicon substrate are arranged in a staggered and interlocking manner to form an interdigital hinge structure; It also includes a support positioning structure, the support positioning structure including a plurality of support positioning columns (4), two rows of support positioning columns are arranged one by one along one end of the sub-silicon substrate provided with the interdigitated structure, and the top ends of the support positioning columns (4) are provided with welding caps (10); When the two sub-silicon substrates are in a folded state along the interdigitated hinge structure, the welding caps (10) at the top ends of the corresponding supporting positioning columns (4) are welded together to form welding points (9) for fixing the relative positions of the two sub-silicon substrates and providing electrical connection between the two sub-silicon substrates.

2. A three-dimensional integrated structure according to claim 1, characterized in that: There are gaps between adjacent interdigits (2); and the distance between two adjacent interdigit heads (200) on the same silicon substrate is greater than the width of the interdigit neck (20) and less than the width of the interdigit head (200).

3. A three-dimensional integrated structure according to claim 1, characterized in that: The supporting and positioning columns (4) are perpendicular to the surface of the silicon substrate (1), and the supporting and positioning column row is parallel to the interdigital hinge structure; When the two sub-silicon substrates are in a folded state along the interdigitated hinge structure, the welding caps (10) at the top ends of the two rows of corresponding support positioning columns (4) are in contact or close to each other.

4. The three-dimensional integrated structure according to claim 1, characterized in that: The shape of the interdigital head (200) is rectangular, polygonal or circular.

5. A three-dimensional integrated structure according to any one of claims 1 to 4, characterized in that: It also includes a flexible structure (3), wherein the flexible structure (3) and the interdigital hinge structure are arranged alternately or the flexible structure (3) is arranged along the folded edges of two sub-silicon substrates.

6. A three-dimensional integrated structure according to claim 5, characterized in that: The flexible structure (3) is connected to the metal rewiring layer on the lower surface of the silicon substrate (1), or is a part of the second metal rewiring layer (7a) and the fourth metal rewiring layer (7b), or is a multilayer dielectric film composed of the metal interlayer dielectric in the second metal rewiring layer (7a) and the fourth metal rewiring layer (7b), or is an organic film layer independent of the second metal rewiring layer (7a) and the fourth metal rewiring layer (7b).

7. The three-dimensional integrated structure according to claim 5, characterized in that: The supporting positioning column (4) and the flexible structure (3) are respectively arranged on two opposite surfaces of a sub-silicon substrate.

8. A method for preparing a silicon substrate wafer with a three-dimensional integrated structure, characterized in that: Based on the three-dimensional integrated structure according to any one of claims 1 to 7, The following steps are involved: A conductive blind hole (60) is prepared from one surface of the sheet-like silicon substrate and is embedded in the silicon substrate (1) and has an axial direction perpendicular to the surface of the silicon substrate (1); Preparing a multi-layer metal wiring layer electrically connected to the conductive blind hole (60) and a pad or bump located on the top of the multi-layer metal wiring layer on the opening surface of the conductive blind hole (60) of the silicon substrate (1); Temporarily bonding the completed wiring surface of the silicon substrate (1) to the carrier board (8); Exposing the bottom of the filling material of the conductive blind hole (60) to form a TSV conductive through hole (6); Prepare a multi-layer metal wiring layer connected to the bottom of the TSV conductive through hole (6), a pad or bump located on the top of the multi-layer metal wiring layer, and a support positioning column (4) located at the opposite side edge of the multi-layer metal wiring layer; The surface of the silicon substrate wafer is coated with photoresist, a top view of the interdigitated hinge is photoetched, and dry etching is performed until the silicon substrate (1) is etched through, thereby completing the preparation of the interdigitated hinge structure formed by the interdigitated fingers (2); After the bonding is released, the carrier plate (8) is removed, and the preparation of the three-dimensional integrated silicon substrate wafer is completed.

9. A method for assembling a three-dimensional integrated structure, characterized in that: Based on the method for preparing the three-dimensional integrated structure silicon substrate wafer according to claim 8, Assembling chips on the upper and lower surfaces of the prepared three-dimensional integrated structure silicon substrate; Slicing and separating the two sub-silicon substrates, and folding the two sub-silicon substrates along the interdigitated hinge structure until the top ends of the corresponding support positioning pillars (4) are in contact or close to each other; The welding caps (10) at the top ends of the corresponding supporting positioning columns (4) are welded together to form welding points (9), thereby completing the assembly of a three-dimensional integrated structure.

10. The method for assembling a three-dimensional integrated structure according to claim 9, characterized in that: After the assembly is completed, reinforcing glue is applied to the outer corners of the interdigitated structures on the two sub-silicon substrates.

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