Method, device and processing system for improving machine production efficiency

Abstract

The present application provides a method, device and processing system method for improving the production efficiency of a machine, the method comprising: calculating the total idle time corresponding to all processing sequences of a wafer group to be processed, obtaining multiple total idle times, the total idle time being the sum of the estimated idle times corresponding to two adjacent wafer groups to be processed in all processing sequences, the estimated idle time being the estimated waiting time for the two adjacent wafer groups to be processed to be processed successively; determining the processing sequence corresponding to the shortest total idle time as the optimal processing sequence; controlling the machine to process the wafer group to be processed according to the optimal processing sequence. The method solves the problem of low output efficiency of the machine due to unreasonable processing sequence in the prior art.

Description

Technical Field

[0001] The present application relates to the field of machine processing technology, and more specifically, to a method, device, computer-readable storage medium, processor, and processing system for improving machine production efficiency. Background Art

[0002] In the semiconductor manufacturing process, for chamber machines, that is, machines that process a single wafer at a time in a single chamber, the wafer group is the most basic processing unit of the machine, which can be a single wafer or multiple wafers in a wafer box. Due to different processing requirements, a wafer group corresponds to a recipe. Recipe is a formula in industrial automation manufacturing, and its content may include multiple processes in the process processing process and the process parameter values ​​of each process and the duration of the process. Different recipe matching sequences will significantly affect the output efficiency and speed of the machine. A good recipe matching strategy can significantly improve the machine production efficiency OEE. In the past, engineers could only judge the better front and back recipe matching mode of chamber machines based on experience, and there is no systematic method to quantitatively recommend recipe matching strategies. The existing recipe matching relies too much on manual experience and requires high skills of engineers. There is no systematic method to recommend recipe matching strategies for chamber machines with the purpose of improving production efficiency.

[0003] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country for those skilled in the art. Summary of the invention

[0004] The main purpose of the present application is to provide a method, device, computer-readable storage medium, processor and processing system for improving the production efficiency of a machine, so as to solve the problem in the prior art that the production efficiency of the machine is low due to unreasonable processing sequence.

[0005] According to one aspect of an embodiment of the present invention, a method for improving machine production efficiency is provided, comprising: calculating the total idle time corresponding to all processing sequences of a wafer group to be processed, obtaining a plurality of the total idle times, wherein the total idle time is the sum of the estimated idle times corresponding to two adjacent wafer groups to be processed in all processing sequences, wherein the estimated idle time is the estimated waiting time for two adjacent wafer groups to be processed to be processed successively; determining the processing sequence corresponding to the shortest total idle time as the optimal processing sequence; and controlling the machine to process the wafer group to be processed according to the optimal processing sequence.

[0006] Optionally, the total idle time corresponding to all processing sequences of the wafer group to be processed is calculated to obtain multiple total idle times, including: within a predetermined time, obtaining at least one average idle time, the average idle time is the average of N idle times, the idle time is the time between the end time of processing of the Kth processed wafer in the first wafer group and the start time of processing of the Kth processed wafer in the second wafer group, the start time of processing of the Kth processed wafer in the first wafer group is earlier than the start time of processing of the Kth processed wafer in the second wafer group, the first wafer group and the second wafer group are both composed of N wafers, wherein N≥1, 1≤K≤N, and the start processing time of the first wafer group and the start processing time of the second wafer group are adjacent; calculating the corresponding average idle times of multiple adjacent wafer groups. The median of the average idle time is obtained to obtain multiple median idle times, the median idle time corresponds to the adjacent wafer groups one by one, the adjacent wafer groups include two wafer groups with adjacent start processing time and corresponding to a processing parameter group respectively, one adjacent wafer group corresponds to a combination of the processing parameter groups, any two adjacent wafer groups correspond to different combinations of two processing parameter groups, and multiple adjacent wafer groups correspond to all combinations of the processing parameter groups; the total idle time corresponding to all processing sequences of the wafer group to be processed is calculated to obtain multiple total idle times, the total idle time is the sum of the expected idle times corresponding to the two adjacent wafer groups to be processed in all processing sequences, and the expected idle time is the median idle time of the adjacent wafer groups corresponding to the two adjacent wafer groups to be processed.

[0007] Optionally, the processing technology of the machine includes multiple process units, and the process unit includes multiple processes. Within a predetermined time, the average idle time of all two adjacent wafer groups is obtained to obtain multiple average idle times, including: within the predetermined time when the machine executes the target process unit for production, the average idle time of all two adjacent wafer groups is obtained to obtain multiple average idle times, the target process unit is any one of the process units, the average idle time is the average value of at least one idle time, and the idle time is the time between the end time of processing the first wafer and the start time of processing the second wafer during the execution of the target process unit for production.

[0008] Optionally, the machine simultaneously executes two of the target process units, the two target process units are the same process unit, the first wafer group includes a third wafer, a fourth wafer and a fifth wafer, the second wafer group includes a sixth wafer, a seventh wafer and an eighth wafer, one of the target process units executed by the machine processes the third wafer, the sixth wafer and the seventh wafer respectively, and the other target process unit executed by the machine processes the fourth wafer, the fifth wafer and the eighth wafer respectively, the average idle time is the average of the first idle time, the second idle time and the third idle time, the first idle time is the time between the start time of processing the sixth wafer and the end time of processing the third wafer, the second idle time is the time between the start time of processing the seventh wafer and the end time of processing the fourth wafer, and the third idle time is the time between the start time of processing the eighth wafer and the end time of processing the fifth wafer.

[0009] Optionally, there are two processing parameter groups, namely a first processing parameter group and a second processing parameter group, and the median of the corresponding idle time of multiple adjacent wafer groups is calculated to obtain multiple median idle times, including: calculating the median of the average idle time of multiple first adjacent wafer groups to obtain a first median, the first adjacent wafer group includes a third wafer group and a fourth wafer group, the processing parameter group corresponding to the third wafer group is the first processing parameter group, the processing parameter group corresponding to the fourth wafer group is the first processing parameter group, and the start processing time of the third wafer group is earlier than the start processing time of the fourth wafer group; calculating the median of the average idle time of multiple second adjacent wafer groups to obtain a second median, the second adjacent wafer group includes a fifth wafer group and a sixth wafer group, the processing parameter group corresponding to the fifth wafer group is the second processing parameter group, and the processing parameter group corresponding to the sixth wafer group is the second processing parameter group. parameter group, the start processing time of the fifth wafer group is earlier than the start processing time of the sixth wafer group; the median of the average idle time of multiple third adjacent wafer groups is calculated to obtain a third median, the third adjacent wafer groups include a seventh wafer group and an eighth wafer group, the processing parameter group corresponding to the seventh wafer group is the first processing parameter group, the processing parameter group corresponding to the eighth wafer group is the second processing parameter group, and the start processing time of the seventh wafer group is earlier than the start processing time of the eighth wafer group; the median of the average idle time of multiple fourth adjacent wafer groups is calculated to obtain a fourth median, the fourth adjacent wafer groups include a ninth wafer group and a tenth wafer group, the processing parameter group corresponding to the ninth wafer group is the second processing parameter group, the processing parameter group corresponding to the tenth wafer group is the first processing parameter group, and the start processing time of the ninth wafer group is earlier than the start processing time of the tenth wafer group.

[0010] Optionally, the wafer group to be processed includes a first wafer group to be processed, a second wafer group to be processed and a third wafer group to be processed, the processing parameter group corresponding to the first wafer group to be processed is the first processing parameter group, the processing parameter group corresponding to the second wafer group to be processed is the second processing parameter group, and the processing parameter group corresponding to the third wafer group to be processed is the first processing parameter group, and the total idle time corresponding to all processing sequences of the wafer group to be processed is calculated to obtain multiple total idle times, including: when the processing sequence is to process the first wafer group to be processed, the second wafer group to be processed and the third wafer group to be processed in sequence, the total idle time is the sum of the third median and the fourth median; when the processing sequence is to process the first wafer group to be processed, the third wafer group to be processed and the second wafer group to be processed in sequence, the total idle time is the sum of the third median and the fourth median. the sum of the first median and the third median; when the processing order is to process the second wafer group to be processed, the first wafer group to be processed and the third wafer group to be processed in sequence, the total idle time is the sum of the fourth median and the first median; when the processing order is to process the second wafer group to be processed, the third wafer group to be processed and the first wafer group to be processed in sequence, the total idle time is the sum of the fourth median and the first median; when the processing order is to process the third wafer group to be processed, the first wafer group to be processed and the second wafer group to be processed in sequence, the total idle time is the sum of the first median and the third median; when the processing order is to process the third wafer group to be processed, the second wafer group to be processed and the first wafer group to be processed in sequence, the total idle time is the sum of the third median and the fourth median.

[0011] According to another aspect of an embodiment of the present invention, a device for improving machine production efficiency is also provided, including: a calculation unit, used to calculate the total idle time corresponding to all processing sequences of a wafer group to be processed, and obtain a plurality of the total idle times, wherein the total idle time is the sum of the estimated idle times corresponding to two adjacent wafer groups to be processed in all processing sequences, and the estimated idle time is the estimated waiting time for two adjacent wafer groups to be processed to be processed successively; a determination unit, used to determine the processing sequence corresponding to the shortest total idle time as the optimal processing sequence; and a control unit, used to control the machine to process the wafer group to be processed according to the optimal processing sequence.

[0012] According to yet another aspect of the embodiments of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored program, wherein the program executes any one of the methods described.

[0013] According to yet another aspect of an embodiment of the present invention, a processor is provided, wherein the processor is used to run a program, wherein any one of the methods is executed when the program is run.

[0014] According to another aspect of the embodiments of the present invention, there is further provided a processing system, including a machine and a device for improving the production efficiency of the machine, wherein the device for improving the production efficiency of the machine includes a device for executing any one of the methods described above.

[0015] In an embodiment of the present invention, in the method for improving the production efficiency of the above-mentioned machine, first, the total idle time corresponding to all processing sequences of the wafer group to be processed is calculated to obtain multiple total idle times, and the total idle time is the sum of the estimated idle times corresponding to all two adjacent wafer groups to be processed, and the estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed one after another; then, the processing sequence corresponding to the shortest total idle time is determined as the optimal processing sequence; finally, the machine is controlled to process the wafer group to be processed according to the optimal processing sequence. This method calculates the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times, compares the multiple total idle times to determine that the processing sequence corresponding to the shortest total idle time is the optimal processing sequence, and controls the machine to process the wafer group to be processed according to the optimal processing sequence, thereby reducing the total idle time to improve the production efficiency of the machine, and solving the problem of low output efficiency of the machine due to unreasonable processing sequence in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A flow chart showing a method for improving machine production efficiency according to an embodiment of the present application is shown;

[0018] Figure 2 A timing diagram of a machine processing a first wafer group and a second wafer group according to an embodiment of the present application is shown;

[0019] Figure 3 A schematic diagram of a device for improving machine production efficiency according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0021] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0024] For the convenience of description, some nouns or terms involved in the embodiments of the present application are explained below:

[0025] A processing parameter group, namely a recipe, is a recipe in industrial automation manufacturing, and its content may include multiple processes in the process of technological processing, as well as the process parameter values ​​of each process and the duration of the process.

[0026] As mentioned in the background technology, the unreasonable processing sequence in the prior art leads to low output efficiency of the machine. In order to solve the above problem, a typical embodiment of the present application provides a method, device, computer-readable storage medium, processor and processing system for improving the production efficiency of a machine.

[0027] According to an embodiment of the present application, a method for improving production efficiency of a machine is provided.

[0028] Figure 1 FIG. 1 is a flow chart of a method for improving machine production efficiency according to an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0029] Step S101, calculating the total idle time corresponding to all processing sequences of the wafer group to be processed, and obtaining a plurality of the total idle times, wherein the total idle time is the sum of the estimated idle time corresponding to two adjacent wafer groups to be processed in all processing sequences, and the estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed successively;

[0030] Step S102, determining the processing sequence corresponding to the shortest total idle time as the optimal processing sequence;

[0031] Step S103 , controlling the machine to process the above-mentioned wafer group to be processed according to the above-mentioned optimal processing sequence.

[0032] In the above-mentioned method for improving the production efficiency of the machine, first, the total idle time corresponding to all processing sequences of the wafer group to be processed is calculated to obtain multiple total idle times, and the total idle time is the sum of the estimated idle times corresponding to all two adjacent wafer groups to be processed, and the estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed one after another; then, the processing sequence corresponding to the shortest total idle time is determined as the optimal processing sequence; finally, the machine is controlled to process the wafer group to be processed according to the optimal processing sequence. This method calculates the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times, compares the multiple total idle times to determine that the processing sequence corresponding to the shortest total idle time is the optimal processing sequence, and controls the machine to process the wafer group to be processed according to the optimal processing sequence, thereby reducing the total idle time to improve the production efficiency of the machine, and solving the problem of low output efficiency of the machine due to unreasonable processing sequence in the prior art.

[0033] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0034] In one embodiment of the present application, the total idle time corresponding to all processing sequences of a wafer group to be processed is calculated to obtain multiple total idle times, including: obtaining at least one average idle time within a predetermined time, the average idle time being the average of N idle times, the idle time being the time between the end time of processing of the Kth processed wafer in the first wafer group and the start time of processing of the Kth processed wafer in the second wafer group, the start time of processing of the Kth processed wafer in the first wafer group being earlier than the start time of processing of the Kth processed wafer in the second wafer group, the first wafer group and the second wafer group are both composed of N wafers, wherein N≥1, 1≤K≤N, and the start processing time of the first wafer group and the start processing time of the second wafer group are adjacent; calculating the corresponding idle times of multiple adjacent wafer groups. The median of the above-mentioned average idle time is obtained to obtain multiple median idle times, and the above-mentioned median idle times correspond one-to-one to the above-mentioned adjacent wafer groups. The above-mentioned adjacent wafer groups include two of the above-mentioned wafer groups whose start processing time is adjacent and respectively correspond to one processing parameter group. One of the above-mentioned adjacent wafer groups corresponds to a combination of the above-mentioned processing parameter groups. The combinations of the two above-mentioned processing parameter groups corresponding to any two of the above-mentioned adjacent wafer groups are different, and multiple of the above-mentioned adjacent wafer groups correspond to all combinations of the above-mentioned processing parameter groups; the total idle time corresponding to all processing sequences of the wafer group to be processed is calculated to obtain multiple of the above-mentioned total idle times. The above-mentioned total idle time is the sum of the expected idle times corresponding to the two adjacent wafer groups to be processed in all processing sequences, and the above-mentioned expected idle time is the above-mentioned median idle time of the above-mentioned adjacent wafer groups corresponding to the two adjacent wafer groups to be processed.Specifically, the first wafer group and the second wafer group are each composed of N wafers, one wafer corresponds to one idle time, so there are also N idle times. The processing of multiple wafers in each wafer group also has a sequence. The idle time is the time between the end time of processing the Kth processed wafer in the first wafer group and the start time of processing the Kth processed wafer in the second wafer group, 1≤K≤N, and the average value of the N idle times is calculated to obtain the average idle time of the first wafer group and the second wafer group with adjacent start processing times. Since one wafer group corresponds to one processing parameter group, the processing parameter groups corresponding to the first wafer group and the second wafer group are different, and the average idle time is also different. One of the adjacent wafer groups corresponds to a combination of the processing parameter groups, and each of the processing There may be multiple adjacent wafer groups corresponding to the processing start time of the combination of parameter groups, that is, each adjacent wafer group corresponds to multiple average idle times. The medians of the corresponding average idle times of the multiple adjacent wafer groups are calculated to obtain multiple median idle times. Since the multiple adjacent wafer groups correspond to all combinations of the above processing parameter groups, the median idle times corresponding to the combinations of all the above processing parameter groups are obtained. The total idle times corresponding to all processing sequences of the wafer groups to be processed are calculated to obtain multiple total idle times. After the processing sequence is determined, all two adjacent wafer groups to be processed with corresponding processing sequences are matched with the corresponding combinations of the above processing parameter groups to obtain the corresponding median idle times. After calculating and matching all the median idle times, the above total idle time is obtained. One processing sequence corresponds to one total idle time.

[0035] It should be noted that the wafer group to be processed within the above-mentioned predetermined time is taken as a sample. The longer the above-mentioned predetermined time is, the more samples there are, the more accurate the above-mentioned estimated idle time is, and the greater the improvement in output efficiency will be achieved by the determined optimal processing sequence. In addition, the number of wafers in the above-mentioned first wafer group and the above-mentioned second wafer group is different, and N is the number of wafers in the wafer group with a smaller number of wafers.

[0036] In one embodiment of the present application, the processing technology of the machine includes multiple process units, and the process units include multiple processes. Within a predetermined time, the average idle time of all two adjacent wafer groups is obtained to obtain multiple average idle times, including: within the predetermined time when the machine executes the target process unit for production, the average idle time of all two adjacent wafer groups is obtained to obtain multiple average idle times, the target process unit is any one of the process units, the average idle time is the average value of at least one idle time, and the idle time is the time between the end time of processing the first wafer and the start time of processing the second wafer during the production process of the target process unit. Specifically, the process unit composed of multiple processes is used as a standard unit for processing, the processing start time is the time when the target process unit starts processing the wafer group, and the processing end time is the time when the target process unit ends processing the wafer group. Each process unit can determine an optimal processing sequence through the above-mentioned improvement method to improve the output efficiency of each process unit.

[0037] In one embodiment of the present application, Figure 2As shown, the above-mentioned machine simultaneously executes two of the above-mentioned target process units, the two above-mentioned target process units are the same above-mentioned process unit, the above-mentioned first wafer group lot1 includes the third wafer lot1-w1, the fourth wafer lot1-w2 and the fifth wafer lot1-w3, the above-mentioned second wafer group lot2 includes the sixth wafer lot2-w1, the seventh wafer lot2-w2 and the eighth wafer lot2-w3, and the above-mentioned target process unit executed by the above-mentioned machine processes the above-mentioned third wafer lot1-w1, the above-mentioned sixth wafer lot2-w1 and the above-mentioned seventh wafer lot2-w2 respectively, and the above-mentioned target process unit executed by the above-mentioned machine processes the above-mentioned fourth wafer lot1-w2, the above-mentioned The fifth wafer lot1-w3 and the eighth wafer lot2-w3 are processed, and the average idle time is the average of the first idle time, the second idle time and the third idle time. The first idle time is the time between the processing start time t5 of the sixth wafer lot2-w1 and the processing end time t2 of the third wafer lot1-w1. The second idle time is the time between the processing start time t9 of the seventh wafer lot2-w2 and the processing end time t4 of the fourth wafer lot1-w2. The third idle time is the time between the processing start time t11 of the eighth wafer lot2-w3 and the processing end time t8 of the fifth wafer lot1-w3. Specifically, the time for the above-mentioned machine to simultaneously execute the processing of all wafer groups of the two above-mentioned target process units is T. The above-mentioned first wafer group lot1 and the above-mentioned second wafer group lot2 both have three wafer groups, that is, N=3, and the corresponding idle time is three. The above-mentioned first idle time T 1 is the time between the processing start time t5 of the sixth wafer lot2-w1 and the processing end time t2 of the third wafer lot1-w1, that is, T 1 =t5-t2, the second idle time T 2 is the time between the processing start time t9 of the seventh wafer lot2-w2 and the processing end time t4 of the fourth wafer lot1-w2, that is, T 2 =t9-t4, the third idle time T 3 is the time between the processing start time t11 of the eighth wafer lot2-w3 and the processing end time t8 of the fifth wafer lot1-w3, that is, T 3 =t11-t8, the above average idle time T 平 is the first idle time T 1 , the second idle time T 2 and the third idle time T 3 The average value, T 平 =T 1 +T 2 +T3 / 3.

[0038] In one embodiment of the present application, there are two processing parameter groups, namely a first processing parameter group and a second processing parameter group, and the median of the corresponding idle times of multiple adjacent wafer groups is calculated to obtain multiple median idle times, including: calculating the median of the average idle time of multiple first adjacent wafer groups to obtain a first median, the first adjacent wafer group includes a third wafer group and a fourth wafer group, the processing parameter group corresponding to the third wafer group is the first processing parameter group, the processing parameter group corresponding to the fourth wafer group is the first processing parameter group, and the start processing time of the third wafer group is earlier than the start processing time of the fourth wafer group; calculating the median of the average idle time of multiple second adjacent wafer groups to obtain a second median, the second adjacent wafer group includes a fifth wafer group and a sixth wafer group, the processing parameter group corresponding to the fifth wafer group is the second processing parameter group, and the processing parameter group corresponding to the sixth wafer group is the first processing parameter group. Second processing parameter group, the start processing time of the above-mentioned fifth wafer group is earlier than the start processing time of the above-mentioned sixth wafer group; calculate the median of the average idle time of multiple third adjacent wafer groups to obtain a third median, the above-mentioned third adjacent wafer groups include the seventh wafer group and the eighth wafer group, the above-mentioned processing parameter group corresponding to the above-mentioned seventh wafer group is the above-mentioned first processing parameter group, the above-mentioned processing parameter group corresponding to the above-mentioned eighth wafer group is the above-mentioned second processing parameter group, and the start processing time of the above-mentioned seventh wafer group is earlier than the start processing time of the above-mentioned eighth wafer group; calculate the median of the average idle time of multiple fourth adjacent wafer groups to obtain a fourth median, the above-mentioned fourth adjacent wafer group includes the ninth wafer group and the tenth wafer group, the above-mentioned processing parameter group corresponding to the above-mentioned ninth wafer group is the above-mentioned second processing parameter group, the above-mentioned processing parameter group corresponding to the above-mentioned tenth wafer group is the above-mentioned first processing parameter group, and the start processing time of the above-mentioned ninth wafer group is earlier than the start processing time of the above-mentioned tenth wafer group. Specifically, there are two processing parameter groups and four combinations of the processing parameter groups, corresponding to the first adjacent wafer group, the second adjacent wafer group, the third adjacent wafer group and the fourth adjacent wafer group. Taking the first adjacent wafer group as an example, the processing parameter group corresponding to the wafer group with an earlier start time in the first adjacent wafer group is the first processing parameter group, and the processing parameter group corresponding to the wafer group with a later start time in the first adjacent wafer group is the first processing parameter group. Multiple first adjacent wafer groups correspond to multiple average idle times, and the median of the multiple average idle times is taken to obtain the first median. For example, the multiple average idle times are 3S, 4S, 6S and 8S respectively, and the first median is 5S. Similarly, the second median corresponding to the second adjacent wafer group, the third median corresponding to the third adjacent wafer group and the fourth median corresponding to the fourth adjacent wafer group can be calculated.

[0039] In one embodiment of the present application, the above-mentioned wafer group to be processed includes a first wafer group to be processed, a second wafer group to be processed and a third wafer group to be processed, the above-mentioned processing parameter group corresponding to the above-mentioned first wafer group to be processed is the above-mentioned first processing parameter group, the above-mentioned processing parameter group corresponding to the above-mentioned second wafer group to be processed is the above-mentioned second processing parameter group, and the above-mentioned processing parameter group corresponding to the above-mentioned third wafer group to be processed is the above-mentioned first processing parameter group, and the total idle time corresponding to all processing sequences of the wafer group to be processed is calculated to obtain multiple total idle times, including: when the above-mentioned processing sequence is to process the above-mentioned first wafer group to be processed, the above-mentioned second wafer group to be processed and the above-mentioned third wafer group to be processed in sequence, the above-mentioned total idle time is the sum of the above-mentioned third median and the above-mentioned fourth median; when the above-mentioned processing sequence is to process the above-mentioned first wafer group to be processed, the above-mentioned third wafer group to be processed and the above-mentioned second wafer group to be processed in sequence, the above-mentioned total idle time It is the sum of the first median and the third median; when the processing order is to sequentially process the second wafer group to be processed, the first wafer group to be processed and the third wafer group to be processed, the total idle time is the sum of the fourth median and the first median; when the processing order is to sequentially process the second wafer group to be processed, the third wafer group to be processed and the first wafer group to be processed, the total idle time is the sum of the fourth median and the first median; when the processing order is to sequentially process the third wafer group to be processed, the first wafer group to be processed and the second wafer group to be processed, the total idle time is the sum of the first median and the third median; when the processing order is to sequentially process the third wafer group to be processed, the second wafer group to be processed and the first wafer group to be processed, the total idle time is the sum of the third median and the fourth median.Specifically, taking the three wafer groups to be processed and the two processing parameter groups as an example, the three wafer groups to be processed have 6 processing sequences. When the processing sequence is to sequentially process the first wafer group to be processed, the second wafer group to be processed and the third wafer group to be processed, since the processing parameter group corresponding to the first wafer group to be processed is the first processing parameter group, and the processing parameter group corresponding to the second wafer group to be processed is the second processing parameter group, the estimated idle time between the first wafer group to be processed and the second wafer group to be processed is the third median, and the processing parameter group corresponding to the second wafer group to be processed is the third median. is the second processing parameter group, and the processing parameter group corresponding to the third group of wafers to be processed is the first processing parameter group. Therefore, the estimated idle time between the second group of wafers to be processed and the third group of wafers to be processed is the fourth median, and the total idle time corresponding to this processing sequence is the sum of the third median and the fourth median. Similarly, the total idle times corresponding to the remaining five processing sequences are the sum of the first median and the third median, the sum of the fourth median and the first median, the sum of the fourth median and the first median, the sum of the first median and the third median, and the sum of the third median and the fourth median.

[0040] The embodiment of the present application also provides a device for improving the production efficiency of a machine. It should be noted that the device for improving the production efficiency of a machine in the embodiment of the present application can be used to execute the method for improving the production efficiency of a machine provided in the embodiment of the present application. The device for improving the production efficiency of a machine provided in the embodiment of the present application is introduced below.

[0041] Figure 3 Schematic diagram of a device for improving machine production efficiency according to an embodiment of the present application. Figure 3 As shown, the device comprises:

[0042] The calculation unit 10 is used to calculate the total idle time corresponding to all processing sequences of the wafer group to be processed, and obtain a plurality of the above total idle times, wherein the above total idle time is the sum of the estimated idle time corresponding to two adjacent wafer groups to be processed in all processing sequences, and the above estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed successively;

[0043] A determination unit 20, configured to determine the processing sequence corresponding to the shortest total idle time as the optimal processing sequence;

[0044] The control unit 30 is used to control the machine to process the above-mentioned wafer group to be processed according to the above-mentioned optimal processing sequence.

[0045] In the above-mentioned device for improving the production efficiency of the machine, the calculation unit calculates the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times, and the total idle time is the sum of the estimated idle times corresponding to all two adjacent wafer groups to be processed, and the estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed one after another; the determination unit determines the processing sequence corresponding to the shortest total idle time as the optimal processing sequence; and the control unit controls the machine to process the wafer group to be processed according to the optimal processing sequence. The device calculates the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times, compares the multiple total idle times to determine that the processing sequence corresponding to the shortest total idle time is the optimal processing sequence, and controls the machine to process the wafer group to be processed according to the optimal processing sequence, thereby reducing the total idle time and improving the production efficiency of the machine, and solving the problem of low output efficiency of the machine due to unreasonable processing sequence in the prior art.

[0046] In one embodiment of the present application, the calculation unit includes an acquisition module, a first calculation module and a second calculation module, wherein the acquisition module is used to acquire at least one average idle time within a predetermined time, the average idle time is the average of N idle times, the idle time is the time between the end time of processing of the Kth processed wafer in the first wafer group and the start time of processing of the Kth processed wafer in the second wafer group, the start time of processing of the Kth processed wafer in the first wafer group is earlier than the start time of processing of the Kth processed wafer in the second wafer group, the first wafer group and the second wafer group are both composed of N wafers, wherein N≥1, 1≤K≤N, and the start processing time of the first wafer group and the start processing time of the second wafer group are adjacent; the first calculation module is used to calculate the corresponding The median of the above-mentioned average idle time is used to obtain multiple median idle times, and the above-mentioned median idle times correspond one-to-one to the above-mentioned adjacent wafer groups. The above-mentioned adjacent wafer groups include two of the above-mentioned wafer groups whose start processing time is adjacent and respectively correspond to a processing parameter group. One of the above-mentioned adjacent wafer groups corresponds to a combination of the above-mentioned processing parameter groups. The combinations of the two above-mentioned processing parameter groups corresponding to any two of the above-mentioned adjacent wafer groups are different, and multiple of the above-mentioned adjacent wafer groups correspond to all combinations of the above-mentioned processing parameter groups; the above-mentioned second calculation module is used to calculate the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple of the above-mentioned total idle times. The above-mentioned total idle time is the sum of the expected idle times corresponding to the above-mentioned two adjacent wafer groups to be processed in all processing sequences, and the above-mentioned expected idle time is the above-mentioned median idle time of the above-mentioned adjacent wafer groups corresponding to the above-mentioned two adjacent wafer groups to be processed.Specifically, the first wafer group and the second wafer group are each composed of N wafers, one wafer corresponds to one idle time, so there are also N idle times. The processing of multiple wafers in each wafer group also has a sequence. The idle time is the time between the end time of processing the Kth processed wafer in the first wafer group and the start time of processing the Kth processed wafer in the second wafer group, 1≤K≤N, and the average value of the N idle times is calculated to obtain the average idle time of the first wafer group and the second wafer group with adjacent start processing times. Since one wafer group corresponds to one processing parameter group, the processing parameter groups corresponding to the first wafer group and the second wafer group are different, and the average idle time is also different. One of the adjacent wafer groups corresponds to a combination of the processing parameter groups, and each of the processing There may be multiple adjacent wafer groups corresponding to the processing start time of the combination of parameter groups, that is, each adjacent wafer group corresponds to multiple average idle times. The medians of the corresponding average idle times of the multiple adjacent wafer groups are calculated to obtain multiple median idle times. Since the multiple adjacent wafer groups correspond to all combinations of the above processing parameter groups, the median idle times corresponding to the combinations of all the above processing parameter groups are obtained. The total idle times corresponding to all processing sequences of the wafer groups to be processed are calculated to obtain multiple total idle times. After the processing sequence is determined, all two adjacent wafer groups to be processed with corresponding processing sequences are matched with the corresponding combinations of the above processing parameter groups to obtain the corresponding median idle times. After calculating and matching all the median idle times, the above total idle time is obtained. One processing sequence corresponds to one total idle time.

[0047] It should be noted that the wafer group to be processed within the above-mentioned predetermined time is taken as a sample. The longer the above-mentioned predetermined time is, the more samples there are, the more accurate the above-mentioned estimated idle time is, and the greater the improvement in output efficiency will be achieved by the determined optimal processing sequence. In addition, the number of wafers in the above-mentioned first wafer group and the above-mentioned second wafer group is different, and N is the number of wafers in the wafer group with a smaller number of wafers.

[0048] In one embodiment of the present application, the processing technology of the machine includes multiple process units, the process units include multiple processes, the acquisition module includes an acquisition submodule, the acquisition submodule is used to acquire the average idle time of all two adjacent wafer groups within the predetermined time when the machine executes the target process unit for production, and obtain multiple average idle times, the target process unit is any one of the process units, the average idle time is the average value of at least one idle time, and the idle time is the time between the end time of processing the first wafer and the start time of processing the second wafer during the production process of the target process unit. Specifically, the process unit composed of multiple processes is used as a standard unit for processing, the processing start time is the time when the target process unit starts processing the wafer group, and the processing end time is the time when the target process unit ends processing the wafer group. Each process unit can determine an optimal processing sequence through the above-mentioned improvement method to improve the output efficiency of each process unit.

[0049] In one embodiment of the present application, Figure 2 As shown, the above-mentioned machine simultaneously executes two of the above-mentioned target process units, the two above-mentioned target process units are the same above-mentioned process unit, the above-mentioned first wafer group lot1 includes the third wafer lot1-w1, the fourth wafer lot1-w2 and the fifth wafer lot1-w3, the above-mentioned second wafer group lot2 includes the sixth wafer lot2-w1, the seventh wafer lot2-w2 and the eighth wafer lot2-w3, and the above-mentioned target process unit executed by the above-mentioned machine processes the above-mentioned third wafer lot1-w1, the above-mentioned sixth wafer lot2-w1 and the above-mentioned seventh wafer lot2-w2 respectively, and the above-mentioned target process unit executed by the above-mentioned machine processes the above-mentioned fourth wafer lot1-w2, the above-mentioned The fifth wafer lot1-w3 and the eighth wafer lot2-w3 are processed, and the average idle time is the average of the first idle time, the second idle time and the third idle time. The first idle time is the time between the processing start time t5 of the sixth wafer lot2-w1 and the processing end time t2 of the third wafer lot1-w1. The second idle time is the time between the processing start time t9 of the seventh wafer lot2-w2 and the processing end time t4 of the fourth wafer lot1-w2. The third idle time is the time between the processing start time t11 of the eighth wafer lot2-w3 and the processing end time t8 of the fifth wafer lot1-w3. Specifically, the time for the above-mentioned machine to simultaneously execute the processing of all wafer groups of the two above-mentioned target process units is T. The above-mentioned first wafer group lot1 and the above-mentioned second wafer group lot2 both have three wafer groups, that is, N=3, and the corresponding idle time is three. The above-mentioned first idle time T 1is the time between the processing start time t5 of the sixth wafer lot2-w1 and the processing end time t2 of the third wafer lot1-w1, that is, T 1 =t5-t2, the second idle time T 2 is the time between the processing start time t9 of the seventh wafer lot2-w2 and the processing end time t4 of the fourth wafer lot1-w2, that is, T 2 =t9-t4, the third idle time T 3 is the time between the processing start time t11 of the eighth wafer lot2-w3 and the processing end time t8 of the fifth wafer lot1-w3, that is, T 3 =t11-t8, the above average idle time T 平 is the first idle time T 1 , the second idle time T 2 and the third idle time T 3 The average value, T 平 =T 1 +T 2 +T 3 / 3.

[0050] In one embodiment of the present application, there are two processing parameter groups, namely a first processing parameter group and a second processing parameter group, the first calculation module includes a first calculation sub-module, a second calculation sub-module, a third calculation sub-module and a fourth calculation sub-module, wherein the first calculation sub-module is used to calculate the median of the average idle time of multiple first adjacent wafer groups to obtain a first median value, the first adjacent wafer group includes a third wafer group and a fourth wafer group, the processing parameter group corresponding to the third wafer group is the first processing parameter group, the processing parameter group corresponding to the fourth wafer group is the first processing parameter group, and the start processing time of the third wafer group is earlier than the start processing time of the fourth wafer group; the second calculation sub-module is used to calculate the median of the average idle time of multiple second adjacent wafer groups to obtain a second median value, the second adjacent wafer group includes a fifth wafer group and a sixth wafer group, the processing parameter group corresponding to the fifth wafer group is the second processing parameter group, and the processing parameter group corresponding to the sixth wafer group is the first processing parameter group. The group is the second processing parameter group, and the start processing time of the fifth wafer group is earlier than the start processing time of the sixth wafer group; the third calculation submodule is used to calculate the median of the average idle time of multiple third adjacent wafer groups to obtain a third median, the third adjacent wafer group includes the seventh wafer group and the eighth wafer group, the processing parameter group corresponding to the seventh wafer group is the first processing parameter group, the processing parameter group corresponding to the eighth wafer group is the second processing parameter group, and the start processing time of the seventh wafer group is earlier than the start processing time of the eighth wafer group; the fourth calculation submodule is used to calculate the median of the average idle time of multiple fourth adjacent wafer groups to obtain a fourth median, the fourth adjacent wafer group includes the ninth wafer group and the tenth wafer group, the processing parameter group corresponding to the ninth wafer group is the second processing parameter group, the processing parameter group corresponding to the tenth wafer group is the first processing parameter group, and the start processing time of the ninth wafer group is earlier than the start processing time of the tenth wafer group. Specifically, there are two processing parameter groups and four combinations of the processing parameter groups, corresponding to the first adjacent wafer group, the second adjacent wafer group, the third adjacent wafer group and the fourth adjacent wafer group. Taking the first adjacent wafer group as an example, the processing parameter group corresponding to the wafer group with an earlier start time in the first adjacent wafer group is the first processing parameter group, and the processing parameter group corresponding to the wafer group with a later start time in the first adjacent wafer group is the first processing parameter group. Multiple first adjacent wafer groups correspond to multiple average idle times, and the median of the multiple average idle times is taken to obtain the first median. For example, the multiple average idle times are 3S, 4S, 6S and 8S respectively, and the first median is 5S. Similarly, the second median corresponding to the second adjacent wafer group, the third median corresponding to the third adjacent wafer group and the fourth median corresponding to the fourth adjacent wafer group can be calculated.

[0051] In one embodiment of the present application, the above-mentioned wafer group to be processed includes a first wafer group to be processed, a second wafer group to be processed and a third wafer group to be processed, the above-mentioned processing parameter group corresponding to the above-mentioned first wafer group to be processed is the above-mentioned first processing parameter group, the above-mentioned processing parameter group corresponding to the above-mentioned second wafer group to be processed is the above-mentioned second processing parameter group, and the above-mentioned processing parameter group corresponding to the above-mentioned third wafer group to be processed is the above-mentioned first processing parameter group, and the above-mentioned second calculation module includes a fifth calculation sub-module, a sixth calculation sub-module, a seventh calculation sub-module, an eighth calculation sub-module, a ninth calculation sub-module and a tenth calculation sub-module, wherein the above-mentioned fifth calculation sub-module is used for, when the above-mentioned processing order is to process the above-mentioned first wafer group to be processed, the above-mentioned second wafer group to be processed and the above-mentioned third wafer group to be processed in sequence, the above-mentioned total idle time is the sum of the above-mentioned third median and the above-mentioned fourth median; the above-mentioned sixth calculation sub-module is used for, when the above-mentioned processing order is to process the above-mentioned first wafer group to be processed, the above-mentioned third wafer group to be processed and the above-mentioned second wafer group to be processed in sequence, the above-mentioned total idle time is the sum of the first median and the third median; the seventh calculation submodule is used for, when the processing order is to sequentially process the second wafer group to be processed, the first wafer group to be processed and the third wafer group to be processed, the total idle time is the sum of the fourth median and the first median; the eighth calculation submodule is used for, when the processing order is to sequentially process the second wafer group to be processed, the third wafer group to be processed and the first wafer group to be processed, the total idle time is the sum of the fourth median and the first median; the ninth calculation submodule is used for, when the processing order is to sequentially process the third wafer group to be processed, the first wafer group to be processed and the second wafer group to be processed, the total idle time is the sum of the first median and the third median; the tenth calculation submodule is used for, when the processing order is to sequentially process the third wafer group to be processed, the second wafer group to be processed and the first wafer group to be processed, the total idle time is the sum of the third median and the fourth median.Specifically, taking the three wafer groups to be processed and the two processing parameter groups as an example, the three wafer groups to be processed have 6 processing sequences. When the processing sequence is to sequentially process the first wafer group to be processed, the second wafer group to be processed and the third wafer group to be processed, since the processing parameter group corresponding to the first wafer group to be processed is the first processing parameter group, and the processing parameter group corresponding to the second wafer group to be processed is the second processing parameter group, the estimated idle time between the first wafer group to be processed and the second wafer group to be processed is the third median, and the processing parameter group corresponding to the second wafer group to be processed is the third median. is the second processing parameter group, and the processing parameter group corresponding to the third group of wafers to be processed is the first processing parameter group. Therefore, the estimated idle time between the second group of wafers to be processed and the third group of wafers to be processed is the fourth median, and the total idle time corresponding to this processing sequence is the sum of the third median and the fourth median. Similarly, the total idle times corresponding to the remaining five processing sequences are the sum of the first median and the third median, the sum of the fourth median and the first median, the sum of the fourth median and the first median, the sum of the first median and the third median, and the sum of the third median and the fourth median.

[0052] An embodiment of the present application further provides a processing system, including a machine and a device for improving the production efficiency of the machine, wherein the device for improving the production efficiency of the machine includes a device for executing any one of the above methods.

[0053] The above-mentioned processing system includes a machine and a device for improving the production efficiency of the machine. The calculation unit calculates the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times. The total idle time is the sum of the estimated idle times corresponding to all two adjacent wafer groups to be processed. The estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed one after another. The determination unit determines the processing sequence corresponding to the shortest total idle time as the optimal processing sequence. The control unit controls the machine to process the wafer group to be processed according to the optimal processing sequence. The device calculates the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times, compares the multiple total idle times to determine that the processing sequence corresponding to the shortest total idle time is the optimal processing sequence, and controls the machine to process the wafer group to be processed according to the optimal processing sequence, thereby reducing the total idle time and improving the production efficiency of the machine, and solving the problem of low output efficiency of the machine due to unreasonable processing sequence in the prior art.

[0054] The above-mentioned device for improving machine production efficiency includes a processor and a memory. The above-mentioned calculation unit, the above-mentioned determination unit and the control unit are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize corresponding functions.

[0055] The processor includes a kernel, which retrieves the corresponding program unit from the memory. One or more kernels can be set, and the problem of low output efficiency of the machine due to unreasonable processing sequence in the prior art can be solved by adjusting kernel parameters.

[0056] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0057] An embodiment of the present invention provides a computer-readable storage medium on which a program is stored. When the program is executed by a processor, the above method is implemented.

[0058] An embodiment of the present invention provides a processor, and the processor is used to run a program, wherein the method is executed when the program is run.

[0059] An embodiment of the present invention provides a device, the device including a processor, a memory, and a program stored in the memory and executable on the processor, and when the processor executes the program, at least the following steps are implemented:

[0060] Step S101, calculating the total idle time corresponding to all processing sequences of the wafer group to be processed, and obtaining a plurality of the total idle times, wherein the total idle time is the sum of the estimated idle time corresponding to two adjacent wafer groups to be processed in all processing sequences, and the estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed successively;

[0061] Step S102, determining the processing sequence corresponding to the shortest total idle time as the optimal processing sequence;

[0062] Step S103 , controlling the machine to process the above-mentioned wafer group to be processed according to the above-mentioned optimal processing sequence.

[0063] The devices in this article can be servers, PCs, PADs, mobile phones, etc.

[0064] The present application also provides a computer program product, which, when executed on a data processing device, is suitable for executing a program for initializing at least the following method steps:

[0065] Step S101, calculating the total idle time corresponding to all processing sequences of the wafer group to be processed, and obtaining a plurality of the total idle times, wherein the total idle time is the sum of the estimated idle time corresponding to two adjacent wafer groups to be processed in all processing sequences, and the estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed successively;

[0066] Step S102, determining the processing sequence corresponding to the shortest total idle time as the optimal processing sequence;

[0067] Step S103 , controlling the machine to process the above-mentioned wafer group to be processed according to the above-mentioned optimal processing sequence.

[0068] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0069] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the above-mentioned units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0070] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0071] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0072] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a computer-readable storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present invention. The aforementioned computer-readable storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0073] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0074] 1) In the method for improving the production efficiency of the machine of the present application, first, the total idle time corresponding to all processing sequences of the wafer group to be processed is calculated to obtain multiple total idle times, and the total idle time is the sum of the estimated idle times corresponding to all two adjacent wafer groups to be processed, and the estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed one after another; then, the processing sequence corresponding to the shortest total idle time is determined as the optimal processing sequence; finally, the machine is controlled to process the wafer group to be processed according to the optimal processing sequence. This method calculates the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times, compares the multiple total idle times to determine that the processing sequence corresponding to the shortest total idle time is the optimal processing sequence, and controls the machine to process the wafer group to be processed according to the optimal processing sequence, thereby reducing the total idle time to improve the production efficiency of the machine, and solving the problem of low output efficiency of the machine due to unreasonable processing sequence in the prior art.

[0075] 2) In the device for improving the production efficiency of the machine of the present application, the calculation unit calculates the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times, and the total idle time is the sum of the estimated idle times corresponding to all two adjacent wafer groups to be processed, and the estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed one after another; the determination unit determines the processing sequence corresponding to the shortest total idle time as the optimal processing sequence; the control unit controls the machine to process the wafer group to be processed according to the optimal processing sequence. The device calculates the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times, compares the multiple total idle times to determine that the processing sequence corresponding to the shortest total idle time is the optimal processing sequence, and controls the machine to process the wafer group to be processed according to the optimal processing sequence, thereby reducing the total idle time and improving the production efficiency of the machine, and solving the problem of low output efficiency of the machine due to unreasonable processing sequence in the prior art.

[0076] 3) In the processing system of the present application, there are included a machine and a device for improving the production efficiency of the machine. The calculation unit calculates the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times. The total idle time is the sum of the estimated idle times corresponding to all two adjacent wafer groups to be processed. The estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed one after another. The determination unit determines the processing sequence corresponding to the shortest total idle time as the optimal processing sequence. The control unit controls the machine to process the wafer group to be processed according to the optimal processing sequence. The device calculates the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times, compares the multiple total idle times to determine that the processing sequence corresponding to the shortest total idle time is the optimal processing sequence, and controls the machine to process the wafer group to be processed according to the optimal processing sequence, thereby reducing the total idle time and improving the production efficiency of the machine, and solving the problem of low output efficiency of the machine due to unreasonable processing sequence in the prior art.

[0077] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for improving machine production efficiency, characterized in that: include: Calculate the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain a plurality of the total idle times, wherein the total idle time is the sum of the estimated idle times corresponding to two adjacent wafer groups to be processed in all processing sequences, and the estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed successively; Determine the processing sequence corresponding to the shortest total idle time as the optimal processing sequence; Controlling a machine to process the wafer group to be processed according to the optimal processing sequence, calculating the total idle time corresponding to all processing sequences of the wafer group to be processed, and obtaining a plurality of the total idle times, including: obtaining at least one average idle time within a predetermined time, the average idle time being an average of N idle times, the idle time being a time between a processing end time of a Kth processed wafer in a first wafer group and a processing start time of a Kth processed wafer in a second wafer group, the processing start time of the Kth processed wafer in the first wafer group being earlier than the processing start time of the Kth processed wafer in the second wafer group, the first wafer group and the second wafer group both being composed of N wafers, wherein N≥1, 1≤K≤N, and the start processing time of the first wafer group and the start processing time of the second wafer group being adjacent; calculating a plurality of corresponding The median of the corresponding average idle time of the adjacent wafer group is obtained to obtain multiple median idle times, the median idle time corresponds to the adjacent wafer group one by one, the adjacent wafer group includes two wafer groups with adjacent start processing time and corresponding to a processing parameter group respectively, one adjacent wafer group corresponds to a combination of the processing parameter groups, the combinations of two processing parameter groups corresponding to any two adjacent wafer groups are different, and multiple adjacent wafer groups correspond to all combinations of the processing parameter groups; the total idle time corresponding to all processing sequences of the wafer group to be processed is calculated to obtain multiple total idle times, the total idle time is the sum of the expected idle times corresponding to the two adjacent wafer groups to be processed in all processing sequences, and the expected idle time is the median idle time of the adjacent wafer groups corresponding to the two adjacent wafer groups to be processed.

2. The method according to claim 1, characterized in that The processing technology of the machine includes multiple process units, each of which includes multiple processes. Within a predetermined time, the average idle time of all two adjacent wafer groups is obtained to obtain multiple average idle times, including: Within the predetermined time when the machine executes the target process unit for production, the average idle time of all two adjacent wafer groups is obtained to obtain a plurality of the average idle times, wherein the target process unit is any one of the process units, the average idle time is the average value of at least one idle time, and the idle time is the time between the end time of processing of the Kth processed wafer in the first wafer group and the start time of processing of the Kth processed wafer in the second wafer group during the execution of the target process unit for production.

3. The method according to claim 2, characterized in that The machine simultaneously executes two target process units, which are the same process unit. The first wafer group includes a third wafer, a fourth wafer and a fifth wafer, and the second wafer group includes a sixth wafer, a seventh wafer and an eighth wafer. One target process unit executed by the machine processes the third wafer, the sixth wafer and the seventh wafer respectively, and another target process unit executed by the machine processes the fourth wafer, the fifth wafer and the eighth wafer respectively. The average idle time is an average of the first idle time, the second idle time and the third idle time. The first idle time is the time between the start time of processing the sixth wafer and the end time of processing the third wafer. The second idle time is the time between the start time of processing the seventh wafer and the end time of processing the fourth wafer. The third idle time is the time between the start time of processing the eighth wafer and the end time of processing the fifth wafer.

4. The method according to claim 1, characterized in that: There are two processing parameter groups, namely a first processing parameter group and a second processing parameter group. The median of the corresponding idle time of multiple adjacent wafer groups is calculated to obtain multiple median idle times, including: Calculating the median of average idle time of a plurality of first adjacent wafer groups to obtain a first median, wherein the first adjacent wafer groups include a third wafer group and a fourth wafer group, the processing parameter group corresponding to the third wafer group is the first processing parameter group, the processing parameter group corresponding to the fourth wafer group is the first processing parameter group, and the start processing time of the third wafer group is earlier than the start processing time of the fourth wafer group; Calculating a median of average idle time of a plurality of second adjacent wafer groups to obtain a second median, wherein the second adjacent wafer groups include a fifth wafer group and a sixth wafer group, the processing parameter group corresponding to the fifth wafer group is the second processing parameter group, the processing parameter group corresponding to the sixth wafer group is the second processing parameter group, and a start processing time of the fifth wafer group is earlier than a start processing time of the sixth wafer group; Calculating the median of the average idle time of multiple third adjacent wafer groups to obtain a third median, the third adjacent wafer groups include a seventh wafer group and an eighth wafer group, the processing parameter group corresponding to the seventh wafer group is the first processing parameter group, the processing parameter group corresponding to the eighth wafer group is the second processing parameter group, and the start processing time of the seventh wafer group is earlier than the start processing time of the eighth wafer group; Calculate the median of the average idle time of multiple fourth adjacent wafer groups to obtain a fourth median, the fourth adjacent wafer groups include a ninth wafer group and a tenth wafer group, the processing parameter group corresponding to the ninth wafer group is the second processing parameter group, the processing parameter group corresponding to the tenth wafer group is the first processing parameter group, and the start processing time of the ninth wafer group is earlier than the start processing time of the tenth wafer group.

5. The method according to claim 4, characterized in that The wafer group to be processed includes a first wafer group to be processed, a second wafer group to be processed and a third wafer group to be processed, the processing parameter group corresponding to the first wafer group to be processed is the first processing parameter group, the processing parameter group corresponding to the second wafer group to be processed is the second processing parameter group, and the processing parameter group corresponding to the third wafer group to be processed is the first processing parameter group, and the total idle time corresponding to all processing sequences of the wafer group to be processed is calculated to obtain a plurality of the total idle times, including: In a case where the processing sequence is to sequentially process the first to-be-processed wafer group, the second to-be-processed wafer group, and the third to-be-processed wafer group, the total idle time is the sum of the third median value and the fourth median value; In a case where the processing sequence is to sequentially process the first to-be-processed wafer group, the third to-be-processed wafer group, and the second to-be-processed wafer group, the total idle time is the sum of the first median value and the third median value; In the case where the processing sequence is to sequentially process the second wafer group to be processed, the first wafer group to be processed, and the third wafer group to be processed, the total idle time is the sum of the fourth median value and the first median value; In a case where the processing sequence is to sequentially process the second wafer group to be processed, the third wafer group to be processed, and the first wafer group to be processed, the total idle time is the sum of the fourth median value and the first median value; In the case where the processing sequence is to sequentially process the third wafer group to be processed, the first wafer group to be processed, and the second wafer group to be processed, the total idle time is the sum of the first median value and the third median value; In a case where the processing sequence is to sequentially process the third wafer group to be processed, the second wafer group to be processed, and the first wafer group to be processed, the total idle time is the sum of the third median value and the fourth median value.

6. A device for improving machine production efficiency, characterized in that: include: A calculation unit, used for calculating the total idle time corresponding to all processing sequences of the wafer group to be processed, and obtaining a plurality of the total idle times, wherein the total idle time is the sum of the estimated idle time corresponding to two adjacent wafer groups to be processed in all processing sequences, and the estimated idle time is the estimated waiting time for the two adjacent wafer groups to be processed to be processed successively; A determination unit, configured to determine the processing sequence corresponding to the shortest total idle time as the optimal processing sequence; A control unit is used to control the machine to process the wafer group to be processed according to the optimal processing sequence, the calculation unit includes an acquisition module, a first calculation module and a second calculation module, wherein the acquisition module is used to obtain at least one average idle time within a predetermined time, the average idle time is the average value of N idle times, the idle time is the time between the processing end time of the Kth processed wafer in the first wafer group and the processing start time of the Kth processed wafer in the second wafer group, the processing start time of the Kth processed wafer in the first wafer group is earlier than the processing start time of the Kth processed wafer in the second wafer group, the first wafer group and the second wafer group are both composed of N wafers, wherein N≥1, 1≤K≤N, and the start processing time of the first wafer group and the start processing time of the second wafer group are adjacent; the first calculation module is used to calculate The median of the average idle time corresponding to multiple adjacent wafer groups is obtained to obtain multiple median idle times, and the median idle time corresponds to the adjacent wafer groups one by one. The adjacent wafer groups include two wafer groups with adjacent start processing time and respectively corresponding to a processing parameter group, one adjacent wafer group corresponds to a combination of the processing parameter groups, the combinations of two processing parameter groups corresponding to any two adjacent wafer groups are different, and multiple adjacent wafer groups correspond to all combinations of the processing parameter groups; the second calculation module is used to calculate the total idle time corresponding to all processing sequences of the wafer group to be processed to obtain multiple total idle times, and the total idle time is the sum of the expected idle times corresponding to two adjacent wafer groups to be processed in all processing sequences, and the expected idle time is the median idle time of the adjacent wafer groups corresponding to two adjacent wafer groups to be processed.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein the program executes the method of any one of claims 1 to 5.

8. A processor, characterized in that: The processor is used to run a program, wherein the program executes the method according to any one of claims 1 to 5 when running.

9. A processing system, comprising a machine and a device for improving the production efficiency of the machine, characterized in that: The device for improving machine production efficiency includes a device for executing the method described in any one of claims 1 to 5.

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