MOS transistor manufacturing method and MOS transistor

Abstract

The invention provides a MOS transistor manufacturing method and a MOS transistor. A substrate is provided, a plurality of raised STIs are formed on the substrate, trench areas between the STIs are respectively defined as a low-voltage device area and a medium-voltage device area, a gate oxide layer is grown in the trench area, and then a first protective layer is formed on the gate oxide layer; a first photoresist is covered on the surface of the first protective layer, the first protective layer of the gate oxide layer is exposed by photolithography, and part of the STIs on both sides of the gate oxide layer are exposed; at the same time, part of the STIs on both sides of the gate oxide layer are exposed, and the exposed STIs are etched; the first photoresist and the first protective layer are removed; a second protective layer is grown; the exposed second protective layer is etched, and a polysilicon groove is continuously etched on the substrate; a connecting layer is grown at the polysilicon groove; the second protective layer and the second photoresist are removed by etching to obtain a MOS transistor, so as to avoid defects and improve the reliability and yield of the medium-voltage device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a MOS transistor manufacturing method and a MOS transistor. Background Art

[0002] The existing gate oxide process is to directly grow an oxide layer on a silicon substrate. However, due to the thicker gate oxide thickness of medium-voltage MOS tubes, the medium-voltage gate oxide grown according to the existing process will be higher than that of normal-voltage devices. After the dielectric layer zero chemical mechanical polishing process, the remaining height of the pseudo gate in the medium-voltage device area is relatively low, which will affect the formation of the metal gate and make the metal gate in the medium-voltage device area thinner. Due to the small overall area of ​​medium-voltage devices, in extreme cases, after the dielectric layer zero chemical mechanical polishing process, the pseudo gate in the medium-voltage device area is completely ground away, and a metal gate cannot be formed, thereby damaging the yield and reliability of the product.

[0003] The introduction of the substrate (Wafer) before entering the IOX cycle is as follows Fig. 9 As shown in FIG. 1 , the width of the STI oxide covering the corners of the medium-voltage gate oxide is 118.9A and the height is 105.3A. This part of the oxide will block the etching of the silicon below, resulting in silicon protrusions at the corners, such as Fig.10 As shown in Figure 2. During the growth of the medium-voltage gate oxide, the silicon at the corners of the medium-voltage gate oxide is difficult to be completely oxidized, and eventually a "cat's ear" defect is formed (such as Fig.11 This will cause the thickness of the medium-voltage gate oxide corners to be thinner, making it easy to break down after voltage is applied. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the deficiencies of the prior art, the present invention provides a MOS transistor manufacturing method and a MOS transistor, which solves the problem that the gate oxide corner thickness is relatively thin in semiconductor integrated circuit manufacturing and is easily broken down after voltage is applied.

[0006] (II) Technical solution

[0007] To achieve the above objectives, the present invention is implemented by the following technical solutions: A method for manufacturing a MOS transistor, comprising at least the following steps:

[0008] Step 1, providing a substrate, forming a plurality of raised STIs on the substrate, wherein the trench regions between the STIs are respectively defined as a low-voltage device region and a medium-voltage device region, growing a gate oxide layer in the trench region, and then forming a first protective layer on the gate oxide layer; covering the surface of the first protective layer with a first photoresist, exposing the first protective layer of the gate oxide layer by photolithography, and simultaneously exposing portions of the STIs on both sides of the gate oxide layer;

[0009] Step 2: etching the exposed STI, wherein the STI is etched to a first width and a first depth;

[0010] Step 3: removing the first photoresist and the first protective layer;

[0011] Step 4: growing a second protective layer;

[0012] Step 5: Covering the surface of the medium-voltage gate oxide region with a second photoresist by photolithography to partially expose the second protective layer, etching the exposed second protective layer, wherein the second protective layer is etched to a second width and a second depth, and etching the substrate to form a polysilicon groove;

[0013] Step 6: growing a connection layer at the polysilicon groove;

[0014] Step seven: remove the second protective layer and the second photoresist by etching.

[0015] Optionally, the first width is 80 angstroms to 120 angstroms, and the first depth is 80 angstroms to 120 angstroms.

[0016] Optionally, the second protective layer is a silicon nitride layer with a thickness of 200 angstroms.

[0017] Optionally, in the step 2, the first photoresist is hardened by using at least one of an Ash process and a Bake process before etching, and then wet cleaned.

[0018] Optionally, in the step 2, etching is performed using at least one of a Certas process and an Etch process.

[0019] Optionally, in step five, the second width is greater than the first width, and the second depth is etched to below the substrate.

[0020] Optionally, in step seven, the second photoresist is removed by wet etching, and then the second protective layer is removed.

[0021] Optionally, materials of the first protective layer and the second protective layer are both silicon nitride.

[0022] Optionally, the ratio of the depth of the polysilicon groove to the thickness of the gate oxide layer in the medium-voltage gate oxide region is approximately 0.54:1.

[0023] Optionally, the connection layer is generated by thermal oxidation of the polysilicon groove in a high-temperature furnace tube, with a growth temperature of 800 to 900° C. and a growth thickness of 180 angstroms to 220 angstroms.

[0024] A MOS transistor, comprising:

[0025] substrate;

[0026] A plurality of raised STIs located on the substrate, wherein the trench regions between the STIs are respectively defined as a low voltage device region and a medium voltage device region;

[0027] A connection layer is located in the groove area at the medium voltage device area, wherein the edge thickness of the connection layer is consistent with the overall thickness.

[0028] Optionally, a MOS transistor can be manufactured using the manufacturing method of any of the aforementioned steps.

[0029] (III) Beneficial effects

[0030] The present invention reduces the thickness of the STI oxide covering the edge of the medium voltage gate oxide by adding a pre-etching process for the STI at the IO boundary after the STI CMP, so that the silicon at the edge can be removed cleanly later, avoiding the formation of "cat ear" defects, avoiding the problem that the thickness of the medium voltage gate oxide edge is thin and is easily broken down after voltage is applied, and improving the reliability and yield of the medium voltage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of defining a medium voltage gate oxide region by photolithography provided in an embodiment of the present application;

[0032] Figure 2 This is a schematic diagram of etching the STI oxide covering the edge of the medium voltage gate oxide in an embodiment of the present application;

[0033] Figure 3 This is a schematic diagram of an embodiment of the present application after removing the photoresist and the silicon nitride film;

[0034] Figure 4 A schematic diagram of growing a silicon nitride film as a hard mask layer on a wafer in a high-temperature furnace tube according to an embodiment of the present application;

[0035] Figure 5 This is a schematic diagram of opening the silicon nitride film and etching to a certain thickness in an embodiment of the present application;

[0036] Figure 6 A schematic diagram of growing gate oxide in a medium-voltage gate oxide region by high-temperature furnace tube oxidation in an embodiment of the present application;

[0037] Figure 7 A schematic diagram of removing the silicon nitride film of the hard mask layer according to an embodiment of the present application;

[0038] Figure 8 Schematic diagram of the dielectric layer zero chemical mechanical polishing process;

[0039] Fig. 9 Schematic diagram of the substrate before entering the IOX cycle;

[0040] Fig.10 Schematic diagram of edge silicon protrusion;

[0041] Fig.11 Schematic diagram of the formation of "cat's ear" defects in medium voltage gate oxide growth;

[0042] Fig.12 Schematic diagram of the process improvement.

[0043] Among them, 1-substrate, 2-STI, 3-gate oxide layer, 4-first photoresist, 5-low-voltage device area, 6-first protective layer, 7-medium-voltage device area, 8-connection layer, 9-second protective layer, 10-second photoresist, 11-polysilicon groove. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] Example

[0046] The MOS transistor manufacturing method of the present invention specifically comprises the following process steps:

[0047] Step 1, please refer to Figure 1 , providing a substrate 1, forming a plurality of raised STI2 on the substrate 1, the groove areas between the STI2 are respectively defined as a low voltage device area 5 and a medium voltage device area 7, growing a gate oxide layer 3 in the groove area, and then forming a first protective layer 6 on the gate oxide layer 3, the first protective layer 6 being flush with the top surface of the STI2 after undergoing STI CMP; covering the surface of the first protective layer 6 with a first photoresist 4 by photolithography technology, exposing the first protective layer 6 in the gate oxide layer 3 area at the medium voltage device area 7 by photolithography, and exposing part of the STI2 on both sides of the gate oxide layer 3 area.

[0048] Step 2, please refer to Figure 2 , etching the exposed STI2, the etched width of STI2 is a first width, and the depth is a first depth; specifically, etching is performed on STI2 by at least one of the Certas process and the Etch process, the first width is greater than IO AA by 80 angstroms to 120 angstroms, and the width can make the IO AA in the IO device open after etching, and here, if the IO AA and the IO STI2 area are opened at the same time, a gate oxide is formed after the gate oxide is formed. Fig.11 The cat ear defect shown in the figure can be avoided by etching a portion of STI2 that is larger than IOAA. Fig. 9 The STI2 cover layer above the edge AA at the circled position. If there is such a cover layer, the polysilicon at the edge AA will protrude after etching due to the blocking of the cover layer. Fig.10 As shown in the circled position, this part of the protruding polysilicon is difficult to be fully oxidized during the oxidation process of the gate oxide layer 3, thus forming Fig.11 It should be understood that the value range here is the preferred solution in this embodiment and can also be adjusted according to actual needs. The first depth is 80 angstroms to 120 angstroms, and then the first protective layer 6 and the first photoresist 4 are removed to obtain the following Figure 3 In the structure shown in FIG. 1 , a double-step structure is formed at the edge of the STI2 near the trench region, wherein the etching depth of the STI2 does not contact the gate oxide layer 3 at the trench region. The double-step structure will cause loss in subsequent operations such as flushing, thereby forming a single-step structure. The width of the newly formed trench region is greater than the width of the original trench region. After the second protective layer 9 is grown on the top surface of the substrate 1, the following is obtained. Figure 4 The structure shown;

[0049] Furthermore, the first protective layer 6 and the second protective layer 9 are both made of silicon nitride material.

[0050] Step three, removing the first photoresist 4 and the first protective layer 6 by wet etching;

[0051] Step 4, growing a second protective layer 9 with a thickness of 200 angstroms;

[0052] Step 5, please refer to Figure 5 , a second photoresist 10 is covered on the surface of the medium voltage gate oxide region, a portion of the second protective layer 9 is exposed by photolithography, and the exposed second protective layer 9 is etched, the second protective layer 9 is etched to a second width, the second width is greater than the first width, and a new double-step structure is formed after etching, and the substrate 1 is further etched downward to form a polysilicon groove 11, and the ratio of the thickness of the polysilicon groove 11 to the thickness of the gate oxide layer 3 of the medium voltage device region 7 is about 0.54:1;

[0053] Step 6: Please refer to Figure 6 , a connection layer 8 is grown at the polysilicon groove 11, and the connection layer 8 is generated by thermal oxidation of the polysilicon groove 11 in a high-temperature furnace tube, with a growth temperature of 800° C. to 900° C. and a growth thickness of 180 angstroms to 220 angstroms;

[0054] Step 7. Please refer to Figure 7 , the second protective layer 9 and the second photoresist 10 are removed by etching.

[0055] A MOS transistor can be manufactured using the aforementioned manufacturing method, comprising:

[0056] Substrate 1;

[0057] A plurality of raised STIs 2 located on the substrate 1, wherein the trench areas between the STIs 2 are respectively defined as a low voltage device area 5 and a medium voltage device area 7;

[0058] The connection layer 8 is located in the groove area of ​​the medium voltage device area 7, and the edge thickness of the connection layer is consistent with the overall thickness.

[0059] After STI2 CMP, a pre-etching process is added to the STI2 at the IO boundary, which reduces the thickness of the STI2 oxide covering the edge of the gate oxide layer 3 of the medium voltage device area 7, so that the silicon at the edge can be removed cleanly later to avoid defects.

[0060] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0061] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements all fall within the scope of the present invention to be protected.

Claims

1. A method for manufacturing a MOS transistor, characterized in that: At least the following steps are included: Step 1, providing a substrate, forming a plurality of raised STIs on the substrate, wherein the trench regions between the STIs are respectively defined as a low-voltage device region and a medium-voltage device region, growing a gate oxide layer in the trench region, and then forming a first protective layer on the gate oxide layer; covering the surface of the first protective layer with a first photoresist, exposing the first protective layer of the gate oxide layer by photolithography, and simultaneously exposing portions of the STIs on both sides of the gate oxide layer; Step 2: etching the exposed STI, wherein the STI is etched to a first width and a first depth; Step 3: removing the first photoresist and the first protective layer; Step 4: growing a second protective layer; Step 5, covering the surface of the medium-voltage gate oxide region with a second photoresist, exposing a portion of the second protective layer by photolithography, etching the exposed second protective layer, wherein the etched width of the second protective layer is a second width, and continuing to etch the substrate to form a polysilicon groove; Step 6: growing a connection layer at the polysilicon groove; Step seven: remove the second protective layer and the second photoresist by etching.

2. A method for manufacturing a MOS transistor according to claim 1, characterized in that: The first width is 80 angstroms to 120 angstroms, and the first depth is 80 angstroms to 120 angstroms.

3. A method for manufacturing a MOS transistor according to claim 1, characterized in that: The second protective layer is a silicon nitride layer with a thickness of 200 angstroms.

4. The method for manufacturing a MOS transistor according to claim 1, characterized in that: In the step 2, the first photoresist is hardened by using at least one of an Ash process and a Bake process before etching, and then wet cleaned.

5. The method for manufacturing a MOS transistor according to claim 1, characterized in that: In the step 2, etching is performed by using at least one of a Certas process and an Etch process.

6. A method for manufacturing a MOS transistor according to claim 1, characterized in that: In the step five, the second width is greater than the first width and less than the width of the STI.

7. A method for manufacturing a MOS transistor according to claim 1, characterized in that: In the step seven, the second photoresist is removed by wet etching, and then the second protective layer is removed.

8. The method for manufacturing a MOS transistor according to claim 1, characterized in that: The materials of the first protective layer and the second protective layer are both silicon nitride.

9. The method for manufacturing a MOS transistor according to claim 1, characterized in that: The ratio of the depth of the polysilicon groove to the thickness of the gate oxide layer is approximately 0.54:

1.

10. The method for manufacturing a MOS transistor according to claim 1, characterized in that: The connection layer is generated by thermal oxidation of the polysilicon groove in a high-temperature furnace tube, with a growth temperature of 800° C. to 900° C. and a growth thickness of 180 angstroms to 220 angstroms.

11. A MOS transistor manufactured by a MOS transistor manufacturing method according to any one of claims 1 to 10, characterized in that: include: substrate; A plurality of raised STIs located on the substrate, wherein the trench regions between the STIs are respectively defined as a low voltage device region and a medium voltage device region; A connection layer is located in the trench region at the medium voltage device region.

12. The MOS transistor according to claim 11, wherein: The edge thickness of the connecting layer is consistent with the overall thickness.

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