Protection Circuit

Abstract

The present invention provides a protection circuit for preventing an electrostatic discharge current from entering a core circuit. The protection circuit of the present invention includes a detection circuit, a current release element, a first transistor and a second transistor. The detection circuit is coupled between a first contact pad and a second contact pad to detect whether an electrostatic discharge event occurs. When an electrostatic discharge event occurs, the detection circuit sets a detection signal to a preset level. When the detection signal is at the preset level, the current release element is turned on to allow the electrostatic discharge current to flow. The first transistor is coupled between the core circuit and the second contact pad. The second transistor is coupled between the first transistor and the second contact pad. When the detection signal is at the preset level, the second transistor is turned on to turn off the first transistor.

Description

Technical Field

[0001] The present invention relates to a protection circuit, and more particularly to a protection circuit for preventing an electrostatic discharge (ESD) current from flowing into a core circuit. Background Art

[0002] Component damage caused by electrostatic discharge (ESD) has become one of the most important reliability issues for integrated circuit products. Especially as the size continues to shrink to the sub-micron level, the gate oxide layer of metal oxide semiconductors is getting thinner and thinner, and integrated circuits are more susceptible to damage due to electrostatic discharge. In general industrial standards, the input and output pins (I / O pins) of integrated circuit products must be able to pass the human body model electrostatic discharge test of more than 2000 volts and the mechanical model electrostatic discharge test of more than 200 volts. Therefore, in integrated circuit products, electrostatic discharge protection components must be set near all input and output pads to protect the internal core circuit from electrostatic discharge current. Summary of the invention

[0003] One embodiment of the present invention provides a protection circuit for preventing an electrostatic discharge current from entering a core circuit. The protection circuit of the present invention includes a detection circuit, a current release element, a first transistor and a second transistor. The detection circuit is coupled between a first contact pad and a second contact pad to detect whether an electrostatic discharge event occurs. When an electrostatic discharge event occurs, the detection circuit sets a detection signal to a preset level. The current release element is coupled between the first and second contact pads. When the detection signal is at the preset level, the current release element is turned on to allow the electrostatic discharge current to flow through. The first transistor is coupled between the core circuit and the second contact pad. The second transistor is coupled between the first transistor and the second contact pad. When the detection signal is at the preset level, the second transistor is turned on to turn off the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a schematic diagram of an operating circuit of the present invention.

[0005] Figure 2 FIG. 4 is another schematic diagram of the operating circuit of the present invention.

[0006] Figure 3 FIG. 4 is another schematic diagram of the operating circuit of the present invention.

[0007] Figure 4 Schematic diagram of the detection circuit of the present invention.

[0008] Figure 5 FIG. 4 is another schematic diagram of the detection circuit of the present invention.

[0009] Reference numerals:

[0010] 100, 200, 300: Operation circuit

[0011] 102, 202, 302: core circuit

[0012] 104, 204, 304: Protection circuit

[0013] 106, 108, 206, 208, 306, 308: Contact pads

[0014] 110, 210, 310, 400, 500: Detection circuit

[0015] 112, 212, 312: Current release element

[0016] 114, 116, 214, 216, 214, 216, transistors

[0017] V1: Detection signal

[0018] V2~V5:Control signal

[0019] Nesd, 220, 320, 326, 412, 512: N-type transistors

[0020] 222, 322, 328, 410, 510: P-type transistors

[0021] 218, 318, 324, 408, 508: Inverting circuit

[0022] 402, 502: resistance

[0023] 404, 504: Capacitor

[0024] 414, 514: common nodes DETAILED DESCRIPTION

[0025] In order to make the purpose, features and advantages of the present invention more clearly understood, the following embodiments are specifically cited and described in detail with reference to the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each element in the embodiment is for illustrative purposes and is not intended to limit the present invention. In addition, some of the figure numbers in the embodiments are repeated for the purpose of simplifying the description and do not mean the correlation between different embodiments.

[0026] Figure 11 is a schematic diagram of an operating circuit of the present invention. As shown in the figure, the operating circuit 100 includes a core circuit 102 and a protection circuit 104. The present invention does not limit the type of the core circuit 102. In one possible embodiment, the core circuit 102 is a non-volatile memory, such as a one-time programmable chip. In other embodiments, the core circuit 102 includes a plurality of metal fuses, a plurality of poly-fuses, a plurality of metal anti-fuses, or a plurality of poly anti-fuses.

[0027] The protection circuit 104 is coupled between the contact pads 106 and 108, and determines whether an electrostatic discharge event occurs. When an electrostatic discharge event occurs at the contact pad 106 and the contact pad 108 receives a ground voltage, the protection circuit 104 enters a protection mode. In the protection mode, the protection circuit 104 releases an electrostatic discharge current from the contact pad 106 to the contact pad 108 to prevent the electrostatic discharge current from entering the core circuit 102 from the contact pad 106. At this time, the protection circuit 104 may command the core circuit 102 to stop operating. The present invention does not limit how the protection circuit 104 commands the core circuit 102 to stop operating. In a possible embodiment, the protection circuit 104 stops providing an operating voltage (such as a ground voltage) to the core circuit 102. Since the core circuit 102 lacks an operating voltage, it cannot operate.

[0028] When the contact pad 106 receives a first operating voltage (e.g., 5V) and the contact pad 108 receives a second operating voltage (e.g., 0V), the protection circuit 104 enters a normal mode. In the normal mode (no electrostatic discharge event), the protection circuit 104 activates the core circuit 102 so that the core circuit 102 operates normally. In one possible embodiment, the protection circuit 104 re-provides an operating voltage (e.g., a ground voltage) to the core circuit 102. In some embodiments, the core circuit 102 may perform a write operation.

[0029] In the present embodiment, the protection circuit 104 includes a detection circuit 110, a current release element 112, transistors 114 and 116. The detection circuit 110 is coupled between the contact pads 106 and 108 to determine whether an electrostatic discharge event occurs. For example, when the potential of the contact pad 106 rises instantaneously and the contact pad 108 is coupled to the ground, it indicates that an electrostatic discharge event occurs. Therefore, the detection circuit 110 sets a detection signal V1 to a first preset level, such as a low level or a high level. In other embodiments, when the potential of the contact pad 108 rises instantaneously and the contact pad 106 is coupled to the ground, the detection circuit 110 also sets the detection signal V1 to the first preset level.

[0030] In some embodiments, the detection circuit 110 further generates a control signal V2. When an electrostatic discharge event occurs, the detection circuit 110 sets the control signal V2 to a second preset level, such as a high level or a low level. In this example, the control signal V2 is an inverted signal of the detection signal V1. For example, when the detection signal V1 is a low level, the control signal V2 is a high level. When the detection signal V1 is a high level, the control signal V2 is a low level.

[0031] The present invention does not limit the order in which the detection circuit 110 generates the detection signal V1 and the control signal V2. In one possible embodiment, the detection circuit 110 generates the detection signal V1 first, and then generates the control signal V2. In this example, the detection circuit 110 inverts the detection signal V1 to generate the control signal V2. In another possible embodiment, the detection circuit 110 generates the control signal V2 first, and then generates the detection signal V1. In this example, the detection circuit 110 may invert the control signal V2 to generate the detection signal V1.

[0032] The current release element 112 is coupled between the contact pads 106 and 108, and receives the control signal V2. When an electrostatic discharge event occurs, the detection signal V1 is a first preset level (such as a low level). Therefore, the control signal V2 is a second preset level (such as a high level). At this time, the current release element 112 is turned on to release the electrostatic discharge current from the contact pad 106 to the contact pad 108 or from the contact pad 108 to the contact pad 106. In this embodiment, the current release element 112 is an N-type transistor Nesd. The gate of the N-type transistor Nesd receives the control signal V2, its drain is coupled to the contact pad 106, and its source is coupled to the contact pad 108. In order to withstand high voltage, the channel size of the N-type transistor Nesd is larger than the channel size of the transistors 114 and 116. In other embodiments, the current release element 112 is a P-type transistor.

[0033] The transistor 116 is coupled between the core circuit 102 and the contact pad 108. In the present embodiment, the transistor 116 is an N-type transistor, whose drain (or first electrode) is coupled to the core circuit 102, whose source (or second electrode) is coupled to the contact pad 108, and whose gate is coupled to the transistor 114 and receives the detection signal V1. In one possible embodiment, when the detection signal V1 is at a first preset level (such as a low level), it indicates that an electrostatic discharge event has occurred. Therefore, the transistor 116 is not turned on to disable the core circuit 102. In other embodiments, in a normal mode (no electrostatic discharge event has occurred), the contact pad 108 receives a ground voltage. At this time, since the detection signal V1 is not at the first preset level, the transistor 116 is turned on to activate the core circuit 102. In one possible embodiment, the transistor 116 provides the voltage (such as a ground voltage) received by the contact pad 108 to the core circuit 102, so that the core circuit 102 operates normally.

[0034] The transistor 114 is coupled between the transistor 116 and the contact pad 108. When the detection signal V1 is at a first predetermined level, the control signal V2 is at a second predetermined level, so the transistor 114 is turned on to turn off the transistor 116. In one embodiment, when the detection signal V1 is at the first predetermined level, the transistor 114 sets the gate voltage of the transistor 116 to be equal to the potential of the contact pad 108 (e.g., a ground voltage).

[0035] In the present embodiment, the transistor 114 is an N-type transistor, whose drain (or third electrode) is coupled to the gate of the transistor 116, whose source (or fourth electrode) is coupled to the contact pad 108, and whose gate is coupled to the gate of the N-type transistor Nesd. In the normal mode (no electrostatic discharge event occurs), the contact pad 108 receives a ground voltage. At this time, since the detection signal V2 is not the second preset level, the transistor 114 is not turned on.

[0036] In some embodiments, when an electrostatic discharge event occurs, the detection circuit 110 sets the detection signal V1 to a first preset level. At this time, although the transistor 116 is not turned on, the detection signal V1 may gradually rise due to leakage current in the detection circuit 110, thereby turning on the transistor 116 and activating the core circuit 102. At this time, if the electrostatic discharge current enters the core circuit 102, it will damage the core circuit 102. Therefore, when the detection signal V1 is the first preset level, the transistor 114 is turned on to set the gate voltage of the transistor 116 to be equal to the potential of the contact pad 108 (such as a ground voltage) to prevent the transistor 116 from activating the core circuit 102.

[0037] Figure 2FIG. 2 is another schematic diagram of the operating circuit of the present invention. The operating circuit 200 includes a core circuit 202 and a protection circuit 204. Figure 1 The characteristics of the core circuit 102 are similar, so they are not repeated. The protection circuit 204 is coupled between the contact pads 206 and 208. When an electrostatic discharge event occurs at the contact pad 206 and the contact pad 208 is coupled to the ground, the protection circuit 204 enters a protection mode. In this mode, the protection circuit 204 releases the electrostatic discharge current from the contact pad 206 to the contact pad 208 and disables the core circuit 202. When the electrostatic discharge event does not occur, the protection circuit 204 enters a normal mode. In this mode, the protection circuit 204 commands the core circuit 202 to operate normally.

[0038] In this embodiment, the protection circuit 204 includes a detection circuit 210, a current release element 212, transistors 214, 216 and an inverter circuit 218. Since the characteristics of the detection circuit 210, the current release element 212, the transistors 214 and 216 are similar to Figure 1 The characteristics of the detection circuit 110, the current release element 112, and the transistors 114 and 116 are not described in detail.

[0039] The inverting circuit 218 is coupled between the contact pads 206 and 208, and inverts the detection signal V1 to generate the control signal V3. In this example, the level of the control signal V3 is the same as the level of the control signal V2. In this embodiment, the inverting circuit 218 acts as a buffer, so the driving capability of the control signal V3 is higher than the driving capability of the control signal V2. As shown in the figure, the inverting circuit 218 includes an N-type transistor 220 and a P-type transistor 222.

[0040] The source of the P-type transistor 222 is coupled to the contact pad 206, and the drain thereof is coupled to the gate of the transistor 214, and the gate thereof serves as the input terminal of the inverter circuit 218 for receiving the detection signal V1. The source of the N-type transistor 220 is coupled to the contact pad 208, and the drain thereof serves as the output terminal of the inverter circuit 218 and is coupled to the gate of the transistor 214, and the gate thereof receives the detection signal V1. When an electrostatic discharge event occurs, the detection circuit 210 sets the detection signal V1 to a first preset level. At this time, the control signal V3 is a second preset level. Therefore, the transistor 214 is turned on to set the gate voltage of the transistor 216 to be equal to the potential of the contact pad 208 (such as a ground voltage) to prevent the transistor 216 from activating the core circuit 202. The present invention does not limit the number of the inverter circuits. In other embodiments, the protection circuit 204 has an odd number of inverter circuits. The inverter circuits are connected in series between the detection circuit 210 and the transistor 214.

[0041] Figure 3FIG. 3 is another schematic diagram of the operating circuit of the present invention. The operating circuit 300 includes a core circuit 302 and a protection circuit 304. Figure 1 The characteristics of the core circuit 102 are similar, so they are not repeated here. The protection circuit 304 is coupled between the contact pads 306 and 308. When an electrostatic discharge event occurs at the contact pad 306 and the contact pad 308 is coupled to the ground, the protection circuit 304 enters a protection mode. In this mode, the protection circuit 304 releases the electrostatic discharge current from the contact pad 306 to the contact pad 308 and disables the core circuit 302. When the electrostatic discharge event does not occur, the protection circuit 304 enters a normal mode. In this mode, the protection circuit 304 commands the core circuit 302 to operate normally. In the present embodiment, the protection circuit 304 includes a detection circuit 310, a current release element 312, transistors 314, 316, an inverter circuit 318 and 324. Since the characteristics of the detection circuit 310, the current release element 312, the transistors 314 and 316 are similar to Figure 1 The characteristics of the detection circuit 110, the current release element 112, and the transistors 114 and 116 are not described in detail.

[0042] The inverter circuits 318 and 324 are connected in series between the detection circuit 310 and the transistor 314 to process the control signal V2 and generate the control signal V5. In this embodiment, the inverter circuits 318 and 324 form a buffer circuit to increase the driving capability of the control signal V2. In this example, the driving capability of the control signal V5 is greater than the driving capability of the control signal V2. The present invention does not limit the number of inverter circuits. In other embodiments, the protection circuit 304 has an even number of inverter circuits.

[0043] In the present embodiment, the inverting circuit 318 is coupled between the contact pads 306 and 308, and inverts the control signal V2 to generate the control signal V4. In this example, the level of the control signal V4 is the same as the level of the detection signal V1. As shown in the figure, the inverting circuit 318 includes an N-type transistor 320 and a P-type transistor 322. The source of the P-type transistor 322 is coupled to the contact pad 306, and its drain serves as the output end of the inverting circuit 318 to provide the control signal V4, and its gate serves as the input end of the inverting circuit 318 to receive the control signal V2. The source of the N-type transistor 320 is coupled to the contact pad 308, its drain is coupled to the drain of the P-type transistor 322, and its gate is coupled to the gate of the P-type transistor 322.

[0044] The inverting circuit 324 is coupled between the contact pads 306 and 308, and inverts the control signal V4 to generate the control signal V5. In this example, the level of the control signal V5 is the same as the level of the control signal V2. As shown in the figure, the inverting circuit 324 includes an N-type transistor 326 and a P-type transistor 328. The source of the P-type transistor 328 is coupled to the contact pad 306, and its drain serves as the output of the inverting circuit 324, and provides the control signal V5 to the gate of the transistor 314, and its gate serves as the input of the inverting circuit 324 to receive the control signal V4. The source of the N-type transistor 326 is coupled to the contact pad 308, its drain is coupled to the drain of the P-type transistor 328, and its gate is coupled to the gate of the P-type transistor 328.

[0045] Figure 4 FIG. 4 is a schematic diagram of a detection circuit of the present invention. As shown in the figure, the detection circuit 400 includes a resistor 402, a capacitor 404 and an inverter circuit 408. In this embodiment, the detection circuit 400 can be used as Figure 1 The detection circuit 110, Figure 2 The detection circuit 210 and Figure 3 For convenience of explanation, it is assumed that the detection circuit 400 is Figure 1 The detection circuit 110.

[0046] The resistor 402 is coupled between the contact pad 106 and the common node 414. The capacitor 404 is coupled between the common node 414 and the contact pad 108. In this embodiment, the level of the common node 414 is used as the detection signal V1. In some embodiments, the common node 414 is directly connected to Figure 2 The input terminal of the inverting circuit 218.

[0047] When an electrostatic discharge event occurs at the contact pad 106 and the contact pad 108 is coupled to the ground, the level of the common node 414 (i.e., the detection signal V1) is a low level. When the contact pad 106 receives a first operating voltage (e.g., 3.3V) and the contact pad 108 receives a second operating voltage (e.g., 0V), the level of the common node 414 (i.e., the detection signal V1) is a high level. In other embodiments, the resistor 402 and the capacitor 404 may be connected in series. Figure 2 between the contact pads 206 and 208 or in series with Figure 3 between contact pads 306 and 308 .

[0048] The inverting circuit 408 inverts the detection signal V1 to generate the control signal V2. In this embodiment, the input terminal of the inverting circuit 408 is coupled to the common node 414, and the output terminal of the inverting circuit 408 is coupled to the common node 414. Figure 1The current release element 112 is used to provide a control signal V2 to the current release element 112. In this example, the output terminal of the inverter circuit 408 may be directly connected to Figure 1 In other embodiments, the output terminal of the inverter circuit 408 may be coupled to the gate of the transistor 114. Figure 2 The current release element 212 or Figure 3 The current release element 312.

[0049] The present invention does not limit the architecture of the inverting circuit 408. Any circuit that can invert the detection signal V1 can be used as the inverting circuit 408. In the present embodiment, the inverting circuit 408 includes a P-type transistor 410 and an N-type transistor 412. The gate of the P-type transistor 410 serves as the input terminal of the inverting circuit 408 for receiving the detection signal V1, and its source is coupled to the contact pad 106, and its drain serves as the output terminal of the inverting circuit 408 for outputting the control signal V2. The gate of the N-type transistor 412 is coupled to the gate of the P-type transistor 410. The drain of the N-type transistor 412 is coupled to the drain of the P-type transistor 410. The source of the N-type transistor 412 is coupled to the contact pad 108. In some embodiments, the inverting circuit 408 is coupled to Figure 2 between the contact pads 206 and 208 or Figure 3 between contact pads 306 and 308 .

[0050] Figure 5 FIG. 5 is another schematic diagram of the detection circuit of the present invention. As shown in the figure, the detection circuit 500 includes a resistor 502, a capacitor 504 and an inverter circuit 508. In this embodiment, the detection circuit 500 can be used as Figure 1 The detection circuit 110, Figure 2 The detection circuit 210 and Figure 3 For convenience of explanation, it is assumed that the detection circuit 500 is Figure 1 The detection circuit 110.

[0051] Capacitor 504 is coupled between contact pad 106 and common node 514. Resistor 502 is coupled between common node 514 and contact pad 108. In the present embodiment, the level of common node 514 is used as control signal V2. When an electrostatic discharge event occurs at contact pad 106 and contact pad 108 is coupled to ground, the level of common node 514 (i.e., control signal V2) is a high level. When contact pad 106 receives a first operating voltage (e.g., 3.3V) and contact pad 108 receives a second operating voltage (e.g., 0V), the level of common node 514 (i.e., control signal V2) is a low level. In other embodiments, capacitor 504 and resistor 502 may be connected in series. Figure 2 between the contact pads 206 and 208 or in series with Figure 3between contact pads 306 and 308 .

[0052] The inverting circuit 508 inverts the control signal V2 to generate the detection signal V1. In this embodiment, the input terminal of the inverting circuit 508 is coupled to the common node 514, and the output terminal of the inverting circuit 508 is coupled to the common node 514. Figure 1 In other embodiments, the output terminal of the inverter circuit 508 may be coupled to the gate of the transistor 116. Figure 2 The input terminal of the inverting circuit 218.

[0053] In this embodiment, the inverter circuit 508 includes a P-type transistor 510 and an N-type transistor 512. The gate of the P-type transistor 510 serves as an input terminal of the inverter circuit 508 for receiving the control signal V2, the source of the P-type transistor 510 is coupled to the contact pad 106, and the drain of the P-type transistor 510 serves as an output terminal of the inverter circuit 508 for outputting the detection signal V1. The gate of the N-type transistor 512 is coupled to the gate of the P-type transistor 510. The drain of the N-type transistor 512 is coupled to the source of the P-type transistor 510. The source of the N-type transistor 512 is coupled to the contact pad 108. In some embodiments, the inverter circuit 508 is coupled to Figure 2 between the contact pads 206 and 208 or Figure 3 between contact pads 306 and 308 .

[0054] Unless otherwise defined, all words (including technical and scientific words) herein are generally understood by those skilled in the art to which the present invention belongs. In addition, unless expressly indicated, the definitions of words in general dictionaries should be interpreted as consistent with the meanings in articles in the relevant technical field, and should not be interpreted as ideal or overly formal. Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0055] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention may be implemented in the form of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A protection circuit, characterized in that: To prevent an electrostatic discharge current from entering a core circuit, the protection circuit includes: A detection circuit coupled between a first contact pad and a second contact pad for detecting whether an electrostatic discharge event occurs, wherein when the electrostatic discharge event occurs, the detection circuit sets a detection signal to a preset level; a current release element coupled between the first contact pad and the second contact pad, and when the detection signal is at the preset level, the current release element is turned on to allow the electrostatic discharge current to flow; a first transistor coupled between the core circuit and the second contact pad; and A second transistor is coupled between the first transistor and the second contact pad. When the detection signal is at the preset level, the second transistor is turned on to set the gate voltage of the first transistor so that the first transistor is not turned on.

2. The protection circuit according to claim 1, characterized in that: The detection circuit includes: a resistor coupled between the first contact pad and a common node; a capacitor coupled between the common node and the second contact pad; and A first inverting circuit has a first input terminal and a first output terminal. The first input terminal is coupled to the common node, and the first output terminal is coupled to the current release element.

3. The protection circuit according to claim 2, characterized in that: The first transistor has a first gate, a first electrode and a second electrode. The first gate receives the detection signal. The first electrode is coupled to the core circuit. The second electrode is coupled to the second contact pad. The second transistor has a second gate, a third electrode and a fourth electrode. The third electrode is coupled to the first gate, and the fourth electrode is coupled to the second contact pad.

4. The protection circuit according to claim 3, characterized in that: The second gate is directly coupled to the first output terminal.

5. The protection circuit according to claim 3, characterized in that: When the second transistor is turned on, the voltage of the first gate is equal to the potential of the second contact pad.

6. The protection circuit according to claim 3, characterized in that: Also includes: A second inverting circuit has a second input terminal and a second output terminal. The second input terminal is coupled to the common node, and the second output terminal is coupled to the second gate.

7. The protection circuit according to claim 3, characterized in that: Also includes: a second inverting circuit having a second input terminal and a second output terminal, wherein the second input terminal is coupled to the first output terminal; and A third inverting circuit has a third input terminal and a third output terminal. The third input terminal is coupled to the second output terminal, and the third output terminal is coupled to the second gate.

8. The protection circuit according to claim 1, characterized in that: The current release element, the first transistor and the second transistor are N-type transistors.

9. The protection circuit according to claim 1, characterized in that: When the first contact pad receives a first operating voltage and the second contact pad receives a second operating voltage, the core circuit operates normally, and the first transistor is turned on, and the second transistor is turned off.

10. The protection circuit according to claim 1, characterized in that: When the first contact pad receives a first operating voltage and the second contact pad receives a second operating voltage, the detection circuit sets the detection signal not to be the preset level.

Images