Substrate structure and manufacturing method thereof

Abstract

A substrate structure and a manufacturing method thereof include a solder-proof material covering body formed on a substrate body, which has a hollow portion for exposing a part of a circuit layer, and a stepped structure is formed at the edge of the hollow portion to avoid copper migration.

Description

Technical Field

[0001] The present invention relates to a substrate structure, and more particularly to a substrate structure for a bump on lead type wiring. Background Art

[0002] As the size of semiconductor products is shrinking, the circuit spacing in semiconductor packages is required to be smaller and smaller. For this reason, flip-chip package substrates use a bump on lead / bump on trace (BOL) method for circuit design.

[0003] However, the pitch of the circuits designed by the BOL method is very small, so a solder mask cannot be formed between the circuits for electrical isolation. Therefore, an opening that can expose multiple BOL circuits at the same time is usually formed on the entire solder mask by a window process.

[0004] like Figure 1A As shown, the existing packaging substrate 1 using the BOL method has a circuit layer 13 formed on the outer surface 10a of its substrate body 10, and the circuit layer 13 has a plurality of conductive traces 130 and a plurality of electrical contact pads 131 integrally combined with the ends of the conductive traces 130, and a solder mask 11 is provided on the substrate body 10, so that the solder mask 11 has an opening 110 corresponding to all the electrical contact pads 131, so that the upper surface and the side surface of the electrical contact pad 131 are completely exposed in the opening 110.

[0005] In the conventional package substrate 1, the window opening process is completed by exposure and development. In order to increase the structural strength and prevent the circuit layer 13 from being exposed and short-circuited, the thickness h of the solder mask 11 is designed to be much larger than the thickness t of the circuit layer 13 (e.g. Figure 1C Therefore, in order to ensure the accuracy of the target area of ​​the exposed surface 13a (copper material) of the circuit layer 13 (such as Figure 1C As shown in FIG. 1 ), the light energy F in the exposure and development operation will be based on the exposed surface 13a of the circuit layer 13, that is, the light energy F will only act on the exposed surface 13a of the circuit layer 13, so the light energy F is not easy to act on the bottom of the solder mask 11 (that is, the outer surface 10a of the substrate body 10), so that after the development operation, the bottom of the wall of the opening 110 of the solder mask 11 is easily corroded by the developer due to insufficient light, thereby forming an undercut structure V (as shown in FIG. 1 ). Figure 1B shown).

[0006] However, in the conventional package substrate 1, the undercut structure V will have residual developer solution. Therefore, based on the requirement of fine line pitch, the spacing between the conductive traces 130 becomes smaller and smaller, causing the copper material of the conductive traces 130 to migrate along the developer solution remaining in the undercut structure V, i.e., copper migration phenomenon, so that an irregular conductor 9 is formed at the undercut structure V, making the reliability of the package substrate 1 poor. In severe cases, the conductor 9 may connect two adjacent conductive traces 130 to cause an electrical short circuit.

[0007] In addition, although increasing the light energy F can prevent the bottom of the solder mask 11 from forming the bottom cut structure V, if the light energy F is too large, the solder mask on the circuit layer 13 will be overexposed (overexposed), resulting in the solder mask on the circuit layer 13 being difficult to remove after the development operation, causing the area of ​​the exposed surface 13a of the circuit layer 13 to be too small. Therefore, in the subsequent packaging process, other electronic components cannot be effectively connected externally, and even poor electrical transmission may occur.

[0008] Therefore, how to overcome the various deficiencies of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the invention

[0009] In order to solve the above problems in the prior art, the present invention provides a substrate structure and a manufacturing method thereof to avoid the copper migration phenomenon.

[0010] The substrate structure of the present invention comprises: a substrate body having a bonding surface; a circuit layer formed on the bonding surface; and a covering body formed on the bonding surface and covering the circuit layer and having a hollow portion exposing a portion of the circuit layer, wherein the edge of the hollow portion forms a stepped structure.

[0011] The present invention also provides a method for manufacturing a substrate structure, including: providing a substrate body having a bonding surface, and forming a circuit layer on the bonding surface; and forming a coating body on the bonding surface so that the coating body covers the circuit layer, and the coating body has a hollow portion that exposes a portion of the circuit layer, wherein the edge of the hollow portion forms a stepped structure.

[0012] In the aforementioned substrate structure and manufacturing method thereof, the bottom of the hollow portion does not form an undercut structure.

[0013] In the aforementioned substrate structure and its manufacturing method, the circuit layer has a plurality of mutually separated conductive traces, so that a portion of the surface of the plurality of conductive traces is exposed in the hollow portion. For example, the encapsulation body is not formed between the line segments of the plurality of conductive traces exposed in the hollow portion.

[0014] In the aforementioned substrate structure and its manufacturing method, the manufacturing process of the encapsulation body stacks multiple insulating protective layers on the joint surface. For example, the bottom insulating protective layer of the encapsulation body covers the circuit layer, and the bottom insulating protective layer of the encapsulation body is formed by exposure and development, and the exposure energy hits the joint surface, so that the multiple insulating protective layers form openings respectively to serve as the hollow portion. Furthermore, the widths of at least two of the multiple openings are inconsistent so that the edge of the hollow portion forms the stepped structure. Alternatively, the wall surface of at least one of the multiple openings is a flat surface; or, the wall surface of the opening of the bottom insulating protective layer of the encapsulation body can be a vertical surface relative to the joint surface or a slope that is narrow at the top and wide at the bottom.

[0015] In the aforementioned substrate structure and manufacturing method thereof, the encapsulation body is a solder resist.

[0016] As can be seen from the above, the substrate structure and the manufacturing method of the present invention are mainly designed with a stepped structure at the edge of the hollow portion of the encapsulation body to avoid the formation of an undercut structure at the bottom of the encapsulation body. Therefore, compared with the prior art, the substrate structure of the present invention can effectively avoid the phenomenon of copper migration and prevent short circuits between adjacent conductive traces, thereby helping to improve the reliability of the substrate structure of the present invention.

[0017] In addition, in the manufacturing method of the present invention, if the coating includes multiple insulating protective layers stacked on each other, the thickness of the bottom insulating protective layer only needs to be slightly higher than the circuit layer, so the light energy does not need to be set too large. Therefore, compared with the prior art, even if the light energy is set to a strength that does not form a bottom cut structure at the bottom of the bottom insulating protective layer (such as energy directly hitting the joint surface), the material of the bottom insulating protective layer at the hollow portion will not be overexposed, thereby still ensuring that the circuit layer can effectively expose the required metal area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A It is a partial top view schematic diagram of an existing packaging substrate.

[0019] Figure 1B for Figure 1A Cross-sectional view along section line BB.

[0020] Figure 1C for Figure 1A Cross-sectional view along section line CC.

[0021] Figure 2 It is a partial top plan view schematic diagram of the substrate structure of the present invention.

[0022] Figure 2 'for Figure 2 Cross-sectional view along section line L'-L'.

[0023] Figure 2 "for Figure 2 Cross-sectional view along section line L”-L”.

[0024] FIG. 2A to FIG. 2C for Figure 2 'A schematic partial cross-sectional view of different embodiments of the covering body.

[0025] FIG. 3A to FIG. 3E The first embodiment of the method for manufacturing the substrate structure of the present invention is as follows Figure 2 A schematic cross-sectional view of the section line L1-L1.

[0026] Figure 3A 'to Figure 3E ' is the first embodiment of the method for making the substrate structure of the present invention. Figure 2 A schematic cross-sectional view of the section line L2-L2.

[0027] Description of Reference Numerals

[0028] 1: Package substrate

[0029] 10:Substrate body

[0030] 10a: Outer surface

[0031] 11: Solder mask

[0032] 110: Opening

[0033] 13,23: Circuit layer

[0034] 13a: Exposed surface

[0035] 130,230: Conductive traces

[0036] 131,231: Electrical contact pad

[0037] 2: Substrate structure

[0038] 2a: Encapsulation

[0039] 20:Substrate body

[0040] 20a: Joint surface

[0041] 200: Dielectric layer

[0042] 201: Wiring layer

[0043] 21: First insulation protection layer

[0044] 210: First Opening

[0045] 210a: First wall

[0046] 211: Steps

[0047] 22: Second insulation protection layer

[0048] 220: Second opening

[0049] 220a: Second wall

[0050] 230a: Line segment

[0051] 24: Conductive element

[0052] 9: Conductor

[0053] D1,D2: Width

[0054] E, e: gap

[0055] F, F1, F2: Light energy

[0056] h,t: thickness

[0057] T: Stepped structure

[0058] V: Undercut structure

[0059] W: hollow part. DETAILED DESCRIPTION

[0060] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0061] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention. At the same time, the terms such as "on", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0062] Figure 2 FIG. 2 is a partial top view of the substrate structure 2 of the present invention. Figure 2 As shown, the substrate structure 2 includes a substrate body 20, a circuit layer 23, and a coating body 2a having a hollow portion W. In this embodiment, the coating body 2a includes a first insulating protection layer 21 and a second insulating protection layer 22 stacked on each other.

[0063] The substrate body 20 has its outer surface defined as a bonding surface 20 a so that electronic components such as chips, package substrates or package modules can be connected to the bonding surface 20 a of the substrate body 20 .

[0064] In this embodiment, the substrate body 20 is a circuit structure with a core layer or a coreless circuit structure, such as a package substrate, which includes at least one dielectric layer 200 and a wiring layer 201 disposed on the dielectric layer 200. Figure 2 'and Figure 2 ” As shown. For example, the wiring layer 201 is formed by a redistribution layer (RDL) method, and its material is copper, and the material forming the dielectric layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc. It should be understood that the substrate body 20 can also be other carrier units for receiving electronic components, such as a metal plate of a lead frame, or a semiconductor plate such as a wafer, a chip, a silicon interposer, a silicon material, a glass, etc., but is not limited to the above.

[0065] The circuit layer 23 is formed on the bonding surface 20a of the substrate body 20 and is electrically connected to the wiring layer 201 of the substrate body 20. Figure 2 ” as shown.

[0066] In this embodiment, the circuit layer 23 includes a plurality of conductive traces 230 and an electrical contact pad 231 integrally connected to the conductive traces 230, and each of the conductive traces 230 is separated from each other and will not be short-circuited, and the electrical contact pad 231 is used to connect a conductive element 24 (such as a solder material) such as Figure 2 ”), so that the substrate structure 2 is connected to electronic components such as chips, packaging substrates or packaging modules through the conductive element 24.

[0067] The first insulating protection layer 21 is formed on the bonding surface 20a of the substrate body 20 and has at least one first opening 210. Figure 2 and Figure 2 ', so that part of the bonding surface 20a of the substrate body 20, part of the line segments 230a of the conductive traces 230 and the electrical contact pads 231 are exposed in the first opening 210, as shown in FIG. Figure 2 and Figure 2 ” as shown, the first insulating protection layer 21 only covers a portion of the circuit layer 23 and a portion of the bonding surface 20a.

[0068] In this embodiment, the first insulating protection layer 21 is a photosensitive solder mask, and the outline of the first opening 210 is generally rectangular, groove-shaped or other appropriate shapes, and the first wall surface 210a of the first opening 210 is a flat surface. For example, the first wall surface 210a is a vertical surface relative to the joint surface 20a (such as Figure 2A as shown) or an inclined surface (as Figure 2 ' is thinner at the top and wider at the bottom or has a sloped appearance), and the first insulating protection layer 21 has no undercut structure formed between the first wall 210a of the first opening 210 and the bonding surface 20a. Specifically, the electrical contact pad 231 does not contact the first insulating protection layer 21, and the partial line segments 230a of the conductive traces 230 protrude out of the first wall 210a of the first opening 210, so that the partial line segments 230a of the conductive traces 230 and the electrical contact pad 231 are exposed in the first opening 210.

[0069] The second insulating protection layer 22 is formed on a portion of the surface of the first insulating protection layer 21 and has at least one second opening 220 exposing the first opening 210. Figure 2 and Figure 2 ', so that part of the bonding surface 20a of the substrate body 20, part of the line segments 230a of the conductive traces 230 and the electrical contact pad 231 are exposed in the second opening 220, as shown in FIG. Figure 2 and Figure 2 ” as shown, the second insulating protection layer 22 only covers a portion of the circuit layer 23, wherein the first opening 210 and the second opening 220 serve as the hollow portion W. It should be understood that the layout range of the second insulating protection layer 22 is almost equal to (slightly smaller than) the layout range of the first insulating protection layer 21.

[0070] In this embodiment, the second insulating protective layer 22 is a photosensitive solder mask, and the contour of the second opening 220 is roughly corresponding to the contour of the first opening 210 and is rectangular, groove-shaped or other appropriate shapes, and the second wall surface 220a of the second opening 220 is a flat surface. For example, the second wall surface 220a is a vertical surface relative to the joint surface 20a (such as Figure 2B as shown) or an inclined surface (as Figure 2A The second wall 220a shown as narrow at the top and wide at the bottom may have a sloped appearance, or Figure 2CThe second wall surface 220a shown as a slope that is wide at the top and narrow at the bottom or has a cliff-like or precipice-like appearance), and the second insulating protection layer 22 forms a step-like structure T between the second wall surface 220a of the second opening 220 and the first wall surface 210a of the first opening 210 of the first insulating protection layer 21. Specifically, the first wall surface 210a of the first opening 210 of the first insulating protection layer 21 protrudes into the second opening 220, so that the protruding portion of the first insulating protection layer 21 serves as a step portion 211 to form the step-like structure T. It should be understood that the circuit layer 23 does not contact the second insulating protection layer 22.

[0071] Therefore, the encapsulation body 2 a is not formed between the line segments 230 a of the conductive traces 230 exposed in the hollow portion W, and the encapsulation body 2 a is not formed between the electrical contact pads 231 .

[0072] In addition, there are many types of materials for solder mask, and even many types of photosensitive materials, so the material of the first insulating protection layer 21 and the material of the second insulating protection layer 22 can be the same or different.

[0073] FIG. 3A to FIG. 3E and Figure 3A 'to Figure 3E ' is a cross-sectional schematic diagram of a method for manufacturing a first embodiment of a substrate structure 2 of the present invention, wherein: FIG. 3A to FIG. 3E Presentation Figure 2 The process status of the section line L1-L1, and Figure 3A 'to Figure 3E 'Present Figure 2 The process status of the cross section line L2-L2.

[0074] In this embodiment, FIG. 3A to FIG. 3E The process status shown is similar to Figure 3A 'to Figure 3E The process states shown correspond to the steps at the same time point.

[0075] like Figure 3A and Figure 3A ', and refer to Figure 2 , providing a substrate body 20, on which a circuit layer 23 is formed on a bonding surface 20a.

[0076] like Figure 3B and Figure 3B 'As shown, a first insulating protection layer 21 is formed on the entire bonding surface 20a of the substrate body 20.

[0077] like Figure 3C and Figure 3C', at least one first opening 210 is formed on the first insulating protection layer 21 by exposure and development, so that part of the bonding surface 20a of the substrate body 20, part of the line segment 230a of the conductive trace 230 and the electrical contact pad 231 are exposed in the first opening 210.

[0078] In this embodiment, during the exposure and development operation, the light energy F1 is based on the joint surface 20a of the substrate body 20, so that the light energy F1 acts on the joint surface 20a of the substrate body 20, so that the bottom side of the first insulating protective layer 21 can fully absorb the light energy F1, and thus after the development operation, the bottom of the first wall surface 210a of the first opening 210 can be prevented from being corroded by the developer solution due to sufficient light exposure. Therefore, the first wall surface 210a of the first opening 210 presents a flat surface, and the bottom of the first wall surface 210a of the first opening 210 does not form an undercut structure.

[0079] like Figure 3D and Figure 3D ', a second insulating protection layer 22 is formed on the entire surface of the first insulating protection layer 21 and the partial bonding surface 20a of the substrate body 20, and the second insulating protection layer 22 fills the first opening 210 to cover the line segments 230a of the conductive traces 230 and the electrical contact pads 231.

[0080] like Figure 3E and Figure 3E ', at least one second opening 220 exposing the first opening 210 is formed on the second insulating protection layer 22 by exposure and development, so that part of the bonding surface 20a of the substrate body 20, part of the line segments 230a of the conductive traces 230 and the electrical contact pad 231 are exposed in the second opening 220.

[0081] In this embodiment, the width D2 of the second opening 220 of the second insulating protection layer 22 is greater than the width D1 of the first opening 210 of the first insulating protection layer 21, so as to facilitate the formation of a stepped structure T (eg, Figure 2 ' shown).

[0082] In addition, during the exposure and development operation, the light energy F2 can be adjusted according to the requirements to form the desired embodiment of the second wall surface 220a of the second opening 220. For example, when the light energy F2 is relatively large, the following can be formed: Figure 2A The second wall surface 220a shown in FIG. 1 is a sloped surface that is narrow at the top and wide at the bottom. When the illumination energy F2 is normal, the following Figure 2B When the illumination energy F2 is small, a vertical second wall surface 220a may be formed. Figure 2CThe second wall surface 220a shown is a sloped surface that is wide at the top and narrow at the bottom, and may form an undercut structure. It should be understood that since the second insulating protection layer 22 does not contact the circuit layer 23, even if the second insulating protection layer 22 forms an undercut structure, it will not cause copper migration.

[0083] In subsequent processes, a plurality of conductive elements 24 may be formed on the electrical contact pads 231 (eg Figure 2 ”), so that the substrate structure 2 is connected to electronic components such as chips, packaging substrates or packaging modules through the conductive element 24.

[0084] The method for manufacturing the substrate structure 2 of the present invention is to manufacture the first insulating protective layer 21 and the second insulating protective layer 22 so that the thickness of the first insulating protective layer 21 only needs to cover the circuit line 23 (that is, the difference E between the thickness of the first insulating protective layer 21 and the thickness of the circuit layer 23 is extremely small, such as Figure 3B and Figure 3B ' as shown), the thickness of the first insulating protective layer 21 is extremely thin. Therefore, compared with the prior art, the light energy F1 of the present invention can directly act on the bonding surface 20a of the substrate body 20 (or the light energy F1 can be set so that the bottom of the first insulating protective layer 21 does not form an undercut structure), thereby effectively avoiding the phenomenon of copper migration, which is conducive to improving reliability.

[0085] In addition, in the manufacturing method of the present invention, since the thickness of the first insulating protective layer 21 is extremely thin, the light energy F1 does not need to be set too large. Therefore, compared with the prior art, even if the light energy F1 is set to a strength that does not form an undercut structure at the bottom of the first insulating protective layer 21, the material of the first insulating protective layer 21 at the hollow portion W will not be overexposed, thereby ensuring that the circuit layer 23 effectively exposes the required metal area (i.e., the partial line segments 230a of the conductive traces 230 and the electrical contact pads 231).

[0086] In summary, in the substrate structure and the manufacturing method thereof of the present invention, the edge of the hollow portion of the encapsulation body is designed with a stepped structure to avoid the formation of an undercut structure at the bottom of the encapsulation body. Therefore, the substrate structure of the present invention can effectively avoid the phenomenon of copper migration and prevent short circuits between adjacent conductive traces, thereby helping to improve the reliability of the substrate structure of the present invention.

[0087] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as listed in the attached claims.

Claims

1. A substrate structure, characterized in that: include: A substrate body having a bonding surface; A circuit layer including electrical contact pads formed on the bonding surface; as well as The encapsulation body is formed on the joint surface and encapsulates the circuit layer, and the encapsulation body has a hollow portion for exposing the electrical contact pad of the circuit layer, wherein the edge of the hollow portion of the encapsulation body forms a stepped structure, and a conductive element directly connected to the electrical contact pad is formed at the hollow portion of the encapsulation body.

2. The substrate structure according to claim 1, characterized in that: The bottom of the hollow portion does not form an undercut structure.

3. The substrate structure according to claim 1, characterized in that: The circuit layer has a plurality of conductive traces separated from each other, so that a portion of the surface of the plurality of conductive traces is exposed outside the hollow portion.

4. The substrate structure according to claim 3, characterized in that: The encapsulation body is not formed between the line segments of the plurality of conductive traces exposed from the hollow portion.

5. The substrate structure according to claim 1, characterized in that: The encapsulation body comprises a plurality of insulating protection layers stacked on each other.

6. The substrate structure according to claim 5, characterized in that: The bottom insulating protection layer of the coating body covers the circuit layer.

7. The substrate structure according to claim 5, characterized in that: The plurality of insulating protection layers respectively form openings to serve as the hollow portions.

8. The substrate structure according to claim 7, characterized in that: The widths of at least two of the plurality of openings are inconsistent, so that the edge of the hollow portion forms the stepped structure.

9. The substrate structure according to claim 7, characterized in that: The wall surface of at least one of the plurality of openings is a flat surface.

10. The substrate structure according to claim 7, characterized in that: The wall surface of the opening of the bottom insulating protection layer of the encapsulation body is a vertical surface or an inclined surface narrow at the top and wide at the bottom relative to the joint surface.

11. The substrate structure according to claim 1, characterized in that: The coating is a solder resist.

12. A method for manufacturing a substrate structure, characterized in that: include: Providing a substrate body having a bonding surface, and forming a circuit layer including an electrical contact pad on the bonding surface; as well as A coating is formed on the joint surface so that the coating covers the circuit layer, and the coating has a hollow portion that exposes the electrical contact pad of the circuit layer, wherein the edge of the hollow portion of the coating forms a stepped structure, and a conductive element directly connected to the electrical contact pad is formed at the hollow portion of the coating.

13. The method for manufacturing a substrate structure according to claim 12, wherein: The bottom of the hollow portion does not form an undercut structure.

14. The method for manufacturing a substrate structure according to claim 12, wherein: The circuit layer has a plurality of conductive traces separated from each other, so that a portion of the surface of the plurality of conductive traces is exposed outside the hollow portion.

15. The method for manufacturing a substrate structure according to claim 14, wherein: The encapsulation body is not formed between the line segments of the plurality of conductive traces exposed from the hollow portion.

16. The method for manufacturing a substrate structure according to claim 12, wherein: The process of manufacturing the encapsulation body is to stack a plurality of insulating protection layers on the joint surface.

17. The method for manufacturing a substrate structure according to claim 16, wherein: The bottom insulating protection layer of the coating body covers the circuit layer.

18. The method for manufacturing a substrate structure according to claim 17, wherein: The manufacturing method also includes forming the bottom insulating protection layer of the encapsulation body by exposure and development, and the exposure energy hits the joint surface.

19. The method for manufacturing a substrate structure according to claim 16, wherein: The plurality of insulating protection layers respectively form openings to serve as the hollow portions.

20. The method for manufacturing a substrate structure according to claim 19, wherein: The widths of at least two of the plurality of openings are inconsistent, so that the edge of the hollow portion forms the stepped structure.

21. The method for manufacturing a substrate structure according to claim 19, wherein: The wall surface of at least one of the plurality of openings is a flat surface.

22. The method for manufacturing a substrate structure according to claim 19, wherein: The wall surface of the opening of the bottom insulating protection layer of the encapsulation body is a vertical surface or an inclined surface narrow at the top and wide at the bottom relative to the joint surface.

23. The method for manufacturing a substrate structure according to claim 12, wherein: The coating is a solder resist.

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