Heat dissipation substrate for semiconductor and method for manufacturing the same

Abstract

Provided is a semiconductor heat dissipation substrate capable of forming a fine pattern on a thick electrode metal plate and improving dielectric strength and peel strength, and a method of manufacturing the same. The semiconductor heat dissipation substrate according to an embodiment of the present application includes an electrode metal plate having a plurality of electrode patterns formed with a pattern space therebetween so as to be electrically insulated from each other, a metal base disposed below the electrode metal plate to diffuse heat conducted from the electrode metal plate, an insulating layer formed between the electrode metal plate and the metal base, and an insulating material filling portion filling the pattern space and a peripheral portion outside an electrode pattern group composed of the plurality of electrode patterns, directly contacting side surfaces of the plurality of electrode patterns to support the side surfaces of the plurality of electrode patterns.

Description

TECHNICAL FIELD

[0001] The present invention relates to a heat dissipation substrate for mounting a semiconductor element, a semiconductor module including the same, and a manufacturing method thereof. More particularly, the present invention relates to a manufacturing method of a heat dissipation substrate having both a heat dissipation plate function and a circuit board function for mounting a semiconductor element, and a structural characteristic according to the same, the heat dissipation substrate including a thick electrode metal plate to be suitable for mounting a high-power semiconductor element or a high-output LED, etc. BACKGROUND

[0002] Recently, research and development on the generation, storage, and use of renewable energy such as solar power generation or wind power generation are actively conducted in the field of the electric power industry. The efficiency improvement, safety, and energy saving of various electrical / electronic devices including batteries for electric vehicles and power systems are also actively researched and developed. A key component used herein is a power module using a power device, i.e., a power semiconductor module. In the lighting field, there is also a tendency to apply an LED light source having excellent efficiency and service life to a light source requiring high output such as a car headlight, a streetlight, and a plant growth light for a smart farm.

[0003] The current used in these power devices is several tens to several hundreds of amperes (Ampere), and the voltage is several hundreds to several thousands of volts (Volt), which is high power. Therefore, the power module generates a large amount of heat, and there can be a problem of misoperation and reliability of the device due to the heat. In order to prevent these defects, how to quickly dissipate the heat generated in the power semiconductor element becomes a big problem. In the case of a high-output LED light source module, heat dissipation is also a decisive factor in determining the service life and efficiency of the device.

[0004] In the existing manufacturing method of a metal printed circuit board for a power semiconductor, an insulating layer is interposed between a metal substrate having high thermal conductivity and a copper foil, and is laminated (hot pressed) at high temperature and high pressure, and then manufactured through a general printed circuit board manufacturing process. The thermal conductivity of a metal printed circuit board (Metal PCB) manufactured by the prior art is generally 3 W / m.K to 5 W / m.K, and a large heat sink must be attached in order to sufficiently dissipate heat. Herein, in the general printed circuit board manufacturing process, in order to form a circuit electrode pattern on a layer made of a copper foil, an etching or plating process is used.

[0005] However, the existing metal printed circuit board manufacturing method is difficult to apply to a heat dissipation substrate for a high-power semiconductor. This is because, when the thickness of the electrode metal plate is increased in order to mount a high-power semiconductor, it is difficult to cope with by etching or plating process. In fact, in the related art field, if the thickness of the electrode metal plate is 0.3 mm or more, it is judged that it is difficult to maintain profitability by etching or plating. In addition, there is a problem that the cross-sectional profile of the electrode pattern is deteriorated, and insulation damage is easily generated.

[0006] In addition, the etching or plating process has a big problem of environmental pollution caused by the use of toxic chemicals or heavy metal substances. It is necessary to develop an environmentally friendly manufacturing method that minimizes the emission of pollutants and a heat dissipation substrate structure suitable therefor. SUMMARY

[0007] TECHNICAL PROBLEM

[0008] The present application has been made to solve the above problems, and aims to provide a heat dissipation substrate for a semiconductor including a thick electrode metal plate having a thickness of 0.2 mm or more and a manufacturing method thereof.

[0009] The present application aims to provide a heat dissipation substrate for a semiconductor having a structure that realizes excellent heat dissipation performance, improves dielectric strength, and has high peel strength by including a thick electrode metal plate.

[0010] In addition, the present application aims to provide a manufacturing method of a heat dissipation substrate for a semiconductor, and the manufacturing method of a heat dissipation substrate for a semiconductor according to the present application is a method of effectively patterning a thick electrode metal plate and effectively manufacturing a heat dissipation substrate for a semiconductor capable of providing excellent insulation performance and high peel strength in an environmentally friendly manner.

[0011] SOLUTION TO THE PROBLEM

[0012] To solve the above problems, a heat dissipation substrate for a semiconductor according to an embodiment of the present application includes an electrode metal layer in which an electrode pattern for mounting a semiconductor element is formed through a pattern space, a metal base constituting a heat sink that diffuses and dissipates heat emitted from the semiconductor element through heat conduction, an insulating layer having electrical insulation and disposed between the electrode metal layer and the metal base, and a groove and a reinforcing protrusion, the groove being formed in at least one of a surface of the metal base that interfaces with the insulating layer and a surface of the electrode metal layer that interfaces with the insulating layer, the reinforcing protrusion being formed by filling the inside of the groove with the same material as that of the insulating layer, and the pattern space including a portion that is vertically machined from the surface of the electrode metal layer.

[0013] The pattern space can be cut to a depth deeper than the bottom surface of the electrode metal layer and shallower than the bottom surface of the insulating layer to expose the insulating layer.

[0014] The pattern space can further include a portion formed by isotropic etching.

[0015] The cross section of the groove and the reinforcing protrusion can be dovetail-shaped.

[0016] In a manufacturing method of a semiconductor heat dissipation substrate according to an embodiment of the present application, a pattern space is formed so that an electrode metal layer forms an electrode pattern, the electrode metal layer is joined with an insulating layer formed on a metal base or a ceramic base having insulating properties, and the manufacturing method of the semiconductor heat dissipation substrate includes: a cutting step of cutting from one side of the electrode metal layer to a predetermined depth shallower than the thickness of the electrode metal layer to leave a remaining portion to form a groove pattern; and an etching step of etching the remaining portion left along the groove pattern while the electrode metal layer is joined with the insulating layer or the ceramic base to form the electrode pattern; in the etching step, the remaining portion is etched while being arranged on the side opposite to the surface of the electrode metal layer joined with the insulating layer or the ceramic base.

[0017] A manufacturing method of a semiconductor heat dissipation substrate according to an embodiment of the present application includes: a joining step of forming a multilayer heat dissipation substrate joined in the form of sequentially stacking a metal base, an insulating layer, and an electrode metal layer; a cutting step of cutting from the surface of the electrode metal layer along the shape of a pre-designed electrode pattern to form a groove having a depth shallower than the bottom surface of the electrode metal layer, thereby forming a groove pattern leaving a remaining portion having a predetermined thickness between adjacent electrode patterns; and an etching step of electrically insulating the adjacent electrode patterns by completely etching the remaining portion to expose the insulating layer; in the joining step, the electrode metal layer and the metal base are joined via the insulating layer, but before the joining step, a groove is formed on the surface of the electrode metal layer or the metal base in contact with the insulating layer, and then a vacuum heat pressing process is performed to form a reinforcing protrusion connected with the insulating layer while being joined.

[0018] The cross section of the groove and the reinforcing protrusion can be dovetail-shaped.

[0019] A method of manufacturing a heat dissipation substrate for a semiconductor according to an embodiment of the present application includes: a cutting step of cutting from a surface of an electrode metal layer along a shape of a pre-designed electrode pattern to form a groove having a depth shallower than a bottom surface of the electrode metal layer, thereby forming a groove pattern leaving a remaining portion having a predetermined thickness between adjacent electrode patterns; a bonding step of bonding in a form of sequentially stacking a metal base, an insulating layer, and the electrode metal layer such that the bottom surface of the electrode metal layer which is flat is in contact with the insulating layer; and an etching step of electrically insulating the adjacent electrode patterns by completely etching the remaining portion to expose the insulating layer; in the bonding step, the electrode metal layer and the metal base are bonded via the insulating layer, but before the bonding step, a groove is formed on a surface of the electrode metal layer or the metal base which is in contact with the insulating layer, and then a vacuum heat pressing process is performed to form a reinforcing protrusion connected to the insulating layer at the same time of bonding.

[0020] A cross section of the groove and the reinforcing protrusion can be dovetail-shaped.

[0021] A heat dissipation substrate for a semiconductor according to an embodiment of the present application includes: an electrode metal plate having a plurality of electrode patterns, a pattern space being formed between the plurality of electrode patterns such that the plurality of electrode patterns are electrically insulated from each other; a metal base disposed below the electrode metal plate to diffuse heat conducted from the electrode metal plate; an insulating layer formed between the electrode metal plate and the metal base; and an insulating material filling portion filling the pattern space and a peripheral portion outside an electrode pattern group composed of the plurality of electrode patterns, directly contacting side surfaces of the plurality of electrode patterns to support the side surfaces of the plurality of electrode patterns.

[0022] The insulating layer and the insulating material filling portion can be made of the same electrically insulating resin to constitute an integrally formed insulating portion.

[0023] The heat dissipation substrate for a semiconductor can further include an insulating ceramic web embedded in the insulating layer between the electrode metal plate and the metal base.

[0024] The metal base can further include a stepped portion formed by cutting a portion below the pattern space and the peripheral portion to be lower than an upper surface located directly below the plurality of electrode patterns, and the insulating material filling portion can be extended to directly contact side surfaces and a bottom surface of the stepped portion.

[0025] The heat dissipation substrate for a semiconductor can further include a first notch portion recessed in a side surface of the plurality of electrode patterns, or a second notch portion recessed in a side surface of a stepped portion of the metal base, and the insulating material filling portion can fill the first notch portion or the second notch portion.

[0026] In a method of manufacturing a heat dissipation substrate for a semiconductor according to an embodiment of the present application, the substrate heat dissipation substrate includes a plurality of electrode patterns, a pattern space formed between the plurality of electrode patterns to electrically insulate the plurality of electrode patterns, and a peripheral portion surrounding an outer side of an electrode pattern group composed of the plurality of electrode patterns, the method of manufacturing the heat dissipation substrate for a semiconductor includes: forming a groove pattern corresponding to the pattern space and the peripheral portion by cutting one side of an electrode metal plate to be formed into the plurality of electrode patterns to a predetermined depth shallower than a thickness of the electrode metal plate to leave a remaining portion; printing an insulating resin on at least the electrode metal plate side of one side of the electrode metal plate on which the groove pattern is formed and one side of a metal base facing the one side of the electrode metal plate so that the groove pattern is filled with the insulating material and the electrode metal plate and the metal base are joined via the insulating resin; and separating the plurality of electrode patterns from each other by removing the remaining portion.

[0027] In removing the remaining portion, the removing can be performed by cutting the remaining portion.

[0028] In joining the electrode metal plate and the metal base, the insulating resin can be printed on one side of the electrode metal plate and one side of the metal base, respectively, and the joining can be performed in a state in which an insulating ceramic web is interposed between the one side of the electrode metal plate and the one side of the metal base on which the insulating resin is printed.

[0029] A method of manufacturing a heat dissipation substrate for a semiconductor according to an embodiment of the present application includes: forming a multilayer substrate in which a metal base, an insulating layer, and an electrode metal plate are sequentially stacked; forming a groove pattern corresponding to a pattern space defining a plurality of electrode patterns and a peripheral portion surrounding an outer side of an electrode pattern group composed of the plurality of electrode patterns by cutting the multilayer substrate from the electrode metal plate side to a predetermined depth deeper than an upper surface of the metal base; and forming an insulating material filling portion by filling an insulating resin in the groove pattern and curing the insulating resin.

[0030] In forming the groove pattern, a first notch portion recessed in a side surface of the plurality of electrode patterns or a second notch portion recessed in a side surface of a stepped portion of the metal base can be formed.

[0031] Effects of the Invention

[0032] According to the present application, there is provided a semiconductor heat dissipation substrate including a thicker electrode metal plate having a thickness of 0.2 mm or more and a manufacturing method of the semiconductor heat dissipation substrate which can effectively produce the same.

[0033] According to the present application, there is provided a semiconductor heat dissipation substrate having a structure in which a thicker electrode metal plate is included to achieve excellent heat dissipation performance, improve dielectric strength, and have high peel strength.

[0034] Further, according to the present application, there is provided a manufacturing method of a semiconductor heat dissipation substrate, which is a method of effectively patterning a thicker electrode metal plate and effectively manufacturing a semiconductor heat dissipation substrate capable of providing excellent insulation performance and high peel strength.

[0035] Further, according to the present application, etching and plating processes, which cause environmental pollution, are excluded, and a mechanical processing process, which does not use or discharge toxic compounds, heavy metal compounds, or the like, is used instead of the etching and plating processes, thereby having an effect that a semiconductor heat dissipation substrate can be manufactured through an environmentally friendly process. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A power semiconductor module according to an embodiment of the present application is shown.

[0037] Figure 2 An electrode patterning process of a semiconductor heat dissipation substrate according to an embodiment of the present application is shown.

[0038] Figure 3 An electrode patterning process using a cutting machine tool as an embodiment of the present application is shown.

[0039] Figure 4 A manufacturing method of a semiconductor heat dissipation substrate according to an embodiment of the present application is shown.

[0040] Figure 5 A manufacturing method of a semiconductor heat dissipation substrate according to an embodiment of the present application is shown.

[0041] Figure 6 A manufacturing method of a semiconductor heat dissipation substrate according to an embodiment of the present application is shown.

[0042] Figure 7 A manufacturing method of a semiconductor heat dissipation substrate according to an embodiment of the present application is shown.

[0043] Figure 8 A manufacturing method of a semiconductor heat dissipation substrate according to an embodiment of the present application is shown.

[0044] Figure 9A manufacturing method of a heat dissipation substrate for a semiconductor according to an embodiment of the present application is shown.

[0045] Figure 10 A heat dissipation substrate for a semiconductor according to an embodiment of the present application is shown.

[0046] Figure 11 A heat dissipation substrate for a semiconductor according to an embodiment of the present application is shown.

[0047] Figure 12 A power semiconductor module to which a heat dissipation substrate for a semiconductor according to an embodiment of the present application is applied is shown.

[0048] Figure 13 A heat dissipation substrate for a semiconductor according to an embodiment of the present application is shown.

[0049] Figure 14 A manufacturing process of the above-described Figure 13 heat dissipation substrate for a semiconductor is shown.

[0050] Figure 15 A heat dissipation substrate for a semiconductor according to an embodiment of the present application is shown.

[0051] Figure 16 A manufacturing process of the above-described Figure 15 heat dissipation substrate for a semiconductor is shown.

[0052] Figure 17 A heat dissipation substrate for a semiconductor according to an embodiment of the present application is shown.

[0053] Figure 18 A manufacturing process of the above-described Figure 17 heat dissipation substrate for a semiconductor is shown.

[0054] Figure 19 A heat dissipation substrate for a semiconductor according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0055] Hereinafter, various embodiments of the present application will be described with reference to the accompanying drawings. The technical spirit of the present application can be more clearly understood through the embodiments. Furthermore, the present application is not limited to the embodiments described below, but can be modified in various forms within the scope of the technical spirit of the present application. Meanwhile, the same reference numerals denote the same elements having common characteristics in the viewpoint of the present application, and the explanation of the elements having the same reference numerals can be omitted in the description with respect to other drawings. In the present specification, the directions of up, down, upper surface, bottom surface, and the like are based on the directions shown in the drawings.

[0056] Figure 1 A power semiconductor module according to an embodiment of the present application is shown.

[0057] In the (a) section, the power semiconductor module M according to an embodiment of the present application includes a semiconductor heat dissipation substrate 101 and a power semiconductor element 301. The power semiconductor element 301 is mounted on the electrode pattern 31 on the upper surface of the semiconductor heat dissipation substrate 101, and is electrically connected by wire bonding 302.

[0058] The (b) section shows the I-I' cross section shown in the (a) section. The semiconductor heat dissipation substrate 101 includes a metal base 10, an insulating layer 20, and an electrode metal layer 30 from the lower side of the drawing. The metal base 10 can be made of a metal such as copper, aluminum, etc. having excellent thermal conductivity, and the insulating layer 20 can include a synthetic resin, an oxide, or a nitride having electrical insulation. The insulating layer 20 is preferably made of a material having excellent thermal conductivity and heat resistance in addition to electrical insulation, and has adhesion or cohesion, so as to be used for bonding the metal base 10 and the electrode metal layer 30. The electrode metal layer 30 can be made of a metal such as copper, copper-manganese alloy, etc. having low resistivity and excellent thermal conductivity. The electrode pattern 31 is formed through a pattern space 32 formed by removing a portion of the electrode metal layer 30 to the bottom surface to expose the insulating layer 20. Here, the thickness of the electrode metal layer 30 is preferably 0.2 mm or more.

[0059] Figure 2 An electrode patterning process of a semiconductor heat dissipation substrate according to an embodiment of the present application is shown.

[0060] The (a) section shows an example of a mass production process in which the electrode metal layer 30 is patterned using a plunge-cut machine tool E so that a plurality of circuit patterns corresponding to respective semiconductor modules are arranged in an array on the electrode metal layer 30 constituting the upper surface of a large-area multi-layer heat dissipation substrate B.

[0061] The (b) section shows the configuration of the plunge-cut machine tool E in detail (for a detailed description of the configuration, refer to Korean Patent No. 10-1336087). By cutting while maintaining a predetermined depth d, a groove pattern 32E constituting the pattern space is formed.

[0062] Figure 3 An electrode patterning process using a cutting machine tool as an embodiment of the present application is shown.

[0063] This figure illustrates a method for manufacturing a semiconductor heat dissipation substrate M0 according to a first embodiment. With a metal base 10, an insulating layer 20, and an electrode metal layer 30 sequentially stacked from the bottom, a pattern space 32 is formed using a fixed-depth cutting machine tool E. The depth of the pattern space 32 is greater than the thickness of the electrode metal layer 30, and only the insulating layer 20 is exposed in the pattern space 32.

[0064] Figure 4 This drawing illustrates a method for manufacturing a semiconductor heat sink substrate according to an embodiment of the present invention. This drawing also illustrates a method for manufacturing a semiconductor heat sink substrate M1 according to a second embodiment.

[0065] In part (a), with Figure 3 Similarly, in the embodiment, a multilayer heat dissipation substrate 101 is formed by stacking a metal base 10, an insulating layer 20 and an electrode metal layer 30 sequentially from the bottom, and a mask pattern 41 in the form of an electrode pattern is formed on the top of the electrode metal layer 30.

[0066] In part (b), a depth-cutting machine tool E is used to form a groove pattern 32E corresponding to the pattern space in the portion of the unprinted mask pattern 41. At this time, a remaining portion with a thickness t of 0.05 mm to 0.1 mm is left on the bottom surface of the groove pattern 32E.

[0067] In section (c), the remaining portion of the bottom surface of the aforementioned groove pattern is removed by etching, thereby exposing the insulating layer 20. When the multilayer heat sink 101 is cut into sections corresponding to each module, the heat sink M1 for semiconductors is completed.

[0068] Figure 5 This drawing illustrates a method for manufacturing a semiconductor heat sink substrate according to an embodiment of the present invention. The accompanying drawing also illustrates a method for manufacturing a semiconductor heat sink substrate M1 according to a third embodiment.

[0069] In part (a), a groove pattern 32E is formed on the upper surface of the electrode metal layer 30 using a fixed-depth cutting machine tool E. At this time, a remaining portion 320 with a predetermined thickness t is left on the bottom surface of the groove pattern 32E. Here, the predetermined thickness t is related to... Figure 4 The thickness is the same in the embodiments. In addition, a substrate on which an insulating layer 20 is stacked on top of the metal base 10 is prepared.

[0070] In part (b), the electrode metal layer 30, in which the groove pattern 32E is formed in part (a) above, is bonded to the substrate on which the insulating layer 20 is stacked on top of the metal base 10. The bonding can be performed using a vacuum hot pressing method. Alternatively, an adhesive with excellent thermal conductivity can be used for bonding, or the insulating layer 20 can be used as an adhesive layer.

[0071] In the (c) section, the remaining portion 320 of the bottom surface of the groove pattern is removed by etching, thereby exposing the insulating layer 20. When the heat dissipation substrate is cut to correspond to each module, the semiconductor heat dissipation substrate Ml is completed.

[0072] Figure 6 A manufacturing method of a semiconductor heat dissipation substrate according to an embodiment of the present application is shown. The present drawing shows a manufacturing method of a semiconductor heat dissipation substrate M2 according to a fourth embodiment.

[0073] In the (a) section, a groove pattern 32E is formed in the electrode metal layer 30, and a remaining portion 321 having a predetermined thickness t is left. As in the embodiment of Figure 5 The difference from the (a) section of the embodiment of Figure 5 is that the opposite surface of the mask pattern 42 is processed by the plunge-cut machine tool E. In addition, a substrate in which the insulating layer 20 is stacked on the upper surface of the metal base 10 is prepared.

[0074] In the (b) section, the electrode metal layer 30 in which the groove pattern 32E is formed in the above (a) section is joined to the substrate in which the metal base 10 and the insulating layer 20 are stacked. At this time, the surface in which the groove pattern is formed is made to be in contact with the insulating layer 20, so that the surface in which the mask pattern 42 and the remaining portion 321 are formed becomes the upper surface.

[0075] In the (c) section, the exposed remaining portion 321 from the surface in which the mask pattern 42 is formed is removed by etching. Instead of etching, the above-mentioned remaining portion 321 can be additionally cut by the above-mentioned plunge-cut machine tool E. In this case, the cutting depth of the above-mentioned plunge-cut machine tool E should be deeper than the thickness t of the above-mentioned remaining portion 321, and should not exceed the depth of the above-mentioned pattern space 32. As a result, a structure in which the insulating layer 20 is exposed through the pattern space 32 is formed. When the multilayer heat dissipation substrate is cut to correspond to each module, the semiconductor heat dissipation substrate M2 is completed.

[0076] Figure 7 A manufacturing method of a semiconductor heat dissipation substrate according to an embodiment of the present application is shown. The present drawing shows a manufacturing method of a semiconductor heat dissipation substrate M3 according to a fifth embodiment.

[0077] In the (a) section, the ceramic base 11 serves as a heat sink. A multilayer heat dissipation substrate is prepared in which the electrode metal layer 30 is joined to the ceramic base 11, and a mask pattern 41 is formed on the upper surface of the electrode metal layer 30. The ceramic base 11 can be made of a material such as aluminum nitride (AIN), silicon carbide (SiC), etc., and a technique such as Direct Copper Bonding (DCB), Active Metal Brazing (AMB), etc., which has already been commercialized, can be applied to join the above-described ceramic base 11 and the electrode metal layer 30.

[0078] When the groove pattern 32E is formed by using the depth-gauge cutting machine tool E, a remaining portion 320 having a predetermined depth t is left. In order to prevent the cutting tool from penetrating the electrode metal layer 30 and directly contacting the ceramic base 11, a margin is left.

[0079] In the (b) section, the above-described remaining portion 320 is removed by etching from the upper surface, and the ceramic base 11 is exposed through the pattern space 32. When the multilayer heat dissipation substrate is cut to correspond to each module, the semiconductor heat dissipation substrate M3 is completed.

[0080] Figure 8 A manufacturing method of a semiconductor heat dissipation substrate according to an embodiment of the present application is shown. The present drawing shows a manufacturing method of a semiconductor heat dissipation substrate M3 according to a sixth embodiment.

[0081] In the (a) section, as in the (a) section of Embodiment 1, Figure 5 In the (a) section, as in the (a) section of Embodiment 1, Figure 7 the material of the ceramic base 11 is the same as the material described in Embodiment 1.

[0082] In the (b) section, the electrode metal layer 30 in which the groove pattern 32E is formed in the (a) section in such a manner that the remaining portion 320 is left on the bottom surface is joined to the ceramic base 11 so that the remaining portion 320 side is in contact with the ceramic base 11. As for the joining, the above-described DCB or AMB technique, etc., can be used.

[0083] In the (c) section, as in the (b) section of Embodiment 1, Figure 7 In the (c) section, as in the (b) section of Embodiment 1,

[0084] Figure 9A manufacturing method of a heat dissipating substrate for semiconductor according to an embodiment of the present application is shown. The present drawing shows a manufacturing method of a heat dissipating substrate for semiconductor M4 according to a seventh embodiment.

[0085] In the (a) section, the surface opposite to the mask pattern 42 is processed using the depth-cutting machine tool E to form a groove pattern 32E in the electrode metal layer 30, and a remaining portion 321 having a predetermined depth t is left. In addition, the ceramic base 11 is prepared. Figure 6 In the (a) section, the surface opposite to the mask pattern 42 is processed using the depth-cutting machine tool E to form a groove pattern 32E in the electrode metal layer 30, and a remaining portion 321 having a predetermined depth t is left. In addition, the ceramic base 11 is prepared.

[0086] In the (b) section, the ceramic base 11 and the electrode metal layer 30 are joined in a state where the mask pattern 42 and the remaining portion 321 are positioned on the ceramic base 11 toward the ceramic base 11 on the groove pattern 32E side and on the upper surface opposite thereto. The joining technique is the same as that described in the embodiment of Figure 8

[0087] In the (c) section, the remaining portion 321 is removed by etching. Instead of etching, the depth-cutting machine tool E can be used to additionally cut the remaining portion 321. In this case, the cutting depth of the depth-cutting machine tool E should be deeper than the thickness t of the remaining portion 321 and not exceed the depth of the pattern space 32. When the multilayer heat dissipating substrate is cut to correspond to each module, the heat dissipating substrate for semiconductor M4 is completed.

[0088] Figure 10 A heat dissipating substrate for semiconductor according to an embodiment of the present application is shown.

[0089] The heat dissipating substrate for semiconductor M5 according to the present embodiment is characterized in that the metal base 12 is integrally formed with the heat sink structure H. The electrode metal layer 30 and the insulating layer 20 can be formed in the same manner as any one of the embodiments described above. Figures 3 to 6 On the other hand, instead of the metal base 12 described above, a ceramic base integrally formed with the heat sink structure can be employed.

[0090] On the other hand, in the embodiments described above, the cross-sectional profile of the step portion forming the boundary between the pattern space 32 and the electrode pattern 31 is formed vertically or almost vertically with respect to the two surfaces from the surface side of the electrode metal layer 30 to the surface exposing the insulating layer 20 or the ceramic base 11.

[0091] In the embodiments of Figure 3 , Figure 6 or Figure 9 , in the case where the pattern space 32 is formed using only the depth-cutting machine tool E without an etching process, the step portion is substantially formed vertically, and in the embodiments of Figures 4 to 9 ​In the embodiment, in the case where the remaining portions 320, 321 are removed by an etching process, the thickness t of the remaining portions is less than 0.1 mm, i.e., a very small portion of the electrode metal layer 30, and thus even if the remaining portions are removed by an isotropic wet etching process, the radius of curvature R of the portion where the step portion meets the insulating layer 20 or the ceramic base 11 is formed to be 0.1 mm or less. Thus, excellent insulating properties can be obtained between two electrode patterns 31 adjacent across the pattern space 32.

[0092] Figure 11 A semiconductor heat dissipating substrate according to an embodiment of the present application is shown.

[0093] In the semiconductor heat dissipating substrate M6 according to the present embodiment, either one side surface or both side surfaces of the surface of the metal base 10 which meets the insulating layer 20 and the surface of the electrode metal layer 30 which meets the insulating layer 20 can further include reinforcing protrusions 21, 23. The cross section of the reinforcing protrusions 21, 23 is dovetail-shaped. As shown in the drawing, the reinforcing protrusions 21, 23 can be formed by filling a groove having a dovetail-shaped cross section with the same material as that of the insulating layer 20. As the material of the insulating layer 20, an epoxy resin or the like having excellent electrical insulation and thermal conductivity can be used.

[0094] In the manufacturing process of the semiconductor heat dissipating substrate M6 according to the present embodiment, a dovetail-shaped groove is processed on the metal base 10 and / or the electrode metal layer 30, an epoxy resin is interposed between the metal base 10 and the electrode metal layer 30, and then they are joined by a vacuum heat pressing process, so that the reinforcing protrusions 21, 23 can be formed.

[0095] Even if there is a difference in linear expansion coefficient between the material constituting the metal base 10 and the material constituting the electrode metal layer 30, the reinforcing protrusions 21, 23 formed as described above can prevent the interface between the layer and the insulating layer 20 from peeling due to the difference in linear expansion coefficient.

[0096] Figure 12 A power semiconductor module using the semiconductor heat dissipating substrate according to an embodiment of the present application is shown.

[0097] A power semiconductor module M7 to which the semiconductor heat dissipation substrate 101 according to an embodiment of the present application is applied includes a power semiconductor element 301. The power semiconductor element 301 can be mounted on at least one of the plurality of electrode patterns 31 formed on the upper surface of the semiconductor heat dissipation substrate 102, and electrically connected by wire bonding 302. On the other hand, as another example, the power semiconductor element can include a plurality of input / output terminals or pad electrodes, and they can be surface mounted (SMT) on the plurality of electrode patterns 31 of the semiconductor heat dissipation substrate 102. The plurality of electrode patterns 31 are formed in an island shape surrounded by an insulator in the pattern space 32 filled between the electrode patterns and the peripheral portion of the electrode pattern group composed of the plurality of electrode patterns.

[0098] Figure 13 A semiconductor heat dissipation substrate according to an embodiment of the present application is shown. The present drawing is a cross-sectional view of the semiconductor heat dissipation substrate corresponding to the II-II' section of the above-described Figure 12

[0099] The semiconductor heat dissipation substrate M7 includes a metal base 10, an insulating portion 21 including an insulating layer 20, and a plurality of electrode patterns 31 formed from an electrode metal plate 30, from the lower side of the drawing. A pattern space 32 is arranged between the plurality of electrode patterns 31, and the pattern space 32 electrically insulates the adjacent electrode patterns from each other. The pattern space 32 and the peripheral portion of the electrode pattern group composed of the plurality of electrode patterns 31 are filled with an insulating material.

[0100] The metal base 10 is made of a metal having excellent thermal conductivity such as copper, aluminum, or the like. The metal base 10 can also be formed of a thick metal plate or a metal block. On the other hand, although not shown in the drawing, a heat dissipation fin structure can be formed on the bottom surface or the like of the metal base 10 to increase the heat dissipation effect by expanding the contact area with the outside.

[0101] ​The insulating portion 21 is composed of an insulating layer 20 and an insulating material filling portion. The insulating layer 20 is located between the metal base 10 and the electrode metal plate 30. The insulating material filling portion is formed by filling insulating material in the pattern space 32 and the peripheral portion of the plurality of pattern electrodes 31. The insulating layer 20 can include synthetic resin, oxide or nitride having electrical insulation. The insulating layer 20 is preferably made of a material having excellent thermal conductivity and heat resistance in addition to electrical insulation, and has adhesion or cohesion, so as to be also used for joining the metal base 10 and the electrode metal plate 30. The insulating material filling portion can be made of the same material as the material of the insulating layer 20, so as to integrally form the insulating portion 21. As for the material forming the insulating portion 21, the above-mentioned material satisfying the conditions of electrical insulation, thermal conductivity and heat resistance, etc. can be exemplified, for example, epoxy synthetic resin.

[0102] The electrode metal plate 30 can be made of metal such as copper, copper-manganese alloy, aluminum and nickel having low resistivity, excellent thermal conductivity and workability. The electrode pattern 31 is divided by the pattern space 32 formed by removing a portion of the electrode metal plate 30 to the bottom surface to expose the insulating layer 20.

[0103] Here, the thickness T of the electrode metal plate 30 is preferably 0.2 mm or more. Also, when the thickness of the insulating layer 20 is defined as tl, the thickness of the peripheral portion and the insulating space 32 is defined as t2, and the height from the bottom surface of the insulating layer 20 to the upper surface of the electrode pattern is defined as H, they have the following relationship:

[0104] <Formula 1> tl < t2 ≤ H

[0105] In other words, preferably, the height of the insulating body filled in the peripheral portion and the insulating space 32 is higher than the bottom surface of the electrode pattern 31 and lower than or equal to the upper surface of the electrode pattern 31. This structure can improve the dielectric strength between the plurality of electrode patterns 31, and also improve the dielectric strength between the heat dissipation substrate 101 for semiconductor and external circuit. Further, the structure is a structure in which at least a portion of the electrode pattern 31 is embedded in the insulating material filling portion, so as to improve the peeling strength with respect to the plurality of electrode patterns 31.

[0106] Figure 14 A process of manufacturing the above-mentioned heat dissipation substrate for semiconductor Figure 13 is shown.

[0107] First, as shown in (a), a groove pattern 330 having a predetermined depth corresponding to the pattern space and the peripheral portion is formed by cutting (milling) one face of the electrode metal plate 30 using a cutting tool such as an end mill. The depth of the groove pattern 330 is shallower than the thickness of the electrode metal plate 30, so as to leave a remaining portion 331 on the bottom face of the groove pattern 330. When viewed in a plan view, the remaining portion 331 can be left on all portions corresponding to the pattern space and the peripheral portion. Further, the thickness of the remaining portion 331 is preferably less than 0.2 mm, and more preferably, the remaining portion 331 can be formed to have a thickness of 0.05 to 0.1 mm.

[0108] As shown in (b), an insulating resin 200, such as an epoxy resin, is printed on the upper face of the metal base 10, and the same insulating resin 200 is printed on the face on which the groove pattern 330 is formed, and in this state, it is turned over so that the two faces on which the insulating resin 200 is applied face each other.

[0109] As shown in (c), the members prepared in the process of (b) are joined by a vacuum heat pressing process. As a result, the insulating resins 200 printed on the opposite faces of the two members are integrally cured to form the insulating portion 21, as described above.

[0110] However, unlike the examples of (b) and (c), either one of the upper face of the metal base 10 and the face of the electrode metal plate 30 on which the groove pattern 330 is formed can be coated with the insulating resin 200 to a sufficient thickness, and then they can be joined to each other.

[0111] Next, as shown in (d), the remaining portion 331, that is, the portion in which the plurality of electrode patterns 31 divided by the groove pattern 330 are connected to each other in a thin thickness, is removed by etching or milling, so as to form the pattern space 32. Further, by cutting along the cutting line CT shown in the drawing, a semiconductor heat dissipation substrate of a single module unit is completed.

[0112] Figure 15 A semiconductor heat dissipation substrate according to an embodiment of the present application is shown.

[0113] The semiconductor heat dissipation substrate M8 according to the present embodiment is similar to the semiconductor heat dissipation substrate M7 according to the above-described Figure 13The semiconductor heat dissipating substrate 101 according to the embodiment differs from the semiconductor heat dissipating substrate 101 according to the above embodiment in that the insulating web 25 is included in the insulating portion 22, and the rest is the same. The insulating web 25 can be a solid inorganic insulating material, such as a web made of a ceramic material. The insulating web 25 is made of a ceramic material having higher specific resistance and higher thermal conductivity than the insulating material constituting the rest of the insulating portion 22, and thus can contribute to improving the dielectric strength and thermal conductivity between the electrode pattern 31 and the metal base 10. In addition, it can contribute to suppressing thermal expansion of the insulating portion 22 or increasing mechanical strength.

[0114] Figure 16 A process of manufacturing the semiconductor heat dissipating substrate according to the above embodiment is shown. Figure 15

[0115] First, the (a) portion shows a state in which the insulating web 25 is arranged between the opposing insulating resins 200 in the state in which the electrode metal plate 30 and the metal base 10 are joined with the insulating web 25 interposed in the insulating portion 22, in the same manner as in the (b) portion of the above embodiment. Figure 15

[0116] The (b) portion shows a state in which the vacuum heat pressing process is performed in the above state, the electrode metal plate and the metal base 10 are joined with the insulating web 25 interposed in the insulating portion 22, and the remaining portion is removed by the etching or milling process shown in the (d) portion of the above embodiment, to form the plurality of electrode patterns 31, the pattern spaces 32, and the peripheral portion. Also, when cutting is performed along the cutting line CT, the semiconductor heat dissipating substrate according to the embodiment is completed. Figure 3

[0117] Figure 17 A semiconductor heat dissipating substrate according to an embodiment of the present application is shown.

[0118] In the semiconductor heat dissipating substrate M9 according to the embodiment, the portion constituting the pattern space 322 between the plurality of electrode patterns 31 and the portion constituting the peripheral portion outside the plurality of electrode patterns 31 in the insulating portion 23 are formed in the following structure. First, the upper surface of the insulating portion 23 is formed to have the same height as the upper surface height of the plurality of electrode patterns 31. Next, in the relevant portion, the bottom surface of the insulating portion 23 is expanded in the thickness direction of the metal base 11. That is, it has a structure in which the rest of the upper surface of the metal base 11 except for the portion facing the bottom surface of the electrode pattern 31 is excavated to a predetermined depth and is filled with an insulator.

[0119] ​​​In other words, when the thickness of the electrode pattern 31 is defined as T, the thickness of the insulating layer between the electrode pattern 31 and the metal base 11 is defined as t1, and the thickness of the portion of the insulating part 23 corresponding to the pattern space 322 and the peripheral part is defined as t3, the following relationship is established.

[0120] <Equation 2>T+t1 <t3

[0121] In the semiconductor heat dissipation substrate 103 with this structure, the sides of the electrode pattern 31 are completely embedded in the insulating portion 23, as described above. Figure 13 Similarly, in this embodiment, the dielectric strength between the multiple electrode patterns 31 and between the electrode patterns 31 and the external conductor is improved, and the peel strength of the electrode patterns 31 is also improved. Furthermore, in the insulating portion 23, the pattern space 322 and the peripheral portion are supported by engaging with the stepped portion formed on the upper part of the metal base 11, thus exhibiting strong resistance to lateral loads and preventing deformation or breakage due to the difference in thermal expansion coefficients between the metal and the insulator. With this structure, the peel strength between the insulating portion 23 and the metal base 11 is also improved.

[0122] Figure 18 The above-mentioned manufacturing process is shown. Figure 17 The process of heat dissipation substrates for semiconductors.

[0123] As shown in section (a), a multilayer substrate is prepared by sequentially stacking a metal base 10, an insulating layer 20, and an electrode metal plate 30 from the bottom. Similar to the embodiment described above, the multilayer substrate can be prepared by printing or coating insulating resin between the two opposing surfaces of the metal base 10 and the electrode metal plate 30 and bonding them together using a vacuum hot-pressing process.

[0124] As shown in section (b), the surface of the electrode metal plate 30 is machined, for example, by milling with an end mill, thereby cutting the pattern space 322 between the plurality of electrode patterns 31 and the outer periphery of the electrode pattern group formed by the plurality of electrode patterns 31 to a depth greater than the top surface of the metal base 10, thereby forming a groove pattern. That is, by cutting to a depth greater than the sum of the thickness T of the electrode metal plate 30 and the thickness t1 of the insulating layer 20, a step portion 111 lower than the portion facing the bottom surface of the electrode patterns 31 is formed on the upper part of the metal base 11.

[0125] Then, as shown in section (c), insulating resin is filled into the cut portion, i.e., the groove pattern described above, and cured to form an insulating material filling portion 201. The insulating material filling portion 201 can be formed of the same insulating material as the insulating layer 20. Thus, the insulating layer 20 and the insulating material filling portion 201 are integrally formed in the insulating portion 23. When cut along the CT line, a semiconductor heat dissipation substrate for a semiconductor module is completed.

[0126] Figure 19 A semiconductor heat dissipation substrate is shown according to an embodiment of the present invention.

[0127] The semiconductor heat sink substrate M10 according to this embodiment and the above-described... Figure 6 The difference between the semiconductor heat dissipation substrate 103 in the embodiments is that the semiconductor heat dissipation substrate M10 includes a first notch 312 and / or a second notch 122. The first notch 312 is formed on the side of the electrode pattern 31 by machining, and the second notch 122 is formed on the side of the stepped portion 121 of the metal base 12. Furthermore, apart from the structural difference in the insulating material filling portion 202 formed by filling the first notch 312 and / or the second notch 122, the remaining configuration of this embodiment is the same as described above. Figure 6 The configuration is the same as that of the embodiments.

[0128] Here, the first notch 312 and the second notch 122 can be formed by recessing inward from the side perpendicular to the top / bottom of the electrode pattern 31 and the metal base 12. (Refer to above) Figure 7 In the cutting process described in part (b), the first notch 312 and the second notch 122 can be formed by using a form tool manufactured to correspond to the shape of the groove pattern and the notch, instead of a general end mill. The notch can be formed simultaneously with the groove pattern, or it can be formed after the groove pattern is formed. The cutting process using the form tool can be performed in a direction parallel to the metal base 12.

[0129] The semiconductor heat sink substrate 104 according to this embodiment may include both the first notch 312 and the second notch 122, or it may include only one of the first notch 312 and the second notch 122. The first notch 312 and the second notch 122 significantly improve the peel strength of the semiconductor heat sink substrate 104 by engaging the side surfaces of the insulating material filling portion 202 with the electrode pattern 31 and the metal base 12, respectively.

[0130] Industrial availability

[0131] The present application can be used to manufacture a heat dissipation substrate having both a heat dissipation plate function and a circuit board function for mounting semiconductor elements. The semiconductor heat dissipation substrate according to the present application can be used to manufacture a semiconductor module including a power semiconductor element or a high-output LED, etc.

Claims

1. A heat dissipation substrate for semiconductors, characterized in that, The semiconductor heat dissipation substrate includes: an electrode metal plate having a plurality of electrode patterns, a pattern space being formed between the plurality of electrode patterns so that the plurality of electrode patterns are electrically insulated from each other; a metal base disposed below the electrode metal plate to diffuse heat conducted from the electrode metal plate; an insulating layer formed between the electrode metal plate and the metal base; and an insulating material filling portion filling the pattern space and a peripheral portion outside an electrode pattern group composed of the plurality of electrode patterns, directly contacting side surfaces of the plurality of electrode patterns to support the side surfaces of the plurality of electrode patterns, the metal base further includes a stepped portion formed by cutting a portion below the pattern space and the peripheral portion to be lower than an upper surface located directly below the plurality of electrode patterns, and the insulating material filling portion is extended to directly contact side surfaces and a bottom surface of the stepped portion. a first notch portion recessed in the side surfaces of the plurality of electrode patterns or a second notch portion recessed in the side surfaces of the stepped portion of the metal base, the insulating material filling portion filling the first notch portion or the second notch portion.

2. The heat dissipating substrate for a semiconductor according to claim 1, wherein 3. A method of manufacturing a semiconductor heat dissipation substrate including a plurality of electrode patterns, a pattern space formed between the plurality of electrode patterns to electrically insulate the plurality of electrode patterns from each other, and a peripheral portion surrounding an outside of an electrode pattern group composed of the plurality of electrode patterns, the method of manufacturing the semiconductor heat dissipation substrate characterized by comprising: forming a groove pattern corresponding to the pattern space and the peripheral portion by cutting one side of an electrode metal plate to be formed with the plurality of electrode patterns to a predetermined depth shallower than a thickness of the electrode metal plate, so as to leave a remaining portion corresponding to all of the pattern space and the peripheral portion when viewed in a plan view; printing an insulating resin on at least the electrode metal plate side of one side of the electrode metal plate on which the groove pattern is formed and one side of a metal base facing the one side of the electrode metal plate, so that the groove pattern is filled with an insulating material, and joining the electrode metal plate and the metal base via the insulating resin; and separating the plurality of electrode patterns from each other by removing the remaining portion. In removing the remaining portion, the removing is performed by cutting or etching the remaining portion.

4. The method of producing a heat dissipation substrate for a semiconductor according to claim 3, wherein 5. The method of manufacturing the semiconductor heat dissipation substrate according to claim 3, wherein in joining the electrode metal plate and the metal base, an insulating resin is printed on one side of the electrode metal plate and one side of the metal base, respectively, and the joining is performed in a state in which an insulating ceramic web is interposed between the one side of the electrode metal plate and the one side of the metal base on which the insulating resin is printed. ​

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