Packaging method and packaging structure of fan-out stacked chips

Abstract

The present invention provides a packaging method and packaging structure of a fan-out stacked chip, the method comprising: fixing a first chip in a slot body on a dummy chip, the first chip being provided with a plurality of conductive through holes; hybrid bonding the second chip with the first chip, the orthographic projection of the second chip on the dummy chip overlapping with the dummy chip; separating the dummy chip from the second chip, and forming a plurality of conductive convex columns on the surface of the second chip facing the first chip and on the outside of the first chip; forming a first plastic encapsulation layer, the first plastic encapsulation layer wrapping the first chip and the plurality of conductive convex columns; forming a second plastic encapsulation layer, the second plastic encapsulation layer wrapping the first chip, the second chip and the first plastic encapsulation layer; forming a redistribution layer on the surface of the first chip and the first plastic encapsulation layer away from the second chip. The present invention performs wafer-level hybrid bonding through wafer expansion technology, realizes high-density interconnection while improving production efficiency, and realizes ultra-thin packaging.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a packaging method and a packaging structure of a fan-out stacked chip. Background Art

[0002] Electronic products are becoming smaller and smaller, and their functions are becoming more and more powerful. As a result, semiconductor packaging needs to be thinner and lighter, and the interconnection density needs to be higher. Traditional packaging cannot meet future needs. Figure 1 It is a typical traditional multi-layer chip packaging structure. Chips 1 and 2 are vertically stacked on a substrate 6 through patch films 3 and 4, and chips 1 and 2 are connected to the substrate 6 through gold wires 5. Chips 1, 2 and gold wires 5 are protected by plastic encapsulation material 7. The entire package is connected to the outside world through solder balls 8. In the current package, due to the height limit of gold wire molding and the protection distance limit from plastic encapsulation material to gold wire, the height from plastic encapsulation material to the surface of chip 2 is strictly limited and cannot be continuously reduced. At the same time, due to the material limitation and the limitation of substrate strength, the production difficulty of ultra-thin substrates is extremely high in substrate process, which limits the application of traditional packages in ultra-thin multi-layer packages. Moreover, whether it is traditional wire bonding connection or inverted solder connection, the pad spacing is above 30um, and it is extremely difficult to continuously reduce it.

[0003] In view of the above problems, it is necessary to propose a packaging method and packaging structure of a fan-out stacked chip that is reasonably designed and can effectively solve the above problems. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art and provide a fan-out stacked chip packaging structure and a packaging method.

[0005] One aspect of the present invention provides a packaging method for a fan-out stacked chip, the method comprising:

[0006] Fixing a first chip in a slot on the dummy chip, wherein the first chip is provided with a plurality of conductive through holes;

[0007] hybrid bonding the second chip to the first chip, wherein the orthographic projection of the second chip on the dummy chip overlaps with the dummy chip;

[0008] Separating the dummy chip from the second chip, and forming a plurality of conductive protrusions on the surface of the second chip facing the first chip and on the outer side of the first chip;

[0009] forming a first plastic encapsulation layer, wherein the first plastic encapsulation layer encapsulates the first chip and the plurality of conductive protrusions;

[0010] forming a second plastic encapsulation layer, wherein the second plastic encapsulation layer encapsulates the first chip, the second chip and the first plastic encapsulation layer;

[0011] A redistribution layer is formed on the surface of the first chip and the first plastic packaging layer facing away from the second chip. The redistribution layer is electrically connected to the first chip through the multiple conductive through holes, and the redistribution layer is electrically connected to the second chip through the multiple conductive protrusions.

[0012] Optionally, a first passivation layer and a first metal pad are provided on a surface of the first chip facing the second chip, and a second passivation layer and a second metal pad are provided on a surface of the second chip facing the first chip;

[0013] The hybrid bonding of the second chip to the first chip includes:

[0014] bonding the first passivation layer of the first chip to the second passivation layer of the second chip; and,

[0015] Bonding the first metal pad of the first chip to the second metal pad of the second chip.

[0016] Optionally, before hybrid bonding the second chip to the first chip, the method further includes:

[0017] forming an adhesive on the first surface of the dummy sheet and the first chip, and allowing a portion of the adhesive to fill a gap between the dummy sheet and the first chip;

[0018] The adhesive on the first surface of the first chip is completely removed, while the adhesive on a portion of the surface of the dummy chip is retained to expose the first passivation layer and the first metal pad of the first chip.

[0019] Optionally, before separating the dummy chip from the second chip, the method further includes:

[0020] The bonded first chip and the dummy chip are thinned to expose the conductive through holes of the first chip.

[0021] Optionally, forming the second plastic encapsulation layer includes:

[0022] Thinning the first plastic encapsulation layer on a side facing away from the second chip to expose the plurality of conductive protrusions, so that the first plastic encapsulation layer is flush with the surface of the first chip;

[0023] The thinned first plastic encapsulation layer and the second surface of the first chip are fixed to a temporary carrier, and then the second plastic encapsulation layer is formed.

[0024] Optionally, forming a redistribution layer on the surfaces of the first chip and the first plastic packaging layer facing away from the second chip includes:

[0025] Separating the first chip and the first plastic packaging layer from the temporary carrier;

[0026] forming a dielectric layer on the surfaces of the first chip and the first plastic packaging layer facing away from the second chip and on the plurality of conductive protrusions;

[0027] Patterning the dielectric layer, and forming a redistribution layer on the patterned dielectric layer;

[0028] The redistribution layer is patterned, and solder balls are formed on the patterned redistribution layer.

[0029] Optionally, the surface of the first chip protrudes from the surface of the dummy chip.

[0030] Another aspect of the present invention provides a fan-out stacked chip packaging structure, the packaging structure comprising a first chip, a second chip, a plurality of conductive protrusions, a hybrid bonding structure, a first plastic packaging layer, a second plastic packaging layer and a redistribution layer;

[0031] The first chip is provided with a plurality of conductive through holes;

[0032] The second chip is disposed on the first chip through the hybrid bond and structural stacking;

[0033] The plurality of conductive protrusions are arranged on a side of the second chip facing the first chip and on an outer side of the first chip;

[0034] The first plastic packaging layer wraps the first chip and the plurality of conductive protrusions;

[0035] The second plastic sealing layer wraps the first chip, the second chip and the first plastic sealing layer;

[0036] The redistribution layer is arranged on the surface of the first chip and the first plastic packaging layer away from the second chip; wherein

[0037] The redistribution layer is electrically connected to the first chip through the plurality of conductive vias, and the redistribution layer is electrically connected to the second chip through the plurality of conductive protrusions.

[0038] Optionally, the hybrid bonding structure includes a first passivation layer and a first metal pad disposed on a surface of the first chip facing the second chip, and a second passivation layer and a second metal pad disposed on a surface of the second chip facing the first chip;

[0039] The first passivation layer and the second passivation layer are bonded together, and the first metal pad and the second metal pad are bonded together.

[0040] Optionally, the packaging structure further includes a dielectric layer and solder balls;

[0041] The dielectric layer is arranged on the second plastic packaging layer and the surface of the first chip facing away from the second chip, the redistribution layer is arranged on the dielectric layer, and the solder balls are arranged on the redistribution layer.

[0042] The present invention provides a packaging method and packaging structure for fan-out stacked chips. The packaging method fixes a first chip in a slot on a dummy chip, adjusts two first chips and second chips of different sizes to the same size through the dummy chip, and then performs wafer-level hybrid bonding on the first chip and the second chip. The wafer-level hybrid bonding is performed through wafer expansion technology to achieve high-density interconnection while improving production efficiency.

[0043] The present invention separates the dummy chip from the second chip, and forms a plurality of conductive protrusions on the surface of the second chip facing the first chip and on the outer side of the first chip, and leads out part of the signal of the second chip through the plurality of conductive protrusions. The first chip is provided with a plurality of conductive through holes, and a redistribution layer is formed on the surface of the first chip and the first plastic packaging layer facing away from the second chip. The conductive through holes, the conductive protrusions and the fan-out redistribution layer replace the traditional substrate interconnection, thereby reducing the package size.

[0044] In the present invention, since direct wafer bonding is adopted between the first chip and the second chip, the thickness after bonding is the same as the thickness of the chip body, the packaging height is reduced to the greatest extent, and an ultra-thin multi-layer high-density stacking package is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of a typical conventional multi-layer chip packaging structure in the prior art;

[0046] Figure 2 A schematic flow chart of a packaging method for fan-out stacked chips according to another embodiment of the present invention;

[0047] Figure 3 to Figure 17 FIG. 4 is a schematic diagram of a packaging process of a fan-out stacked chip according to another embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0049] like Figure 2 As shown, one aspect of the present invention provides a packaging method S100 for a fan-out stacked chip, the packaging method S100 comprising:

[0050] S110, fixing a first chip in a slot on a dummy chip, wherein the first chip is provided with a plurality of conductive through holes.

[0051] Specifically, Figure 1 As shown, the back side of the first chip 110 is fixed to the slot body on the dummy chip 120 by means of a patch adhesive 121, wherein the surface of the first chip 110 protrudes from the surface of the dummy chip 120. A plurality of conductive through holes 130 are arranged on the front side of the first chip 110, and the plurality of conductive through holes 130 can be distributed at equal intervals, wherein the conductive through holes can be through silicon vias. Through silicon via technology is used to realize vertical electrical interconnection of the through silicon vias, thereby reducing the package height.

[0052] like Figure 3 As shown, the surface of the first chip 110 facing away from the tank body is provided with a first passivation layer 111 and a first metal pad 112. In this embodiment, the material of the first passivation layer 111 may be a silicon dioxide passivation layer or a silicon nitride layer, or other materials that can play a passivation role, which is not specifically limited in this embodiment. In this embodiment, the material of the first metal pad 112 is copper, or other metal materials, which is not specifically limited in this embodiment.

[0053] S120: hybrid bonding the second chip to the first chip, wherein the orthographic projection of the second chip on the dummy chip overlaps with the dummy chip.

[0054] Exemplarily, before hybrid bonding the second chip to the first chip, the method further includes:

[0055] First, an adhesive is formed on the first surfaces of the dummy sheet and the first chip, and a portion of the adhesive is filled into the gap between the dummy sheet and the first chip.

[0056] Specifically, specifically, such as Figure 4 As shown, adhesive 122 is formed on the first surfaces of the dummy sheet 120 and the first chip 110, that is, adhesive 122 is formed on the front surfaces of the dummy sheet 120 and the first chip 110, and part of the adhesive 121 is filled into the gap between the dummy sheet 120 and the first chip 110, so that the first chip 110 is completely fixed in the groove of the dummy sheet 120. Because the first surface of the first chip 110 protrudes from the surface of the dummy sheet 120, the adhesive 122 on the dummy sheet 120 is thicker than the adhesive 122 on the first surface of the first chip 110, so that when the first chip 110 and the second chip 140 are hybrid bonded, the second chip 140 can be attached to the dummy sheet 120.

[0057] Secondly, the adhesive on the first surface of the first chip is completely removed, while retaining a portion of the adhesive on the surface of the dummy chip to expose the first passivation layer and the first metal pad of the first chip.

[0058] Specifically, Figure 5 As shown, the adhesive 121 on the first surface of the first chip 110 can be subjected to surface grinding and polishing and chemical cleaning treatment, and the adhesive 122 on the first surface of the first chip 110 can be completely removed, while the adhesive 122 on the surface of a portion of the dummy chip 120 is retained, exposing the first passivation layer 111 and the first metal pad 112 of the first chip 110. The adhesive 122 on the surface of a portion of the dummy chip 120 can fix the dummy chip 120 on the second chip 140.

[0059] Specifically, Figure 6 As shown, the surface of the first chip 110 facing the second chip 140 is provided with a first passivation layer 111 and a first metal pad 112, that is, as mentioned above, the surface of the first chip 110 facing away from the slot body is provided with a first passivation layer 111 and a first metal pad 112, wherein each first metal pad 112 on the first chip 110 corresponds to each conductive via 130 of the first chip 110. The surface of the second chip 140 facing the first chip 110 is provided with a second passivation layer 141 and a second metal pad 142.

[0060] Exemplarily, hybrid bonding the second chip to the first chip includes:

[0061] First, the first passivation layer of the first chip is bonded to the second passivation layer of the second chip.

[0062] Specifically, Figure 6 As shown, the first passivation layer 111 of the first chip 110 is bonded to the second passivation layer 141 of the second chip 140. In this embodiment, the first passivation layer 111 and the second passivation layer 141 can be silicon dioxide layers or silicon nitride layers, or other materials that can play a passivation role, which are not specifically limited in this embodiment. First, the first passivation layer 111 and the second passivation layer 141 are aligned, and the first passivation layer 111 and the second passivation layer 141 are connected by high-temperature pressing.

[0063] Next, the first metal pad of the first chip is bonded to the second metal pad of the second chip.

[0064] Specifically, Figure 6 As shown, the first metal pad 112 of the first chip 110 is bonded to the second metal pad 142 of the second chip 140. In this embodiment, the material of the first metal pad 112 and the second metal pad 142 is copper, or other metal materials, which are not specifically limited in this embodiment. The first metal pad 112 is aligned with the second metal pad 152, and the connection is achieved by high-temperature pressing and utilizing the thermal expansion of copper.

[0065] like Figure 6As shown, the orthographic projection of the second chip 140 on the dummy film 120 coincides with the dummy film 120, that is, the size of the second chip 140 is consistent with the size of the dummy film 120. The dummy film is used to adjust the first chip 110 and the second chip 140 of two different sizes to the same size, and wafer-level hybrid bonding is performed through wafer expansion technology to achieve high-density interconnection while improving production efficiency.

[0066] S130, separating the dummy chip from the second chip, and forming a plurality of conductive protrusions on a surface of the second chip facing the first chip and on an outer side of the first chip.

[0067] Exemplarily, before separating the dummy chip from the second chip, the method further includes:

[0068] The bonded first chip and the dummy chip are thinned to expose the conductive through holes of the first chip.

[0069] Specifically, Figure 7 As shown, the back of the bonded first chip 110 and the dummy film 120 is thinned to expose the conductive via 130, that is, the through silicon via, on the first chip 110. The residual thickness of the first chip 110 and the dummy film 120 after thinning is less than 40 um. By thinning the back of the first chip 110 and the dummy film 120 to expose the conductive via 130 to achieve electrical connection, the package height is further reduced.

[0070] like Figure 8 As shown, the first chip 110 and the dummy chip 120 are irradiated with laser or ultraviolet light. The light wave is determined according to the characteristics of the adhesive 122. Under the action of the light wave energy, the adhesive 122 loses its viscosity. Fig. 9 As shown, the dummy chip 120 is separated from the second chip 140, that is, the second chip 140 is separated from the dummy chip 120, leaving the mixed first chip 110 and the second chip 140. It should be noted that the second chip 140 and the dummy chip 120 can also be separated by other methods, which are not specifically limited in this embodiment.

[0071] like Fig.10 As shown, after the second chip 140 is separated from the dummy chip 120, a plurality of conductive protrusions 150 are formed on the surface of the second chip 140 facing the first chip 110 and on the outer side of the first chip 110 by electroplating or other processes. In other words, the plurality of conductive protrusions 150 are located at the position of the dummy chip 120 before the second chip 140 is separated from the dummy chip 120. The plurality of conductive protrusions 150 are electroplated on the second metal pad 142. The plurality of conductive protrusions 150 can be used to lead out some signals of the second chip 140. Compared with substrate interconnection, the conductive protrusions 150 are used to realize vertical electrical interconnection, thereby reducing the package height.

[0072] In this embodiment, the conductive protrusion 150 is a metal copper pillar, and other metal materials may also be selected as needed.

[0073] S140, forming a first plastic encapsulation layer, wherein the first plastic encapsulation layer encapsulates the first chip and the plurality of conductive protrusions.

[0074] Specifically, Fig.11 As shown, after forming a plurality of conductive protrusions 150, a first plastic encapsulation layer 160 is formed on the side of the first chip 110 away from the second chip 140. The first plastic encapsulation layer 160 wraps the plurality of conductive protrusions 150 and the first chip 110, and the first plastic encapsulation layer 160 protects the plurality of conductive protrusions 150 and the first chip. The plastic encapsulation method can be a film layer vacuum pressing or a traditional plastic encapsulation process, which is not specifically limited in this embodiment.

[0075] S150: forming a second plastic encapsulation layer, wherein the second plastic encapsulation layer encapsulates the first chip, the second chip, and the first plastic encapsulation layer.

[0076] First, the first plastic encapsulation layer is thinned on a side facing away from the second chip to expose the conductive protrusions, so that the first plastic encapsulation layer is flush with the second surface of the first chip.

[0077] Specifically, Fig.12 As shown, the side of the first plastic encapsulation layer 160 facing away from the second chip 140 is thinned by grinding, polishing and chemical cleaning to expose the conductive protrusion 150 and the conductive through hole 130, so that the first plastic encapsulation layer 160 is flush with the second surface of the thinned first chip 110, that is, the first plastic encapsulation layer 160 is flush with the back side of the thinned first chip 110.

[0078] Secondly, the thinned first plastic encapsulation layer and the second surface of the first chip are fixed to a temporary carrier, and then the second plastic encapsulation layer is formed.

[0079] Specifically, the above packaging steps are to package multiple first chips 110, multiple dummy chips 120 and multiple second chips 140 at the same time, and after the first plastic packaging layer 160 is thinned on the side away from the second chip 140, the multiple chip assemblies after thinning need to be cut to form Fig.12 The following packaging steps are then performed, such as Fig.13 As shown, the thinned first plastic encapsulation layer 160 and the surface of the first chip 110 facing away from the second chip 140 are fixed to the temporary carrier 161 by adhesive, that is, the back side of the first chip 110 is used as the contact surface, and according to the final package size, they are attached one by one to the temporary carrier 161 with temporary bonding adhesive, and then plastic encapsulated to form a structure as shown in FIG. Fig.14The second plastic encapsulation layer 170 shown in the figure wraps the first chip 110, the second chip 140 and the first plastic encapsulation layer 160. The plastic encapsulation method can be a film vacuum lamination or a traditional plastic encapsulation process, which is not specifically limited in this embodiment.

[0080] S160. Form a redistribution layer on the surfaces of the first chip and the first plastic packaging layer facing away from the second chip, wherein the redistribution layer is electrically connected to the first chip through the multiple conductive through holes, and the redistribution layer is electrically connected to the second chip through the multiple conductive protrusions.

[0081] Exemplarily, forming a redistribution layer on the surfaces of the first chip and the first plastic packaging layer facing away from the second chip includes:

[0082] First, the first chip and the first plastic packaging layer are separated from the temporary carrier.

[0083] Specifically, Fig.15 As shown, the first chip 110 and the first plastic encapsulation layer 160 are separated from the temporary carrier 161, that is, the temporary carrier 161 is removed. The separation method can be thermal separation, laser separation, ultraviolet light separation, mechanical separation and other methods, which are currently commonly used temporary bonding separation methods. The separation method is not specifically limited in this embodiment and can be selected according to actual needs.

[0084] Next, a dielectric layer is formed on the first chip and the surface of the first plastic packaging layer facing away from the second chip and the plurality of conductive protrusions.

[0085] Specifically, Fig.16 As shown, a dielectric layer 180 is coated on the surface of the first chip 110 and the first plastic layer 160 facing away from the second chip 140 and the plurality of conductive protrusions 150. The material of the dielectric layer 180 can be polyimide (PI), polybenzoxazole (PBO), etc., and the coating method is usually wafer spin coating, which is not specifically limited in this embodiment.

[0086] Thirdly, the dielectric layer is patterned, and a redistribution layer is formed on the patterned dielectric layer.

[0087] Specifically, Fig.16As shown, the dielectric layer 180 is patterned by a photolithography process, and a redistribution layer 190 is formed on the patterned dielectric layer 180. The redistribution layer 190 is electrically connected to the second chip 140 through the conductive vias 130 and a plurality of conductive protrusions 150. The method for forming the redistribution layer 190 may be electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition, etc., which is not specifically limited in this embodiment. The material of the redistribution layer 190 may be metal titanium and metal copper, which is not limited in this embodiment.

[0088] The redistribution layer 190 is electrically connected to the first chip 110 through a plurality of conductive vias 130 to lead out the signal of the first chip 110 ; the redistribution layer 190 is electrically connected to the second chip 140 through a plurality of conductive bosses 150 to lead out the signal of the second chip 140 .

[0089] Finally, the redistribution layer is patterned, and solder balls are formed on the patterned redistribution layer.

[0090] Specifically, Fig.17 As shown, the redistribution layer 190 is patterned by a photolithography process, and a plurality of solder balls 200 are formed on the patterned redistribution layer 190 , which is electrically connected to the outside through the solder balls 200 .

[0091] The present invention provides a packaging method and packaging structure for fan-out stacked chips. The packaging method fixes a first chip in a slot on a dummy chip, adjusts two first chips and second chips of different sizes to the same size through the dummy chip, and then performs wafer-level hybrid bonding on the first chip and the second chip. The wafer-level hybrid bonding is performed through wafer expansion technology to achieve high-density interconnection while improving production efficiency.

[0092] The present invention separates the dummy chip from the second chip, and forms a plurality of conductive protrusions on the surface of the second chip facing the first chip and on the outer side of the first chip, and leads out part of the signal of the second chip through the plurality of conductive protrusions. The first chip is provided with a plurality of conductive through holes, and a redistribution layer is formed on the surface of the first chip and the first plastic packaging layer facing away from the second chip. The conductive through holes, the conductive protrusions and the fan-out redistribution layer replace the traditional substrate interconnection, thereby reducing the package size.

[0093] In the present invention, since direct wafer bonding is adopted between the first chip and the second chip, the thickness after bonding is the same as the thickness of the chip body, the packaging height is reduced to the greatest extent, and an ultra-thin multi-layer high-density stacking package is achieved.

[0094] like Fig.17As shown, another aspect of the present invention provides a fan-out stacked chip packaging structure 100, the packaging structure 100 includes a first chip 110, a second chip 140, a plurality of conductive protrusions 150, a hybrid bonding structure (not shown in the figure), a first plastic encapsulation layer 160, a second plastic encapsulation layer 170 and a redistribution layer 190.

[0095] The first chip 110 is provided with a plurality of conductive vias 130. The plurality of conductive vias 130 may be distributed at equal intervals, wherein the conductive vias may be through silicon vias. Through silicon via technology is used to achieve vertical electrical interconnection of the through silicon vias, thereby reducing the package height.

[0096] The second chip 140 is disposed on the first chip 110 through the hybrid bond and structure stacking.

[0097] A plurality of conductive protrusions 150 are arranged on the side of the second chip 140 facing the first chip 110 and outside the first chip 110. The conductive protrusions 150 can be used to lead out the signals of the second chip 140, and the conductive protrusions 150 replace the traditional substrate interconnection, further reducing the package height.

[0098] The first plastic encapsulation layer 160 wraps the first chip 110 and the plurality of conductive protrusions 150 , and the first plastic encapsulation layer 160 protects the first chip 110 and the plurality of conductive protrusions 150 .

[0099] The second plastic encapsulation layer 170 wraps the first chip 110 , the second chip 140 and the first plastic encapsulation layer 160 , and the second plastic encapsulation layer 170 protects the first chip 110 , the second chip 140 and the first plastic encapsulation layer 160 .

[0100] The redistribution layer 190 is arranged on the surface of the first chip 110 and the first plastic encapsulation layer 160 away from the second chip 140, and the redistribution layer 190 is electrically connected to the second chip 140 through the conductive vias 130 and the plurality of conductive protrusions 150. The fan-out redistribution technology is used to replace the traditional substrate interconnection, and the package size is further reduced. The method for forming the redistribution layer 190 can be electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition and other processes, which are not specifically limited in this embodiment. The material of the redistribution layer 190 can be metal titanium and metal copper, and the material of the redistribution layer 190 is not limited in this embodiment.

[0101] For example, Fig.17As shown, the hybrid bonding structure includes a first passivation layer 111 and a first metal pad 112 arranged on the surface of the first chip 110 facing the second chip 140, and a second passivation layer 141 and a second metal pad 142 arranged on the surface of the second chip 140 facing the first chip 110, the first passivation layer 111 and the second passivation layer 141 are bonded to each other, and the first metal pad 112 and the second metal pad 142 are bonded to each other.

[0102] For example, Fig.17 As shown, the package structure 100 further includes a dielectric layer 180 and solder balls 200. The dielectric layer 180 is disposed on the surface of the second plastic encapsulation layer 170 and the first chip 110 away from the second chip 140. A redistribution layer 190 is disposed on the dielectric layer 180, and the solder balls 200 are disposed on the redistribution layer 190. The package structure is electrically connected to the outside through the solder balls 200.

[0103] It should be noted that, in the present embodiment, the first passivation layer 111 and the second passivation layer 141 can be both silicon dioxide layers, or other materials that can play a passivation role. The material of the first metal pad 112 and the second metal pad 142 is metallic copper, or other metal materials, which are not specifically limited in the present embodiment. The material of the dielectric layer 180 can be polyimide (PI), polybenzoxazole (PBO), etc., and the coating method is usually wafer spin coating, which is not specifically limited in the present embodiment. The material of the redistribution layer 190 can be metallic titanium and copper, or other metal materials, which are not specifically limited in the present embodiment.

[0104] In the packaging structure of the fan-out stacked chip of the present invention, the second chip is hybrid-bonded to the first chip through a hybrid bonding structure, which realizes high-density interconnection while improving production efficiency, and reduces the packaging height to the greatest extent. A plurality of conductive protrusions are arranged on the side of the second chip facing the first chip, and are arranged on the outside of the first chip, and part of the signal of the second chip is led out through the conductive protrusions. The redistribution layer is arranged on the surface of the first chip and the first plastic sealing layer away from the second chip. Compared with the substrate interconnection, the conductive protrusions, the conductive through holes and the redistribution layer are used to further reduce the packaging height, and achieve high-density and ultra-thin packaging.

[0105] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A packaging method for fan-out stacked chips, characterized in that: The method comprises: Fixing the first chip in the slot on the dummy sheet, so as to adjust the first chip and the second chip of different sizes to the same size through the dummy sheet; wherein the first chip is provided with a plurality of conductive through holes; Performing wafer-level hybrid bonding on the second chip and the first chip, wherein the orthographic projection of the second chip on the dummy chip overlaps with the dummy chip; Separating the dummy chip from the second chip, and forming a plurality of conductive protrusions on the surface of the second chip facing the first chip and on the outer side of the first chip; forming a first plastic encapsulation layer, wherein the first plastic encapsulation layer encapsulates the first chip and the plurality of conductive protrusions; forming a second plastic encapsulation layer, wherein the second plastic encapsulation layer encapsulates the first chip, the second chip and the first plastic encapsulation layer; A redistribution layer is formed on the surface of the first chip and the first plastic packaging layer facing away from the second chip. The redistribution layer is electrically connected to the first chip through the multiple conductive through holes, and the redistribution layer is electrically connected to the second chip through the multiple conductive protrusions.

2. The method according to claim 1, characterized in that A first passivation layer and a first metal pad are disposed on a surface of the first chip facing the second chip, and a second passivation layer and a second metal pad are disposed on a surface of the second chip facing the first chip; The hybrid bonding of the second chip to the first chip includes: Bonding the first passivation layer of the first chip to the second passivation layer of the second chip; as well as, Bonding the first metal pad of the first chip to the second metal pad of the second chip.

3. The method according to claim 2, characterized in that Before hybrid bonding the second chip to the first chip, the method further includes: forming an adhesive on the first surface of the dummy sheet and the first chip, and allowing a portion of the adhesive to fill a gap between the dummy sheet and the first chip; The adhesive on the first surface of the first chip is completely removed, while the adhesive on a portion of the surface of the dummy chip is retained to expose the first passivation layer and the first metal pad of the first chip.

4. The method according to claim 1, characterized in that: Before separating the dummy chip from the second chip, the method further includes: The bonded first chip and the dummy chip are thinned to expose the conductive through holes of the first chip.

5. The method according to claim 1, characterized in that The forming of the second plastic encapsulation layer comprises: Thinning the first plastic encapsulation layer on a side facing away from the second chip to expose the plurality of conductive protrusions, so that the first plastic encapsulation layer is flush with the second surface of the first chip; The thinned first plastic encapsulation layer and the second surface of the first chip are fixed to a temporary carrier, and then the second plastic encapsulation layer is formed.

6. The method according to claim 5, characterized in that The forming of a redistribution layer on the surface of the first chip and the first plastic packaging layer facing away from the second chip comprises: Separating the first chip and the first plastic packaging layer from the temporary carrier; forming a dielectric layer on the surfaces of the first chip and the first plastic packaging layer facing away from the second chip and on the plurality of conductive protrusions; Patterning the dielectric layer, and forming a redistribution layer on the patterned dielectric layer; The redistribution layer is patterned, and solder balls are formed on the patterned redistribution layer.

7. The method according to any one of claims 1 to 5, characterized in that: The surface of the first chip protrudes from the surface of the dummy chip.

8. A fan-out stacked chip packaging structure, characterized in that: The packaging method according to any one of claims 1 to 7 is adopted, wherein the packaging structure comprises a first chip, a second chip, a plurality of conductive protrusions, a hybrid bonding structure, a first plastic packaging layer, a second plastic packaging layer and a redistribution layer; The first chip is provided with a plurality of conductive through holes; The second chip is stacked on the first chip through the hybrid bonding structure; The plurality of conductive protrusions are arranged on a side of the second chip facing the first chip and on an outer side of the first chip; The first plastic packaging layer wraps the first chip and the plurality of conductive protrusions; The second plastic sealing layer wraps the first chip, the second chip and the first plastic sealing layer; The redistribution layer is arranged on the surface of the first chip and the first plastic packaging layer away from the second chip; wherein The redistribution layer is electrically connected to the first chip through the plurality of conductive vias, and the redistribution layer is electrically connected to the second chip through the plurality of conductive protrusions.

9. The packaging structure according to claim 8, characterized in that: The hybrid bonding structure includes a first passivation layer and a first metal pad disposed on a surface of the first chip facing the second chip, and a second passivation layer and a second metal pad disposed on a surface of the second chip facing the first chip; The first passivation layer and the second passivation layer are bonded together, and the first metal pad and the second metal pad are bonded together.

10. The packaging structure according to claim 8 or 9, characterized in that: The packaging structure also includes a dielectric layer and solder balls; The dielectric layer is arranged on the second plastic packaging layer and the surface of the first chip facing away from the second chip, the redistribution layer is arranged on the dielectric layer, and the solder balls are arranged on the redistribution layer.

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