Semiconductor structure and method for manufacturing the same

Abstract

The embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate, the substrate having a conductive structure therein; a first lower electrode and a second lower electrode stacked in sequence, the first lower electrode being located between the second lower electrode and the substrate, the first lower electrode being in a columnar shape, the second lower electrode being in a groove shape, the first lower electrode being electrically connected to the conductive structure; a first dielectric layer and a first upper electrode, the first dielectric layer covering the side wall surface of the first lower electrode, the first upper electrode being located on a side of the first dielectric layer away from the first lower electrode; a second dielectric layer and a second upper electrode, the second dielectric layer covering the inner wall and bottom surface of the second lower electrode, the second upper electrode being filled in the groove of the second lower electrode. The present invention provides a new capacitor structure, which is beneficial to improving the capacitance value of a single capacitor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the semiconductor field, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As semiconductor structures shrink in size, it becomes increasingly difficult to increase the capacitance of a single capacitor structure or maintain the capacitance of a single capacitor. When using the same dielectric material, the capacitance can only be increased by increasing the surface area of ​​the electrode plate or reducing the thickness of the dielectric layer, but the latter may lead to excessive leakage current.

[0003] Therefore, changing the capacitor structure to increase the surface area of ​​the electrode plate is an important development direction for increasing the capacitance value of the capacitor structure. Summary of the invention

[0004] The embodiments of the present invention provide a semiconductor structure and a manufacturing method thereof, which are beneficial to improving the capacitance value of a single capacitor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, wherein the substrate has a conductive structure; a first lower electrode and a second lower electrode stacked in sequence, wherein the first lower electrode is located between the second lower electrode and the substrate, the first lower electrode is columnar, the second lower electrode is groove-shaped, and the first lower electrode is electrically connected to the conductive structure; a first dielectric layer and a first upper electrode, wherein the first dielectric layer covers the side wall surface of the first lower electrode, and the first upper electrode is located on a side of the first dielectric layer away from the first lower electrode; a second dielectric layer and a second upper electrode, wherein the second dielectric layer covers the inner wall and bottom surface of the second lower electrode, and the second upper electrode is filled in the groove of the second lower electrode.

[0006] In addition, in the direction perpendicular to the surface of the substrate, the orthographic projection of the top surface of the first lower electrode is located within the orthographic projection of the bottom surface of the second lower electrode. This is conducive to ensuring that when the formation position of the second lower electrode has a certain position deviation, the top surface of the first lower electrode 13 and the bottom surface of the second lower electrode have a larger contact area, ensuring a good signal transmission effect between the first lower electrode and the second lower electrode, thereby improving the performance of the semiconductor structure.

[0007] In addition, the semiconductor structure further comprises: a support layer, the support layer being located between adjacent first lower electrodes. The provision of the support layer is conducive to preventing the first lower electrode from tipping over or collapsing due to its large aspect ratio, and is also conducive to increasing the maximum height of the first lower electrode relative to the substrate, so that the first lower electrode has a larger sidewall surface area, and further the first lower electrode can be used to form a capacitor structure with a larger capacitance value.

[0008] In addition, the support layer includes a first support layer and a second support layer, wherein the first support layer is located between the bottoms of the first lower electrodes, and the second support layer is located between the tops of the first lower electrodes. The use of multiple support layers located between the bottoms and between the tops of the first lower electrodes to support the first lower electrode is beneficial to preventing the bottom or top of the first lower electrode from tilting, thereby ensuring that the first lower electrode has good structural stability.

[0009] In addition, the support layer further includes a third support layer, the third support layer is located between the bottom of the second lower electrode, and the third support layer is used to support the second lower electrode. The third support layer is arranged to prevent the bottom of the second lower electrode from tilting, thereby ensuring that the second lower electrode has good structural stability.

[0010] In addition, a dimension of the third supporting layer between adjacent bottom portions of the second lower electrodes along the substrate surface direction is smaller than a dimension of the second supporting layer between adjacent top portions of the first lower electrodes along the substrate surface direction.

[0011] In addition, the sizes of the third supporting layer between the bottoms of adjacent second lower electrodes along the surface direction of the substrate are the same; the sizes of the second supporting layer between the tops of the first lower electrodes along the surface direction of the substrate are different.

[0012] In addition, the second supporting layer between the tops of the first lower electrodes with larger dimensions along the surface direction of the substrate is in direct contact with the first upper electrode thereunder; the second supporting layer between the tops of the first lower electrodes with smaller dimensions along the surface direction of the substrate is in direct contact with the first dielectric layer thereunder.

[0013] In addition, part of the second supporting layer and the third supporting layer are an integrated structure.

[0014] In addition, the first dielectric layer covers the first upper electrode, and the first dielectric layer has a via hole exposing the first upper electrode; the supporting layer has a backfilling portion, and the backfilling portion fills the via hole.

[0015] In addition, the first upper electrode is located between adjacent first dielectric layers, and the first upper electrode has a first gap therein.

[0016] In addition, the semiconductor structure further includes: an isolation layer, wherein the isolation layer is located between adjacent second lower electrodes and has a second gap therein.

[0017] Correspondingly, an embodiment of the present invention also provides a method for manufacturing a semiconductor structure, comprising: providing a substrate having a conductive structure therein; forming a first lower electrode electrically connected to the conductive structure, the first lower electrode being in a columnar shape; forming a first dielectric layer and a first upper electrode in sequence on the side wall surface of the first lower electrode, the first dielectric layer being located between the first lower electrode and the first upper electrode; after forming the first upper electrode, forming a second lower electrode on a side of the first lower electrode away from the substrate, the second lower electrode being in a groove shape; forming a second dielectric layer on the inner wall and bottom surface of the second lower electrode, and forming a second upper electrode filling the groove of the second lower electrode.

[0018] In addition, the step of forming the first lower electrode includes: forming a first dielectric layer on the substrate, the first dielectric layer including a first supporting layer, a first sacrificial layer, and a second supporting layer stacked in sequence in a direction perpendicular to the substrate; etching the second supporting layer, the first sacrificial layer, and the first supporting layer in sequence to form a first electrode groove exposing the conductive structure; filling the first electrode groove to form a first lower electrode.

[0019] In addition, the process steps for forming the first dielectric layer and the first upper electrode include: etching the second supporting layer to form a via; performing a wet etching process through the via to remove the first sacrificial layer; performing a first deposition process through the via to form a first dielectric layer on the side wall surface of the first lower electrode; performing a second deposition process through the via to form a first upper electrode on a side of the first dielectric layer away from the first lower electrode.

[0020] In addition, after forming the first upper electrode, the via hole is backfilled to form a backfill portion.

[0021] In addition, the process steps for forming the second lower electrode include: forming a second dielectric layer on a side of the first lower electrode away from the substrate; etching the second dielectric layer to form a second electrode groove exposing the first lower electrode, wherein the orthographic projection of the top surface of the first lower electrode is located within the orthographic projection of the bottom surface of the second electrode groove in a direction perpendicular to the surface of the substrate; and performing a third deposition process to form the second lower electrode covering the side wall and bottom surface of the second electrode groove.

[0022] In addition, the second dielectric layer includes a third supporting layer and a second sacrificial layer stacked in sequence; and the etching of the second dielectric layer includes: etching the second sacrificial layer and the third supporting layer in sequence.

[0023] In addition, after forming the second lower electrode, the second sacrificial layer located between adjacent second lower electrodes is removed; an isolation film is formed on the outer wall of the second lower electrode, and a second gap is provided between adjacent isolation films; the top of the second gap is sealed to form a sealing layer, and the sealing layer, the isolation film and the second gap constitute an isolation layer.

[0024] In addition, after forming the second lower electrode and before removing the second sacrificial layer between adjacent second lower electrodes, the method further includes: filling a third dielectric layer in the second electrode groove where the second lower electrode is formed.

[0025] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0026] In the above technical scheme, the semiconductor structure includes a first lower electrode and a second lower electrode stacked in sequence, the first lower electrode is used to form a first type of capacitor structure, and the second lower electrode is used to form a second type of capacitor structure, and the first type of capacitor structure is connected in series with the second type of capacitor structure. In this way, when the capacitance value of the semiconductor structure remains unchanged, there is no need to etch a channel with a large aspect ratio when forming any type of capacitor structure, which is beneficial to ensure that the channel structure of each type of capacitor structure meets the preset structural requirements and avoids etching defects; at the same time, since the channel length of each type of capacitor structure can be relatively short, it is beneficial to avoid the capacitor structure from tipping over or collapsing due to its high aspect ratio during the formation process, thereby reducing the process difficulty and ensuring that the semiconductor structure has a higher structural stability; in addition, since the semiconductor structure is formed by connecting different types of capacitor structures in series, the capacitor structure provided by the embodiment of the present invention can have a larger capacitance value than a single type of capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0028] Figures 1 to 23 A schematic cross-sectional structure diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0029] Figure 24 to Figure 25 A schematic cross-sectional structure diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by yet another embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0031] Figures 1 to 23 A schematic diagram of the cross-sectional structure corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention.

[0032] refer to Figure 1 , providing a substrate 110 having a conductive structure 111 therein; and forming a first dielectric layer 120 on the substrate 110 .

[0033] The conductive structure 111 may be an independent conductive structure located in the substrate 110 , or may be a conductive contact region of the substrate 110 . For example, if the substrate 110 is made of polysilicon, the conductive structure 111 may be a doped region of the substrate 110 .

[0034] In this embodiment, the first dielectric layer 120 includes a first supporting layer 121, a first sacrificial layer 122, and a second supporting layer 123 stacked in sequence in a direction perpendicular to the substrate 110, and the hardness of the first supporting layer 121 and the hardness of the second supporting layer 123 are greater than the hardness of the first sacrificial layer 122. The first supporting layer 121 and the second supporting layer 123 are used to support the first lower electrode formed subsequently, which is beneficial to prevent the first lower electrode from tipping over or collapsing.

[0035] Among them, the materials of the first supporting layer 121 and the second supporting layer 123 include nitride, and the first supporting layer 121 and the second supporting layer 123 can be formed by a single-chip or furnace-tube machine reaction using a chemical vapor deposition process or an atomic layer deposition process; the material of the first sacrificial layer 122 includes oxide or boro-phospho-silicate glass (BPSG), and the first sacrificial layer 122 can be formed by a chemical vapor deposition process.

[0036] In this embodiment, there are two supporting layers between the first lower electrodes, the first supporting layer 121 is located between the bottom of the first lower electrodes to be formed later, and the second supporting layer 123 is located between the top of the first lower electrodes to be formed later. In this way, the bottom and top of the first lower electrode can be supported and fixed at the same time, further preventing the first lower electrode from tipping over or collapsing; at the same time, since the first supporting layer 121 and the second supporting layer 123 are located at the top and bottom of the first dielectric layer 120 respectively, the first sacrificial layer 122 can exist as a whole instead of being divided into a plurality of spaced film layers, which is conducive to reducing the difficulty of removing the sacrificial layer 122 later, and reducing the difficulty of uniformly depositing the first dielectric layer through the vias on the supporting layer, ensuring that the semiconductor structure has good electrical properties.

[0037] In other embodiments, there is only a single supporting layer between the first lower electrodes, and the single supporting layer can be located between the bottoms of the first lower electrodes, between the tops of the first lower electrodes, or at any position between the first lower electrodes.

[0038] In this embodiment, since the first lower electrode is formed in the first dielectric layer 120, the thickness of the first dielectric layer 120 in a direction perpendicular to the substrate 110 is equal to the length of the channel to be formed later for filling the first lower electrode. In this embodiment, there is no specific limitation on the thickness of the first dielectric layer 120 in a direction perpendicular to the surface of the substrate 110. The thickness of the first dielectric layer 120 in a direction perpendicular to the surface of the substrate 110 may be 1000 nm to 1500 nm, for example, 1100 nm, 1250 nm or 1400 nm.

[0039] refer to Figure 2 , the second supporting layer 123 , the first sacrificial layer 122 and the first supporting layer 121 are etched in sequence to form a first electrode groove 124 exposing the conductive structure 111 .

[0040] The first electrode groove 124 is used to fill a conductive material to form a first lower electrode.

[0041] In this embodiment, a plurality of discrete first electrode grooves 124 are arranged in an array; in other embodiments, there is only a single first electrode groove or a plurality of discrete first electrode grooves are arranged irregularly.

[0042] The mask used for etching to form the first electrode groove 124 can be made using lithography or double imaging technology; in addition, the etchant for etching the first dielectric layer 120 can be a mixed gas containing SF6, CFx, Cl2 and Ar, wherein Ar mainly plays a cleaning role; in addition, the etching process includes a bias etching process, and the use of a bias etching process for etching is beneficial to improving the position accuracy of the first electrode groove 124, thereby achieving better signal transmission effects between different conductive structures.

[0043] refer to Figure 3 and Figure 4 , fill the first electrode groove 124 (refer to Figure 2 ), forming a first lower electrode film 130; and etching back the first lower electrode film 130 to form a first lower electrode 13.

[0044] In this embodiment, a deposition process is used to form the first lower electrode film 130, which fills the first electrode groove 124 and covers the top surface of the second supporting layer 123; a planarization process or a dry etching process is used to remove the first lower electrode film 130 covering the top surface of the second supporting layer 123 to form a plurality of discrete first lower electrodes 13.

[0045] The material of the first lower electrode 13 includes conductive materials such as titanium, titanium nitride or tungsten. The first lower electrode 13 can be a single-layer structure composed of a single material or a stacked-layer structure composed of multiple conductive film layers.

[0046] refer to Figure 5 and Figure 6 , the second supporting layer 123 is etched to form a via hole 125 , wherein the via hole 125 exposes the first sacrificial layer 122 .

[0047] In this embodiment, the second supporting layer 123 is etched using a mask having an opening pattern 125a, wherein the number of the opening patterns 125a is two and the shape of the opening patterns 125a is circular; in other embodiments, the number of the opening patterns may be one or more than two and the shape of the opening patterns may be square, hexagonal or the like.

[0048] The number and projection area of ​​the opening patterns 125a can be set according to the orthographic projection area of ​​the first sacrificial layer 122 that needs to be subsequently etched and removed in a direction perpendicular to the surface of the substrate 110. The larger the orthographic projection area of ​​the first sacrificial layer 122, the more the number of the opening patterns 125a and / or the larger the projection area of ​​the opening patterns 125a. This is conducive to shortening the process time of subsequently etching and removing the first sacrificial layer 122 and improving the process efficiency.

[0049] In this embodiment, in the direction perpendicular to the surface of the substrate 110, the orthographic projection of each opening pattern 125a not only covers the area between the plurality of first lower electrodes 13, but also partially overlaps with the orthographic projection of at least one first lower electrode 13. This is beneficial to enlarge the size of a single via hole 125, and the etchant can etch the first sacrificial layer 122 at a faster rate through a larger via hole 125, thereby shortening the etching process time.

[0050] In addition, three adjacent first lower electrodes 13 are arranged in an equilateral triangle, and the orthographic projection of the center of the opening pattern 125a is equidistant from the central axis of each first lower electrode 13. This helps to avoid different effects of etching of the via 125 on different first lower electrodes 13, ensures that different first lower electrodes 13 have the same or similar performance, and helps to improve the performance stability of the semiconductor structure.

[0051] In this embodiment, the first lower electrode 13 includes a first portion 13a located at the center and a second portion 13b surrounding the first portion 13a and in contact with the second support layer 123. In the process of etching the second support layer 123, since the etching selectivity of the same etching process for the second support layer 123 and the first lower electrode 13 cannot be infinite, the etchant will etch and remove the contacted second portion 13b. In this way, in the cross-sectional direction AA, the width of the via hole 125 is greater than the width of the second support layer 123 between adjacent first lower electrodes 13.

[0052] refer to Figure 7 , a wet etching process is performed through the via hole 125 to remove the first sacrificial layer 122 (refer to Figure 6 ).

[0053] Since the wet etching process etches the first sacrificial layer 122 with an etching liquid, in the process step of removing the etching liquid after the etching is completed, the flowing etching liquid will apply compressive stress to the first lower electrode 13. Providing the first supporting layer 121 and the second supporting layer 123 is conducive to preventing the first lower electrode 13 from tipping over or collapsing due to the compressive stress, thereby ensuring that the first lower electrode 13 has good structural stability.

[0054] refer to Figure 8 , a first deposition process is performed through the via hole 125 to form a first dielectric film 131 a.

[0055] The first deposition process includes a vapor deposition process or an atomic layer deposition process, and the coverage area of ​​the first dielectric film 131a is the same as the accessible area of ​​the vapor phase precursor or the carrier gas carrying the precursor. Specifically, the first dielectric film 131a covers the side wall surface and the top surface of the first lower electrode 13, the top surface of the first supporting layer 121, and the top surface and bottom surface of the second supporting layer 123.

[0056] In this embodiment, the material of the first dielectric film 131a has a high dielectric constant. The material of the first dielectric film 131a includes at least one of ZrO, AlO, HfO, SiO, NbO or SiN. The first dielectric film 131a can be a single-layer structure composed of a single material, or a stacked structure composed of multiple conductive film layers. The stacked structure can be formed by a furnace-tube or monolithic atomic layer deposition process.

[0057] refer to Fig. 9 , through via 125 (reference Figure 8 ) a second deposition process is performed to form a first upper electrode film 132a on a side of the first dielectric film 131a away from the first lower electrode 13.

[0058] The second deposition process includes a vapor deposition process or an atomic layer deposition process, and the coverage area of ​​the first upper electrode film 132 a is the same as the accessible area of ​​the vapor precursor or the carrier gas carrying the precursor.

[0059] In this embodiment, during the formation of the first upper electrode film 132a, the deposition rate of the second deposition process can be controlled so that the first upper electrode film 132a has a first gap 132b between adjacent first lower electrodes 13. The provision of the first gap 132b is conducive to reducing the bit error rate caused by coupling between adjacent capacitors.

[0060] Among them, the process steps for forming the first gap 132b may include: first performing a second deposition process with a slower deposition rate to form a first upper electrode film 132a on the side of the first dielectric film 131a away from the first lower electrode 13, and there is a gap without deposition in the first upper electrode film 132a; when the size of the gap without deposition meets the preset requirements, the deposition rate of the second deposition process is accelerated to achieve rapid sealing to form the first gap 132b.

[0061] refer to Fig.10 and Fig.11 , and sequentially etch the first upper electrode film 132a (reference Fig. 9 ) and the first dielectric film 131a (reference Fig. 9 ), forming a first upper electrode 132 and a first dielectric layer 131.

[0062] The first lower electrode 13 , the first dielectric layer 131 and the first upper electrode 132 form a first type capacitor structure, ie, a columnar capacitor structure.

[0063] In this embodiment, a portion of the first upper electrode film 132a located on the top of the second supporting layer 123 and a portion of the first upper electrode film 132a located in the second supporting layer 123 are sequentially etched, that is, the first upper electrode film 132a in the via hole 125 is etched away to form the first upper electrode 132. The purpose of etching away the first upper electrode film 132a in the via hole 125 is to reserve space for filling with an insulating medium, so that the first upper electrode 132 is electrically isolated from the second lower electrode formed subsequently, avoiding problems such as signal interference between different capacitor structures, and ensuring that the semiconductor structure has good signal stability.

[0064] In this embodiment, the purpose of etching the first dielectric film 131a is to expose the top surface of the first upper electrode 132 so that the first lower electrode 132 can be electrically connected to the subsequently formed second lower electrode, and to reduce the thickness of the semiconductor structure so that the semiconductor structure has a smaller packaging size.

[0065] In this embodiment, the first dielectric layer 131 covers the sidewalls of the via hole 125. When the first dielectric layer 131 covers the sidewalls of the via hole 125, in the cross-sectional direction AA (not shown), the width of the backfill portion formed by subsequently filling the via hole 125 is determined by the thickness of the first dielectric layer 131, and the width of the backfill portion can be greater than, less than, or equal to the width of the second supporting layer 123 between the tops of adjacent first lower electrodes 13.

[0066] In other embodiments, reference Fig.12 , the first dielectric layer 231 is only located at the bottom of the via hole 225 .

[0067] When the first dielectric layer 231 is only located at the bottom of the via hole 225, the backfill portion that subsequently fills the via hole 225 is used to isolate the first upper electrode 232 and the subsequently formed second lower electrode, as well as to isolate the adjacent first lower electrodes 23; in addition, since the width of the via hole 225 is greater than the width of the second supporting layer 223 located between the adjacent first lower electrodes 23 in the cross-sectional direction AA (not shown), the width of the backfill portion that is subsequently filled in the via hole 225 is greater than the width of the second supporting layer 223 located between the adjacent first lower electrodes 23, that is, the sizes of the second supporting layer 223 between the first lower electrodes 23 are different along the surface direction of the substrate 210.

[0068] Correspondingly, the second supporting layer 223 between the first lower electrodes 23 with larger dimensions along the surface direction of the substrate 210, that is, the backfill portion is in direct contact with the first upper electrode 232 thereunder, and the second supporting layer 223 between the tops of the first lower electrodes 23 with smaller dimensions along the surface direction of the substrate 210 is in direct contact with the first dielectric layer 231 thereunder.

[0069] refer to Fig.13 A second dielectric layer 14 is formed on a side of the first lower electrode 13 away from the substrate 110 .

[0070] In this embodiment, the second dielectric layer 14 includes a third supporting film 141a and a second sacrificial layer 142 stacked in sequence. The third supporting film 141a is used to form a third supporting layer to support and fix the subsequently formed second lower electrode, which is beneficial to prevent the subsequently formed second lower electrode from tipping over or collapsing.

[0071] In this embodiment, during the deposition process of forming the third support film 141a, the via hole 125 (see Fig.11) is backfilled to form a backfill portion of the second supporting layer 123, and the backfill portion is used to isolate the first upper electrode 132 and the second lower electrode formed subsequently.

[0072] Since the second lower electrode is subsequently formed in the second dielectric layer 14, the thickness of the second dielectric layer 14 in a direction perpendicular to the substrate 110 determines the height of the second lower electrode subsequently formed. It should be noted that the thickness of the first lower electrode 13, the thickness of the second lower electrode, and the size relationship between the two are not limited herein.

[0073] refer to Fig.14 , etch the second dielectric layer 14 (reference Fig.13 ), forming a second electrode groove 14a exposing the top surface of the first lower electrode 13.

[0074] In this embodiment, in the direction perpendicular to the surface of the substrate 110, the orthographic projection of the top surface of the first lower electrode 13 is located within the orthographic projection of the bottom surface of the second electrode groove 14a. This is conducive to ensuring that when the formation position of the second lower electrode has a certain position deviation, the top surface of the first lower electrode 13 and the bottom surface of the subsequently formed second lower electrode have a large contact area, ensuring a good signal transmission effect between the first lower electrode 13 and the second lower electrode.

[0075] In this embodiment, during the process of forming the second electrode groove 14a, a portion of the third support film 141a is etched away (refer to Fig.13 ), forming a third supporting layer 141, and the third supporting layer 141 is located between the bottoms of adjacent second electrode grooves 14a. Since the bottom size of the second electrode groove 141 is larger than the top size of the first lower electrode 13, the size of the third supporting layer 141 between the bottoms of adjacent second lower electrodes along the surface direction of the substrate 110 is smaller than the size of the second supporting layer 123 between the tops of adjacent first lower electrodes 13 along the surface direction of the substrate 110.

[0076] In this embodiment, since the backfill portion is formed in the third support film 141a (refer to Fig.13 ), so the backfill portion and the third supporting layer 141 are an integrated structure; in addition, unlike the second supporting layer 123, the third supporting layer 141 between the bottoms of adjacent second electrode grooves 14a has the same size along the surface direction of the substrate 110.

[0077] refer to Fig.15 and Fig.16 , performing a third deposition process to form a second lower electrode film 151a covering the sidewalls and bottom surface of the second electrode groove 14a and the top surface of the second sacrificial layer 142; and filling the second electrode groove 14a with a third dielectric layer 143.

[0078] Filling the third dielectric layer 143 helps to prevent subsequent process steps from causing damage to the second lower electrode film 151a located at the bottom and side walls of the second electrode groove 14a, thereby ensuring that the second lower electrode film 151a has good electrical properties; in addition, the third dielectric layer 143 also plays a role in supporting the side walls of the second lower electrode 151, thereby preventing the side walls of the second lower electrode film 151a from tipping over or collapsing after the second sacrificial layer 142 is etched away.

[0079] refer to Fig.17 , a planarization process is performed to remove the second lower electrode film 151 a covering the top surface of the second sacrificial layer 142 , and a plurality of discrete second lower electrodes 151 are formed.

[0080] In this embodiment, the top surface of the third dielectric layer 143 after the planarization process is flush with the top surface of the second lower electrode 151 ; in other embodiments, the top surface of the third dielectric layer after the planarization process is lower than the top surface of the second lower electrode.

[0081] refer to Fig.18 , remove the second sacrificial layer 142 located between the adjacent second lower electrodes 151 (refer to Fig.17 ).

[0082] In this embodiment, the second sacrificial layer 142 is etched to reserve space to form a new isolation layer, and the dielectric constant of the isolation layer is smaller than the dielectric constant of the second sacrificial layer 142. This is conducive to shielding signal interference between adjacent second lower electrodes 151 and reducing the bit error rate caused by the coupling effect.

[0083] In other embodiments, when the second sacrificial layer has a lower dielectric constant, the remaining second sacrificial layer may be used as an isolation layer to reduce the number of process steps.

[0084] refer to Fig.19 An isolation film 144 is formed on the outer wall of the second lower electrode 151, and a second gap 145 is provided between adjacent isolation films 144; the top of the second gap 145 is sealed to form a sealing layer 146, and the sealing layer 146, the isolation film 144 and the second gap 145 constitute an isolation layer 147.

[0085] In this embodiment, an atomic layer deposition process or a chemical vapor deposition process can be used to form an isolation film 144 covering the outer wall of the second lower electrode 151 and the top surface of the third supporting layer 141. The isolation film 144 is used to isolate adjacent second lower electrodes 151 to avoid electrical contact between adjacent second lower electrodes 151 when tilted, thereby ensuring that the semiconductor structure has high performance stability; air has the smallest dielectric constant, and providing an isolation layer 147 including an air gap 145 is beneficial to reducing the dielectric constant of the isolation layer 147, thereby reducing the bit error rate caused by the coupling effect of adjacent second lower electrodes 151.

[0086] In this embodiment, the material of the isolation layer 147 has a low dielectric constant, and the material of the isolation layer 147 includes cobalt silicide, carbon oxide, or nitride.

[0087] refer to Fig. 20 , remove the third dielectric layer 143 (reference Fig.19 ), exposing the bottom surface and inner wall of the second lower electrode 151.

[0088] refer to Fig.21 A second dielectric layer 152 is formed on the bottom surface and inner wall of the second lower electrode 151 by a deposition process. The second dielectric layer 152 is also located on the top surface of the isolation layer 144 .

[0089] In this embodiment, the material of the second dielectric layer 152 has a high dielectric constant, and the material type or structure of the second dielectric layer 152 may be the same as or different from that of the first dielectric layer 131 .

[0090] refer to Fig. 22 , filling the second electrode groove 14 a to form a second upper electrode 153 .

[0091] In this embodiment, the second upper electrode 153 is simultaneously located in the grooves of the plurality of second lower electrodes 151 , that is, the second upper electrode 153 simultaneously serves as the upper electrode plates of the plurality of capacitors.

[0092] The second upper electrode 153 , the second dielectric layer 152 and the second lower electrode 151 form a second type of capacitor structure, ie, a concave capacitor structure.

[0093] refer to Fig.23 , forming an isolation structure 16, and connecting the second upper electrode 153 to the first signal terminal 171, and connecting the first upper electrode 132 to the second signal terminal 172. The first signal terminal 171 and the second signal terminal 172 can control the capacitance of the first type of capacitor structure and the second type of capacitor structure connected in series by adjusting the voltage signal, thereby realizing the storage of data information.

[0094] In this embodiment, the semiconductor structure includes a first lower electrode and a second lower electrode stacked in sequence, the first lower electrode is used to form a first type of capacitor structure, the second lower electrode is used to form a second type of capacitor structure, and the first type of capacitor structure is connected in series with the second type of capacitor structure. In this way, while ensuring that the semiconductor structure has a fixed capacitance value, there is no need to etch a channel with a too large aspect ratio when forming any type of capacitor structure, which is beneficial to ensure that the channel structure of each type of capacitor structure meets the preset structural requirements and avoids etching defects; at the same time, since the channel length of each type of capacitor structure can be relatively short, it is beneficial to avoid the capacitor structure from tipping over or collapsing due to its high aspect ratio during the formation process, thereby reducing the process difficulty and ensuring that the semiconductor structure has a higher structural stability; in addition, since the semiconductor structure is formed by connecting different types of capacitor structures in series, the capacitor structure provided in the embodiment of the present invention can have a larger capacitance value than a single type of capacitor structure.

[0095] Another embodiment of the present invention further provides a method for manufacturing a semiconductor structure. Different from the previous embodiment, in this embodiment, after the planarization process, backfilling is performed. Figure 24 to Figure 25 For detailed explanation, Figure 24 to Figure 25 The cross-sectional structure diagram corresponding to each step of the method for manufacturing a semiconductor structure provided by another embodiment of the present invention. For the parts identical or corresponding to the previous embodiment, reference may be made to the corresponding description of the previous embodiment, and no further description will be given below.

[0096] refer to Fig.24 After the planarization process, the top surface of the third dielectric layer 343 is lower than the top surface of the second lower electrode 351 .

[0097] Due to the etching selectivity of the etchant, there is a difference between the etching rate of the second lower electrode 351 and the etching rate of the third dielectric layer 343; at the same time, since the third dielectric layer 343 is usually a dielectric material that is easier to etch and remove, and the second lower electrode 351 is usually a metal material that is more difficult to etch and remove, when etching the second lower electrode film to form a plurality of discrete second lower electrodes 351, the third dielectric layer 343 is usually over-etched, that is, the top surface of the third dielectric layer 343 is lower than the top surface of the second lower electrode 351.

[0098] In this embodiment, in order to prevent the subsequent etching process from damaging the inner wall surface of the second lower electrode 351 exposed by the third dielectric layer 343, the groove in the second lower electrode 351 needs to be backfilled to make the top surface of the third dielectric layer 343 flush with the top surface of the second lower electrode 351.

[0099] It should be noted that the top surface of the third dielectric layer 343 is flush with the top surface of the second lower electrode 351, which is also beneficial to avoid the subsequent deposition process from filling other materials into the groove of the second lower electrode 351, thereby avoiding the need to use multiple etchants to etch different materials to expose the inner wall and bottom surface of the second lower electrode 351, which is beneficial to shortening the process cycle.

[0100] refer to Fig.25 , the groove in the second lower electrode 351 is backfilled.

[0101] In this embodiment, after the backfilling is performed, an etching back process or a planarization process is performed to make the top surface of the third dielectric layer 343 flush with the top surface of the second lower electrode 351 .

[0102] In this embodiment, after the planarization process, the groove of the second lower electrode is backfilled and back-etched to ensure that the top surface of the third dielectric layer is flush with the top surface of the second lower electrode, thereby avoiding damage to the inner wall of the second lower electrode and shortening the subsequent process time for exposing the inner wall and bottom surface of the second lower electrode.

[0103] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, which can be manufactured using the above-mentioned semiconductor structure manufacturing method.

[0104] refer to Fig.23 , the semiconductor structure includes: a substrate 110, the substrate 110 has a conductive structure 111; a first lower electrode 13 and a second lower electrode 151 stacked in sequence, the first lower electrode 13 is located between the second lower electrode 151 and the substrate 110, the first lower electrode 13 is columnar, the second lower electrode 151 is grooved, and the first lower electrode 13 is electrically connected to the conductive structure 111; a first dielectric layer 131 and a first upper electrode 132, the first dielectric layer 131 covers the side wall surface of the first lower electrode 13, and the first upper electrode 132 is located on the side of the first dielectric layer 131 away from the first lower electrode 13; a second dielectric layer 152 and a second upper electrode 153, the second dielectric layer 152 covers the inner wall and bottom surface of the second lower electrode 151, and the second upper electrode 153 is filled in the groove of the second lower electrode 151. In this embodiment, in the direction perpendicular to the surface of the substrate 110, the orthographic projection of the top surface of the first lower electrode 13 is located within the orthographic projection of the second lower electrode 151.

[0105] In this embodiment, the semiconductor structure further includes: a supporting layer, which is located between adjacent first lower electrodes 13 and supports the first lower electrodes 13 .

[0106] Specifically, the support layer includes a first support layer 121 and a second support layer 123 . The first support layer 121 is located between the bottoms of the first lower electrodes 13 , and the second support layer 123 is located between the tops of the first lower electrodes 13 .

[0107] The support layer further includes a third support layer 141 . The third support layer 141 is located between the bottoms of the second lower electrodes 151 . The third support layer 141 is used to support the second lower electrodes 151 .

[0108] In this embodiment, the dimension of the third supporting layer 141 between the bottoms of adjacent second lower electrodes 151 along the surface direction of the substrate 110 is smaller than the dimension of the second supporting layer 123 between the tops of adjacent first lower electrodes 13 along the surface direction of the substrate 110 .

[0109] In this embodiment, the third supporting layer 141 between the bottoms of adjacent second lower electrodes 151 has the same size along the surface direction of the substrate 110, and the second supporting layer 123 between the tops of adjacent first lower electrodes 13 has different sizes along the surface direction of the substrate 110. Specifically, the second supporting layer 123 between the tops of the first lower electrodes 13 with larger sizes along the surface direction of the substrate 110 is in direct contact with the first upper electrode 132 thereunder; the second supporting layer 123 between the tops of the first lower electrodes 13 with smaller sizes along the surface direction of the substrate 110 is in direct contact with the first dielectric layer 131 thereunder.

[0110] In this embodiment, a portion of the second supporting layer 123 and the third supporting layer 141 are an integrated structure.

[0111] In this embodiment, the first dielectric layer 131 covers the first upper electrode 132 , and the first dielectric layer 131 has a via hole (not shown) exposing the first upper electrode 132 ; the support layer has a backfill portion, and the backfill portion fills the via hole.

[0112] In this embodiment, the first upper electrode 132 is located between adjacent first dielectric layers 131 , and a first gap (not marked) is defined in the first upper electrode 132 .

[0113] In this embodiment, the semiconductor structure further includes an isolation layer 147 . The isolation layer 147 is located between adjacent second lower electrodes 151 . The isolation layer 147 has a second gap 145 therein.

[0114] In this embodiment, the semiconductor structure is formed by connecting different types of capacitor structures in series. Compared with a single type of capacitor structure, the capacitor structure provided by the embodiment of the present invention can have a larger capacitance value.

[0115] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a conductive structure therein; A first lower electrode and a second lower electrode are stacked in sequence, wherein the first lower electrode is located between the second lower electrode and the substrate, the first lower electrode is in a columnar shape, the second lower electrode is in a groove shape, and the first lower electrode is electrically connected to the conductive structure; A first dielectric layer and a first upper electrode, wherein the first dielectric layer covers a sidewall surface of the first lower electrode, and the first upper electrode is located on a side of the first dielectric layer away from the first lower electrode; A second dielectric layer and a second upper electrode, wherein the second dielectric layer covers the inner wall and the bottom surface of the second lower electrode, and the second upper electrode is filled in the groove of the second lower electrode; A supporting layer, wherein the supporting layer is located between adjacent first lower electrodes, and includes a first supporting layer located between the bottoms of the first lower electrodes and a second supporting layer located between the tops of the first lower electrodes, wherein the second supporting layers between the tops of the first lower electrodes have different sizes along the surface direction of the substrate, wherein the second supporting layer between the tops of the first lower electrodes having larger sizes along the surface direction of the substrate is in direct contact with the first upper electrode thereunder; and the second supporting layer between the tops of the first lower electrodes having smaller sizes along the surface direction of the substrate is in direct contact with the first dielectric layer thereunder.

2. The semiconductor structure according to claim 1, characterized in that: In a direction perpendicular to the surface of the substrate, an orthographic projection of a top surface of the first lower electrode is located within an orthographic projection of a bottom surface of the second lower electrode.

3. The semiconductor structure according to claim 1, characterized in that: The supporting layer further includes a third supporting layer, the third supporting layer is located between the bottoms of the second lower electrodes, and the third supporting layer is used to support the second lower electrodes.

4. The semiconductor structure according to claim 3, characterized in that: A dimension of the third supporting layer between adjacent bottom portions of the second lower electrodes along the substrate surface direction is smaller than a dimension of the second supporting layer between adjacent top portions of the first lower electrodes along the substrate surface direction.

5. The semiconductor structure according to claim 3, characterized in that: The sizes of the third supporting layer between the bottoms of adjacent second lower electrodes along the surface of the substrate are the same.

6. The semiconductor structure according to claim 3, characterized in that: Part of the second supporting layer and the third supporting layer are an integrated structure.

7. The semiconductor structure according to claim 1, characterized in that: The first dielectric layer covers the first upper electrode, and the first dielectric layer has a via hole exposing the first upper electrode; the supporting layer has a backfilling portion, and the backfilling portion fills the via hole.

8. The semiconductor structure according to claim 1, characterized in that: The first upper electrode is located between adjacent first dielectric layers, and the first upper electrode has a first gap therein.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that: Also includes: An isolation layer is located between adjacent second lower electrodes and has a second gap therein.

10. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate having a conductive structure therein; forming a first lower electrode electrically connected to the conductive structure, wherein the first lower electrode is in a columnar shape; Forming a first dielectric layer and a first upper electrode in sequence on the side wall surface of the first lower electrode, wherein the first dielectric layer is located between the first lower electrode and the first upper electrode; After forming the first upper electrode, forming a second lower electrode on a side of the first lower electrode away from the substrate, wherein the second lower electrode is in a groove shape; forming a second dielectric layer on the inner wall and bottom surface of the second lower electrode, and forming a second upper electrode filling the groove of the second lower electrode; Among them, the step of forming the first lower electrode includes: forming a first dielectric layer on the substrate, the first dielectric layer including a first supporting layer, a first sacrificial layer and a second supporting layer stacked in sequence in a direction perpendicular to the substrate; etching the second supporting layer, the first sacrificial layer and the first supporting layer in sequence to form a first electrode groove exposing the conductive structure; filling the first electrode groove to form the first lower electrode.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: The process steps for forming the first dielectric layer and the first upper electrode include: etching the second supporting layer to form a via; performing a wet etching process through the via to remove the first sacrificial layer; performing a first deposition process through the via to form a first dielectric layer on the side wall surface of the first lower electrode; performing a second deposition process through the via to form a first upper electrode on a side of the first dielectric layer away from the first lower electrode.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: After forming the first upper electrode, the via hole is backfilled to form a backfill portion.

13. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: The process steps for forming the second lower electrode include: forming a second dielectric layer on a side of the first lower electrode away from the substrate; etching the second dielectric layer to form a second electrode groove exposing the first lower electrode, wherein the orthographic projection of the top surface of the first lower electrode is located within the orthographic projection of the bottom surface of the second electrode groove in a direction perpendicular to the surface of the substrate; and performing a third deposition process to form the second lower electrode covering the sidewalls and bottom surface of the second electrode groove.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: The second dielectric layer includes a third supporting layer and a second sacrificial layer stacked in sequence; and the etching of the second dielectric layer includes: etching the second sacrificial layer and the third supporting layer in sequence.

15. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: After forming the second lower electrode, removing the second sacrificial layer between adjacent second lower electrodes; forming an isolation film on the outer wall of the second lower electrode, with a second gap between adjacent isolation films; sealing the top of the second gap to form a sealing layer, the sealing layer, the isolation film and the second gap constitute an isolation layer.

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that: After forming the second lower electrodes and before removing the second sacrificial layer between adjacent second lower electrodes, the method further includes: A third dielectric layer is filled in the second electrode groove forming the second lower electrode.

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