Semiconductor packaging method and substrate used in the semiconductor packaging method

Abstract

The present application provides a semiconductor packaging method and a carrier for the semiconductor packaging method. The semiconductor packaging method comprises: providing a carrier, the carrier comprising a body and a raised portion arranged on the surface of the body, the raised portion dividing the surface of the body into at least two sub-areas; mounting a plurality of chips to be packaged on the sub-areas of the body; each of the sub-areas is mounted with at least one chip; forming an encapsulation layer on the carrier, the encapsulation layer encapsulating the plurality of chips to be packaged and the raised structure, and forming a recessed portion in the area corresponding to the encapsulation layer and the raised portion; peeling off the carrier; performing a slicing process on the packaging structure, so that the packaging structure is broken at the recessed portion to obtain at least two sub-packaging structures; the packaging structure at least comprises the encapsulation layer and the plurality of chips to be packaged.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor packaging method and a carrier used in the semiconductor packaging method. Background Art

[0002] During the chip packaging process, the front side of the chip is first mounted on the carrier board and hot-pressed and plastic-sealed. The carrier board is then peeled off, and then a rewiring structure is formed on the front side of the chip and packaged to obtain a board-level structure. The board-level structure is then divided into multiple sub-board-level structures, each of which includes multiple chips. Finally, each sub-board-level structure is cut to obtain multiple independent chip products.

[0003] Existing solutions generally use lasers to cut board-level structures to obtain multiple sub-board-level structures. However, during the laser cutting process, the laser may injure the operator, and the laser cutting equipment is relatively expensive, and the cutting cost is high. In addition, laser cutting generates heat, and the thermal stress caused by the heat will affect the reliability of the product. Summary of the invention

[0004] Embodiments of the present application provide a semiconductor packaging method and a substrate used in the semiconductor packaging method.

[0005] According to a first aspect of an embodiment of the present application, a semiconductor packaging method is provided. The semiconductor packaging method comprises:

[0006] Providing a carrier, the carrier comprising a body and a protrusion disposed on a surface of the body, wherein the protrusion divides the surface of the body into at least two sub-areas;

[0007] Mounting a plurality of chips to be packaged on the sub-regions of the body; each of the sub-regions is mounted with at least one chip;

[0008] forming an encapsulation layer on the carrier, wherein the encapsulation layer encapsulates the plurality of chips to be packaged and the protruding structure, and a concave portion is formed in the area of ​​the encapsulation layer corresponding to the protruding portion;

[0009] peeling off the carrier plate;

[0010] The packaging structure is sliced ​​to break the packaging structure at the recessed portion to obtain at least two sub-packaging structures, wherein the packaging structure at least includes the encapsulation layer and the plurality of chips to be packaged.

[0011] In one embodiment, the height of the protrusion is greater than or equal to the thickness of the chip; and the slicing of the package structure includes:

[0012] A thinning process is performed on a side of the encapsulation layer away from the recessed portion, so that the thickness of the encapsulation layer after thinning is equal to or less than the depth of the recessed portion.

[0013] In one embodiment, the slicing of the package structure includes:

[0014] Applying a force to the packaging structure to break the packaging structure at the recessed portion;

[0015] Before applying a force to the packaging structure to break the packaging structure at the recessed portion, the semiconductor packaging method further includes:

[0016] A clamp is fixed on the packaging structure, wherein the clamp comprises a clamping plate portion, and the clamping plate portion is at least partially located on two sides of the recessed portion.

[0017] In one embodiment, the clamping plate portion includes a main body portion corresponding to the sub-package structure one by one, and the main body portion is located at the side of the recessed portion; the main body portion is strip-shaped and covers the area of ​​the package structure adjacent to the recessed portion, or the main body portion covers the entire area of ​​the package structure located at the side of the recessed portion;

[0018] The clamping plate portion further comprises an extension portion formed by extending the main body portion and located on the recessed portion, the extension portion is provided with convex structures arranged at intervals, a notch portion is formed between two adjacent convex structures, the convex structures of the two adjacent extension portions are staggered, and the convex structure of one of the extension portions is inserted into the notch portion of the other extension portion;

[0019] When the main body covers the entire area of ​​the packaging structure located on the side of the recessed portion, a hollow portion is provided on the main body, and two hollow portions located on opposite sides of the recessed portion are symmetrically arranged.

[0020] In one embodiment, after the package structure is sliced ​​to break the package structure at the recessed portion to obtain at least two sub-package structures, wherein the package structure at least includes the encapsulation layer and the plurality of chips to be packaged, the semiconductor packaging method further includes:

[0021] The burr structure on the side of the sub-package structure is removed.

[0022] In one embodiment, the thickness of the packaging structure where the chip is located is greater than the thickness of the packaging structure where the recessed portion is located;

[0023] The thickness of the encapsulation layer in the area where the recessed portion is located is in the range of 20 μm to 50 μm; and / or,

[0024] The width of the protrusion is greater than half of the height of the protrusion, and / or the width of the protrusion is less than 5 mm.

[0025] In one embodiment, the protrusion is molded together with the body; and / or,

[0026] The sub-regions are all the same in shape and size.

[0027] According to a second aspect of an embodiment of the present application, a carrier for a semiconductor packaging method is provided, the carrier comprising a main body and a raised portion arranged on the surface of the main body, the raised portion dividing the surface of the main body into at least two sub-areas; the sub-areas are used for mounting chips to be packaged.

[0028] In one embodiment, the width of the protrusion is greater than half of the height of the protrusion, and / or the width of the protrusion is less than 5 mm.

[0029] In one embodiment, the protrusion is molded together with the body; and / or,

[0030] The sub-regions are all the same in shape and size.

[0031] The main technical effects achieved by the embodiments of the present application are:

[0032] The semiconductor packaging method and the carrier used for the semiconductor packaging method provided by the embodiments of the present application, the carrier includes a main body and a raised portion arranged on the surface of the main body, the raised portion can form a recessed portion at the position corresponding to the encapsulation layer and the raised portion, so that the thickness of the area corresponding to the recessed portion of the packaging structure is relatively thin, and the packaging structure is easier to break at the recessed portion, and there is no need to use a laser to cut the packaging structure, which can avoid laser damage to the operator and help improve the operational safety of the packaging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;

[0034] Figure 2 is a top view of a carrier provided by an exemplary embodiment of the present application;

[0035] Figure 3 is a side view of a carrier provided by an exemplary embodiment of the present application from one viewing angle;

[0036] Figure 4 is a side view of a carrier provided by an exemplary embodiment of the present application from another perspective;

[0037] Figure 5 is a cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;

[0038] Figure 6 is a cross-sectional view of a second intermediate structure provided by an exemplary embodiment of the present application;

[0039] Figure 7 is a cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application;

[0040] Figure 8 is a cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application;

[0041] Fig. 9 is a cross-sectional view of a packaging structure provided by an exemplary embodiment of the present application mounted on a carrier;

[0042] Fig.10 is a cross-sectional view of a fifth intermediate structure provided by an exemplary embodiment of the present application;

[0043] Fig.11 is a cross-sectional view of a sub-package structure provided by an exemplary embodiment of the present application;

[0044] Fig.12 is a top view of fixing a clamp to a packaging structure provided by an exemplary embodiment of the present application;

[0045] Fig.13 It is a cross-sectional view of fixing a clamp to a packaging structure provided by an exemplary embodiment of the present application. Specific embodiments

[0046] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0047] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0048] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0049] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0050] The present application embodiment provides a semiconductor packaging method. Figure 1 The semiconductor packaging method includes the following steps 110 to 150.

[0051] In step 110, a carrier is provided, wherein the carrier comprises a body and a protrusion disposed on a surface of the body, wherein the protrusion divides the surface of the body into at least two sub-areas.

[0052] In step 120, a plurality of chips to be packaged are mounted on sub-regions of the body; each sub-region is mounted with at least one chip.

[0053] In step 130, an encapsulation layer is formed on the carrier, wherein the encapsulation layer encapsulates the plurality of chips to be packaged and the protruding structure, and a recessed portion is formed in the area of ​​the encapsulation layer corresponding to the protruding portion.

[0054] In step 140, the carrier is peeled off.

[0055] In step 150, the packaging structure is sliced ​​to break the packaging structure at the recessed portion to obtain at least two sub-packaging structures, wherein the packaging structure at least includes the encapsulation layer and the plurality of chips to be packaged.

[0056] In the semiconductor packaging method provided by the embodiment of the present application, the carrier includes a main body and a protrusion arranged on the surface of the main body. The protrusion can form a recessed portion at the position corresponding to the encapsulation layer and the protrusion, so that the thickness of the area corresponding to the packaging structure and the recessed portion is relatively thin, and the packaging structure is easier to break at the recessed portion. There is no need to use laser to cut the packaging structure, which can avoid laser damage to the operator and help improve the operational safety of the packaging process.

[0057] The following is a detailed introduction to each step of the semiconductor packaging method provided in the embodiment of the present application.

[0058] In step 110, a carrier is provided, wherein the carrier comprises a body and a protrusion disposed on a surface of the body, wherein the protrusion divides the surface of the body into at least two sub-areas.

[0059] See also Figures 2 to 4 , the carrier 10 includes a protrusion 11 and a body 12, and the protrusion 11 is arranged on the surface of the body 12. The surface of the body 12 may be provided with a plurality of protrusions 11, some of which may extend along a first direction, and other protrusions 11 may extend along a second direction, and the first direction intersects with the second direction, so that the plurality of protrusions 11 divide the surface of the body 12 into at least two sub-areas 101. In some embodiments, the first direction is perpendicular to the second direction, so that the shape of the sub-area 101 can be relatively regular. In the illustrated embodiment, the surface of the body 12 is divided into four sub-areas 101 by the protrusions 11. In other embodiments, the number of sub-areas 101 on the surface of the body 12 may be different from four.

[0060] In one embodiment, the shapes and sizes of the sub-regions 101 included on the surface of the body 12 are the same. The packaging structure is formed on the carrier 10, and a plurality of sub-packaging structures are obtained after the packaging structure is sliced, and the shapes and sizes of the sub-packaging structures are the same as the shapes and sizes of the corresponding sub-regions 101. By setting the shapes and sizes of the sub-regions 101 to be the same, the shapes and sizes of the obtained sub-packaging structures can be the same. When the sub-packaging structure is subsequently transported, the sub-packaging structure needs to be put into a box. The shapes and sizes of the sub-packaging structures are the same, so they can be put into boxes of the same size, and there is no need to select boxes of corresponding sizes according to the sizes of the sub-packaging structures, and the operation is relatively simple.

[0061] In one embodiment, the sub-region 101 of the body 12 includes a mounting area 1011 and a blank area 1012. The areas in the sub-region 101 other than the mounting area 1011 are all blank areas 1012. The shape of the mounting area 1011 is designed according to the layout of the chip 20 to be packaged on the surface of the body 12, and the shape of the mounting area 1011 may include a circle, a rectangle or other shapes. The blank area 1012 includes the edge area of ​​the sub-region 101 and the area between adjacent mounting areas 1011. Figure 2 In the illustrated embodiment, each sub-region 101 includes a plurality of mounting areas 1011. In other embodiments, the body 12 may also include one mounting area 1011.

[0062] In the illustrated embodiment, the body 12 is rectangular in shape, and in other embodiments, the body 12 may be circular or other shapes. The material of the carrier 10 may be an iron-nickel fixed expansion alloy, or the material of the carrier 10 may also be stainless steel, polymer, etc.

[0063] In one embodiment, the body 12 and the protrusion 11 are integrally formed. In this way, when the encapsulation layer and the chip are subsequently peeled off from the carrier 10, the protrusion 11 will not be peeled off from the body 12 together with the encapsulation layer. In other embodiments, the protrusion 11 may also be provided separately from the body 12, for example, a bracket may be fixed on the surface of the body 12, and the bracket includes a plurality of protrusions, and after the encapsulation layer and the chip are peeled off from the carrier, the bracket will not be separated from the carrier.

[0064] In step 120, a plurality of chips to be packaged are mounted on sub-regions of the body; each sub-region is mounted with at least one chip.

[0065] Through step 120, the following can be obtained: Figure 5 The first intermediate structure shown in FIG. 1 can mount a chip 20 to be packaged on each mounting area 1011 of the sub-area.

[0066] In one embodiment, after the chip 20 to be packaged is mounted on the body 12, the front side of the chip to be packaged can face the body 12. A solder pad is provided on the front side of the chip to be packaged, and the solder pad can lead out the circuit inside the chip. The solder pad of the chip to be packaged is composed of a conductive electrode that leads the internal circuit of the chip to the surface of the chip. A plurality of solder pads can be provided on the front side of the chip to be packaged. In other embodiments, a process for processing the back side of the chip is required, and after the chip 20 to be packaged is mounted on the body 12, the back side of the chip to be packaged can face the body 12.

[0067] In one embodiment, the chip 20 to be packaged can be obtained by cutting a silicon wafer. The silicon wafer has an active surface, and the active surface of the silicon wafer is provided with a pad. The silicon wafer can be cut by mechanical cutting or laser cutting. Optionally, before cutting the silicon wafer, a grinding device can be used to grind the back side of the silicon wafer opposite to the active surface so that the thickness of the silicon wafer is a specified thickness.

[0068] In one embodiment, the chip 20 to be packaged can be mounted on the body 12 through an adhesive layer, and the adhesive layer can be made of an easily peelable material so that the chip 20 to be packaged can be peeled off from the carrier 10 later. For example, the adhesive layer can be made of a thermal separation material that can lose its viscosity by heating.

[0069] In step 130, an encapsulation layer is formed on the carrier, wherein the encapsulation layer encapsulates the plurality of chips to be packaged and the protruding structure, and a recessed portion is formed in the area of ​​the encapsulation layer corresponding to the protruding portion.

[0070] Through step 130, the following can be obtained: Figure 6 The second intermediate structure is shown.

[0071] See also Figure 6The encapsulation layer 31 is formed on the chip 20 to be packaged and the exposed carrier 10, encapsulating the chip 20 to be packaged and the protrusion 11 to reconstruct a flat structure, so that after the carrier 10 is peeled off, rewiring and packaging can continue on the reconstructed flat structure. The encapsulation layer 31 encapsulates the protrusion 11, so that a concave portion 311 is formed at the position corresponding to the encapsulation layer 31 and the protrusion 11.

[0072] In one embodiment, before forming the encapsulation layer 31, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the chip 20 and the carrier 10, so that the encapsulation layer 31 and the chip 20 to be packaged and the carrier 10 can be more firmly bonded without delamination or cracking.

[0073] In one embodiment, the encapsulation layer 31 may be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding of an epoxy resin compound.

[0074] In step 140, the carrier is peeled off.

[0075] Through step 140, the following can be obtained: Figure 7 The third intermediate structure is shown.

[0076] See also Figure 7 After the third intermediate structure 30 is peeled off from the carrier 10 , a recessed portion 311 is formed in the area of ​​the encapsulation layer 31 corresponding to the raised portion 11 , and the depth of the recessed portion 311 is the same as the height of the raised portion 11 .

[0077] In one embodiment, the carrier 10 can be directly mechanically peeled off from the third intermediate structure 30. In another embodiment, the chip 20 to be packaged is bonded to the carrier 10 via an adhesive layer, and when the adhesive layer is made of a thermal separation material, the adhesive layer can be heated to reduce its viscosity after being heated, thereby peeling off the carrier 10.

[0078] After the chip 20 to be packaged is mounted on the body 12, when the front side of the chip to be packaged faces the body 12, the carrier 10 is peeled off to expose the front side of each chip 20 to be packaged and the recessed portion 311. After the chip 20 to be packaged is mounted on the body 12, when the back side of the chip to be packaged faces the body 12, the carrier 10 is peeled off to expose the back side of each chip 20 to be packaged and the recessed portion 311.

[0079] In one embodiment, after the carrier 10 is peeled off, the front surface and the recessed portion 311 of each chip 20 to be packaged are exposed, and after step 140, the semiconductor packaging method further includes the following steps:

[0080] A rewiring layer is formed on the front side of the chip, and the rewiring layer leads out the bonding pads on the front side of the chip.

[0081] Through this step, we can obtain Figure 8 The fourth intermediate structure shown includes a carrier 10 and a packaging structure located on the carrier 10, and the packaging structure includes an encapsulation layer 31, a chip 20 to be packaged, and a rewiring layer. The rewiring layer includes a conductive structure 41 formed on the front side of the chip. The thickness of the packaging structure where the chip is located is greater than the thickness of the packaging structure where the recessed portion is located;

[0082] In some embodiments, the step of forming a rewiring layer on the front side of the chip may include the following process:

[0083] First, a seed layer is formed on the front side of the chip, wherein the seed layer covers the surface of the third intermediate structure.

[0084] Before forming a seed layer on the front side of the chip, the third intermediate structure may be mounted on the carrier 51 so that the front side of the chip 20 faces away from the carrier 10. The carrier 10 supports the third intermediate structure to facilitate forming a seed layer on the front side of the chip.

[0085] In one embodiment, the seed layer may be formed by a sputtering process.

[0086] In one embodiment, the material of the seed layer includes one or more of copper, nickel, molybdenum, aluminum, titanium, etc. Copper, nickel, molybdenum, aluminum, and titanium have low resistivity, which can make the seed layer have good conductivity and low resistance, which is more conducive to increasing the current size and current density in the subsequent electroplating process. In other embodiments, the material of the seed layer can also be other materials with good conductivity.

[0087] Subsequently, a metal layer is formed on a side of the seed layer away from the third intermediate structure by using an electroplating process, so as to obtain a conductive layer including the seed layer and the metal layer.

[0088] In one embodiment, the material of the metal layer can be the same as or different from that of the seed layer. The metal layer can cover the seed layer, or the metal layer can be a patterned film layer.

[0089] Then, the conductive layer is patterned to form a conductive structure for leading out the pad.

[0090] During the process of patterning the conductive layer, the conductive structure in the recessed portion 311 is etched away, so as to smoothly slice the package structure.

[0091] In one embodiment, the width of the protrusion 11 on the carrier plate is greater than half of the height of the protrusion 11, and / or the width of the protrusion is less than 5 mm. The width of the protrusion 11 refers to the dimension of the protrusion 11 in a direction perpendicular to the extension direction of the protrusion 11. By setting the width of the protrusion 11 to be greater than half of the height of the protrusion 11, the width of the recessed portion 311 formed is greater than half of the depth of the recessed portion 311. When forming the seed layer, it can be avoided that the seed layer breaks at the recessed portion 311, thereby avoiding the seed layer from breaking at the recessed portion 311 and affecting the formation of the metal layer; by setting the width of the protrusion 11 to be less than 5 mm, it can be avoided that the setting of the protrusion 11 occupies a large area of ​​the surface of the main body 12, thereby making the effective utilization rate of the surface of the main body 12 low.

[0092] In some embodiments, the thickness of the encapsulation layer 31 is greater than the height of the protrusion 11. Thus, after the encapsulation layer 31 is peeled off from the carrier 10, the recessed portion 311 formed on the encapsulation layer 31 will not penetrate the encapsulation layer 31, thereby preventing leakage of the electroplating solution during the electroplating process.

[0093] In step 150, the packaging structure is sliced ​​to break the packaging structure at the recessed portion to obtain at least two sub-packaging structures, wherein the packaging structure at least includes the encapsulation layer and the plurality of chips to be packaged.

[0094] In one embodiment, the step 150 of slicing the package structure includes: thinning the side of the encapsulation layer away from the recessed portion, so that the thickness of the encapsulation layer after thinning is equal to or less than the depth of the recessed portion.

[0095] In some embodiments, see Fig. 9 Before thinning the side of the encapsulation layer away from the recessed portion, the package structure can be mounted on a carrier 52, with the conductive structure 41 close to the carrier 52. The carrier 52 supports the package structure, making it easier to thin the package structure.

[0096] Among the multiple sub-package structures included in the package structure, adjacent sub-package structures are connected together by the area of ​​the encapsulation layer 31 corresponding to the recessed portion 311 in the longitudinal direction. By thinning the side of the encapsulation layer 31 away from the recessed portion 311, the thickness of the package structure becomes thinner. When the thickness of the package structure after thinning is equal to the depth of the recessed portion 311, the portion of the encapsulation layer 31 corresponding to the recessed portion 311 in the longitudinal direction is removed, and the adjacent sub-package structures are separated to obtain the following. Fig.10 The fifth intermediate structure is shown in FIG. 5 . Then, the carrier plate 52 is peeled off to obtain Fig.11The sub-package structure 32 is shown. The number of the sub-package structures 32 is the same as the number of the sub-regions 101 of the body 12. In some embodiments, after the portion of the encapsulation layer 31 corresponding to the recessed portion 311 is removed, the encapsulation layer 31 may be further thinned to make the thickness of the sub-package structure 32 thinner.

[0097] In some embodiments, the encapsulation structure may be thinned by a grinding process.

[0098] In some embodiments, the thickness of the encapsulation layer 31 in the area where the recessed portion 311 is located ranges from 20 μm to 50 μm. This arrangement can prevent the thickness of the encapsulation layer 31 in the area where the recessed portion 311 is located from being too large, resulting in a long time spent on the thinning process, which is not conducive to improving the semiconductor packaging efficiency, and can also prevent the thickness of the encapsulation layer 31 in the area where the recessed portion 311 is located from being too small, resulting in the encapsulation layer 31 being broken at the recessed portion 311 when the encapsulation layer 31 is peeled off from the carrier 10. In some embodiments, the thickness of the encapsulation layer 31 in the area corresponding to the recessed portion 311 is 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc.

[0099] In one embodiment, the height of the protrusion 11 is greater than or equal to the thickness of the chip 20 to be packaged. The height of the protrusion 11 refers to the distance from the surface of the protrusion 11 away from the mounting area 1011 to the mounting area 1011, and the thickness of the chip 20 to be packaged refers to the distance from the surface of the chip 20 to be packaged away from the mounting area 1011 to the mounting area 1011. In this way, when the packaging structure is thinned, the packaging structure is separated at the recessed portion 311 when the back of the chip 20 is not exposed or just exposed, which can avoid damage to the back of the chip 20 during the thinning process.

[0100] In another embodiment, the step 150 of slicing the package structure includes: applying a force to the package structure to break the package structure at the recessed portion.

[0101] Before applying force to the package structure, the package structure is first peeled off from the carrier 52 .

[0102] Since the thickness of the area corresponding to the encapsulation layer 31 and the recessed portion 311 is relatively small, an external force can be applied to the packaging structure to break the area corresponding to the encapsulation structure 31 and the recessed portion 311, so that the packaging structure is broken at the recessed portion 311. After the packaging structure is broken at the recessed portion 311, the following can be obtained: Fig.11 A sub-package structure 32 is shown.

[0103] In one embodiment, before applying a force to the packaging structure to break the packaging structure at the recessed portion, the semiconductor packaging method further includes:

[0104] A clamp is fixed on the packaging structure, wherein the clamp includes a clamping plate portion, and the clamping plate portion is at least partially located on both sides of the recessed portion. Fig.12 and Fig.13 The clamping plate portion 60 is located on the packaging structure. When a force is applied to the packaging structure, the clamping plate portion 60 bears the force, thereby preventing cracks from extending to the sub-packaging structure and damaging the chip 20 to be packaged.

[0105] In one embodiment, the clamping plate portion 60 includes a main body portion 61 corresponding to the sub-packaging structure one by one, and the main body portion 61 is located at a side of the recessed portion 311 . Fig.12 and Fig.13 In the illustrated embodiment, the main body 61 is in a strip shape, covering the area of ​​the packaging structure adjacent to the recessed portion 311. In other embodiments, the main body 61 may cover the entire area of ​​the packaging structure located on the side of the recessed portion 311. When the main body 61 covers the entire area of ​​the packaging structure located on the side of the recessed portion 311, a force is applied to the packaging structure, and the force is distributed relatively evenly on the packaging structure, which can avoid the situation where the corners of the packaging structure close to the recessed portion are subjected to a large force and the film layer cracks.

[0106] In some embodiments, the clamping plate portion 60 further includes an extension portion formed by extending the main body portion 61 and located on the recessed portion, the extension portion is provided with convex structures arranged at intervals, a notch portion is formed between two adjacent convex structures, the convex structures of the two adjacent extension portions are staggered, and the convex structure of one of the extension portions is inserted into the notch portion of the other extension portion. In this way, when a force is applied to the packaging structure, the force is concentrated on the end of the convex structure, and the cracks generated extend along the line between the adjacent convex structures, which is more helpful to prevent the cracks from reaching the sub-packaging structure and damaging the chip 20 to be packaged.

[0107] In some embodiments, when the main body covers the entire area of ​​the packaging structure located on the side of the recessed portion, a hollow portion is provided on the main body, and two hollow portions located on opposite sides of the recessed portion are symmetrically arranged. In this way, the applied force can be distributed more evenly in various areas of the packaging structure, and the weight of the clamping plate can be reduced, which is convenient for operators to operate.

[0108] In some embodiments, the clamping plate portion 61 is located on a side of the encapsulation layer 31 away from the chip 20 to be packaged. In this way, the clamping plate portion 61 will not contact the conductive structure 41 of the redistribution layer, and will not damage the conductive structure 41.

[0109] In some embodiments, after the package structure is broken at the recessed portion, a burr structure will be generated at the break; when the package structure is thinned, some burr structures will also be generated on the side of the sub-package structure. After the package structure is sliced ​​to break the package structure at the recessed portion to obtain at least two sub-package structures, the package structure at least includes the encapsulation layer and the multiple chips to be packaged, the semiconductor packaging method further includes: removing the burr structure on the side of the sub-package structure.

[0110] By removing the burr structure on the side of the sub-package structure 32, it is possible to prevent the burr structure from falling off during transportation and moving to the surface of the chip 20, thereby affecting the reliability of the chip 20; it is also possible to prevent the burr structure from scratching operators; it is also possible to prevent the burr structure from preventing the sub-package structure from being smoothly placed in a box for storing the sub-package structure for transportation.

[0111] In some embodiments, a deburring device may be used to remove the burr structure of the sub-package structure 32. Alternatively, a grinding sheet may be used to grind the side of the sub-package structure 32 to remove the burr structure.

[0112] In one embodiment, the thickness of the region corresponding to the package structure and the recessed portion 311 ranges from 20 μm to 50 μm. This arrangement can prevent the package structure from being broken at the recessed portion 311 due to the encapsulation layer 31 being too thick, or the encapsulation layer 31 being broken at the recessed portion 311 due to the encapsulation layer 31 being too thin when peeling the encapsulation layer from the carrier 10.

[0113] In some embodiments, after step 150, the semiconductor packaging method further includes: cutting the sub-package structure to obtain a plurality of packaged chips.

[0114] The present application also provides a substrate for use in a semiconductor packaging method. Figures 2 to 4 The carrier 10 includes a body 12 and a protrusion 11 disposed on the surface of the body 12. The protrusion 11 divides the surface of the body 12 into at least two sub-areas 101. The sub-areas 101 are used for mounting chips to be packaged.

[0115] In one embodiment, the width of the protrusion 11 is greater than half of the height of the protrusion 11 , and / or the width of the protrusion 11 is less than 5 mm.

[0116] In one embodiment, the protrusion 11 is formed together with the body 12 .

[0117] In one embodiment, the sub-regions 101 are all the same in shape and size.

[0118] The carrier for the semiconductor packaging method provided in the embodiment of the present application belongs to the same inventive concept as the embodiment of the semiconductor packaging method described above, and the description of relevant details and beneficial effects can be referred to each other, which will not be repeated here.

[0119] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0120] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims.

[0121] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor packaging method, characterized in that: include: Providing a carrier, the carrier comprising a body and a protrusion disposed on a surface of the body, wherein the protrusion divides the surface of the body into at least two sub-areas; Mounting a plurality of chips to be packaged on the sub-regions of the body; each of the sub-regions is mounted with at least one chip; forming an encapsulation layer on the carrier, wherein the encapsulation layer encapsulates the plurality of chips to be packaged and the protrusions, and a concave portion is formed in an area corresponding to the encapsulation layer and the protrusions; peeling off the carrier plate; Slicing the package structure so that the package structure is broken at the recessed portion to obtain at least two sub-package structures; The packaging structure at least includes the encapsulation layer and the plurality of chips to be packaged; The slicing process of the package structure includes: fixing a clamp on the package structure, the clamp including a clamping plate portion, and the clamping plate portion is at least partially located on two sides of the recessed portion; A force is applied to the packaging structure to break the packaging structure at the recessed portion; the clamping plate portion includes a main body portion corresponding to the sub-packaging structure one by one and an extension portion formed by extending from the main body portion and located on the recessed portion; the main body portion is located on the side of the recessed portion; the extension portion is provided with convex structures arranged at intervals, a notch portion is formed between two adjacent convex structures, the convex structures of two adjacent extension portions are staggered, and the convex structure of one of the extension portions is inserted into the notch portion of the other extension portion.

2. The semiconductor packaging method according to claim 1, wherein: The height of the protrusion is greater than or equal to the thickness of the chip; and the slicing of the package structure comprises: A thinning process is performed on a side of the encapsulation layer away from the recessed portion, so that the thickness of the encapsulation layer after thinning is equal to or less than the depth of the recessed portion.

3. The semiconductor packaging method according to claim 1, wherein: The main body is in the shape of a strip, covering the area adjacent to the packaging structure and the recessed portion, or the main body covers the entire area of ​​the packaging structure located on the side of the recessed portion; when the main body covers the entire area of ​​the packaging structure located on the side of the recessed portion, a hollow portion is provided on the main body, and two hollow portions located on opposite sides of the recessed portion are symmetrically arranged.

4. The semiconductor packaging method according to claim 1, wherein: After the packaging structure is sliced ​​to break the packaging structure at the recessed portion to obtain at least two packaging structures, wherein the packaging structure at least includes the encapsulation layer and the plurality of chips to be packaged, the semiconductor packaging method further includes: The burr structure on the side of the sub-package structure is removed.

5. The semiconductor packaging method according to claim 1, wherein: The thickness of the packaging structure where the chip is located is greater than the thickness of the packaging structure where the recessed portion is located; The thickness of the encapsulation layer in the area where the recessed portion is located is in the range of 20 μm to 50 μm; and / or, The width of the protrusion is greater than half of the height of the protrusion, and / or the width of the protrusion is less than 5 mm.

6. The semiconductor packaging method according to claim 1, wherein: The protrusion is formed together with the body; and / or, The sub-regions are all the same in shape and size.

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