Offset voltage correction circuit and offset voltage correction method

Abstract

The embodiment of the present invention provides an offset voltage correction circuit and an offset voltage correction method, wherein the offset voltage correction circuit comprises: a data acquisition module, which is used to receive a data signal and a reference signal, and obtain a data indication signal according to a comparison result between the reference signal and the offset data signal, wherein the offset data signal is a data signal after the offset signal is superimposed; a trimming enable module, which is used to receive a data signal, a reference signal, a data indication signal and an enable signal; if the enable signal is at a high level, a theoretical indication signal is obtained according to a comparison result between the data signal and the reference signal, and an enable identification signal is generated based on a comparison result between the theoretical indication signal and the data indication signal; an offset correction module, which is used to offset the offset signal based on the enable identification signal; and the accuracy of signal transmission is ensured by offsetting the input offset voltage at the input stage of an operational amplifier.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor circuit design, and in particular to an offset voltage correction circuit and an offset voltage correction method. Background Art

[0002] In the process of signal transmission, various operational amplifiers are widely used in memory. The operational amplifier is a basic analog circuit functional module and is widely used. However, the input stage of the operational amplifier will introduce offset voltage.

[0003] In the process of converting the input analog signal into a digital signal through an operational amplifier, the analog signal may be misconverted due to the input offset voltage of the operational amplifier. This process seriously affects the accuracy of signal transmission and thus seriously affects the use of the memory. Summary of the invention

[0004] The embodiments of the present invention provide an offset voltage correction circuit and an offset voltage correction method, which offset the input offset voltage at the input stage of an operational amplifier, thereby ensuring the accuracy of signal transmission.

[0005] To solve the above technical problems, an embodiment of the present invention provides an offset voltage correction circuit, comprising: a data acquisition module, used to receive a data signal and a reference signal, and obtain a data indication signal according to a comparison result between the reference signal and the offset data signal, wherein the offset data signal is a data signal after the offset signal is superimposed; a trimming enable module, used to receive a data signal, a reference signal, a data indication signal and an enable signal; if the enable signal is at a high level, a theoretical indication signal is obtained according to a comparison result between the data signal and the reference signal, and an enable identification signal is generated based on a comparison result between the theoretical indication signal and the data indication signal; and an offset correction module, used to offset the offset signal based on the enable identification signal.

[0006] Compared with the prior art, the adjustment enable module is turned on by an enable signal, the adjustment enable module generates an enable identification signal based on the comparison result of the theoretical indication signal and the data indication signal, and the offset correction module offsets the offset signal generated in the data acquisition module based on the enable identification signal, thereby ensuring that the data indication signal is consistent with the theoretical indication signal, thereby avoiding the error of the acquired data indication signal caused by the offset signal.

[0007] In addition, the data acquisition module includes: a data receiving unit, having a first input end and a second input end, the first input end is used to receive a data signal, and the second input end is used to receive a reference signal; a data comparison unit, the input end of which is connected to the output end of the data receiving unit, and is used to compare the reference signal and the data signal after the offset signal is superimposed, and obtain a data indication signal.

[0008] In addition, the data receiving unit at least includes a receiving differential amplifier circuit for amplifying the received data signal and the reference signal. The data signal and the reference signal are received by the differential amplifier circuit, so that the application range of the offset voltage correction circuit is wide.

[0009] In addition, the receiving differential amplifier circuit includes: a first differential MOS transistor and a second differential MOS transistor; the gate of the first differential MOS transistor is used to receive a data signal, and the source of the first differential MOS transistor is used to connect to a first load; the gate of the second differential MOS transistor is used to receive a reference signal, and the source of the second differential MOS transistor is used to connect to a second load; the drain of the first differential MOS transistor and the drain of the second differential MOS transistor are connected to the same current source, so that the first differential MOS transistor and the second differential MOS transistor form a differential pair.

[0010] In addition, the first load and the second load use the same load circuit.

[0011] In addition, the data comparison unit includes a comparator.

[0012] In addition, the adjustment enable module includes: a receiving unit, which is used to receive a data signal, a reference signal, a data indication signal and an enable signal; a judgment unit, which is used to judge whether the enable signal is at a high level, and when the enable signal is at a high level, turning on the first comparison unit and the second comparison unit; the first comparison unit, which is used to compare the data signal and the reference signal, and obtain the theoretical indication signal based on the comparison result of the data signal and the reference signal; the second comparison unit, which is used to compare the theoretical indication signal and the data indication signal, and generate an enable identification signal based on the comparison result of the theoretical indication signal and the data indication signal.

[0013] In addition, the offset correction module includes: a control unit for receiving an enable identification signal and generating a corresponding control signal based on the enable identification signal; and a correction unit for changing the conduction state of the internal transistor array based on the control signal to offset the offset signal.

[0014] In addition, the correction unit includes: a correction MOS tube array connected in parallel with the second differential MOS tube; the correction MOS tube array includes: correction MOS tubes of N branches in parallel; the width-to-length ratios of the correction MOS tubes of the N branches increase exponentially according to a 2 relationship, and the sum of the equivalent width-to-length ratios of the MOS tubes of the N branches is less than the second differential MOS tube; N is a natural number greater than or equal to 1. The equivalent width-to-length ratio of the MOS tube for receiving the reference signal is changed by the parallel correction MOS tube array, so that an adjustment signal is applied to the reference signal, thereby offsetting the error caused by the offset signal.

[0015] In addition, the correction MOS tube array further includes: a switch MOS tube connected in series with the correction MOS tube on each branch; the drain of the correction MOS tube is connected to the drain of the second differential MOS tube, the source of the correction MOS tube is connected to the drain of the switch MOS tube, and the source of the switch MOS tube is connected to the source of the second differential MOS tube; the switch MOS tube is used to determine whether to conduct the branch according to the control signal. An embodiment of the present invention provides a specific working mode of the correction MOS tube array.

[0016] An embodiment of the present invention also provides an offset voltage correction method, which is applied to a memory, and includes: receiving a data signal and a reference signal; obtaining a data indication signal based on a comparison result between the reference signal and the offset data signal, wherein the offset data signal is a data signal superimposed with the offset signal; obtaining an enable signal, and when the enable signal is at a high level, obtaining a theoretical indication signal based on a comparison result between the data signal and the reference signal; generating an enable identification signal based on a comparison result between the data indication signal and the theoretical indication signal; and offsetting the offset signal based on the enable identification signal.

[0017] In addition, based on the enable identification signal, the offset signal is offset, including: judging the state of the enable identification signal; if the enable identification signal is at a high level, generating a corresponding control signal according to the enable identification signal; if the enable identification signal is at a low level, not generating a control signal; and adjusting the offset correction module according to the control signal to offset the offset signal.

[0018] In addition, according to the control signal, the offset correction module is adjusted to offset the offset signal, including: based on the control signal, obtaining the target on-off state of each MOS tube in the correction MOS tube array; obtaining the actual on-off state of each MOS tube in the correction MOS tube array; based on the target on-off state, adjusting the actual on-off state.

[0019] Compared with the prior art, the offset voltage correction method is started by an enable signal, an enable identification signal is generated based on the comparison result of the theoretical indication signal and the data indication signal, and the offset signal generated is offset based on the enable identification signal, thereby ensuring that the data indication signal is consistent with the theoretical indication signal, thereby avoiding the error of the acquired data indication signal caused by the offset signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily described by pictures in the corresponding drawings. Unless otherwise stated, the pictures in the drawings are not limited to scale.

[0021] Figure 1 A schematic diagram of a simulated structure of an offset voltage correction circuit provided by a first embodiment of the present invention;

[0022] Figure 2A schematic diagram of the specific structure of the data acquisition module provided in the first embodiment of the present invention;

[0023] Figure 3 A schematic diagram of the specific structure of a data receiving unit provided in the first embodiment of the present invention;

[0024] Figure 4 A schematic diagram of the structure of a correction MOS tube array provided in the first embodiment of the present invention;

[0025] Figure 5 A schematic diagram of the structure of the correction sequence provided by the first embodiment of the present invention;

[0026] Figure 6 A schematic flow chart of an offset voltage correction method provided in accordance with a second embodiment of the present invention. DETAILED DESCRIPTION

[0027] At present, in the process of converting the input analog signal into a digital signal through an operational amplifier, the analog signal may be misconverted due to the input offset voltage of the operational amplifier, which seriously affects the accuracy of signal transmission and thus seriously affects the use of the memory.

[0028] To solve the above problems, a first embodiment of the present invention provides an offset voltage correction circuit, comprising: a data acquisition module, used to receive a data signal and a reference signal, and obtain a data indication signal according to a comparison result between the reference signal and the offset data signal, wherein the offset data signal is a data signal after the offset signal is superimposed; a trimming enable module, used to receive a data signal, a reference signal, a data indication signal and an enable signal; if the enable signal is at a high level, a theoretical indication signal is obtained according to a comparison result between the data signal and the reference signal, and an enable identification signal is generated based on a comparison result between the theoretical indication signal and the data indication signal; and an offset correction module, used to offset the offset signal based on the enable identification signal.

[0029] To make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with each other and quoted from each other without contradiction.

[0030] Figure 1 The analog structure diagram corresponding to the offset voltage correction circuit provided in this embodiment is shown below in combination with Figure 1 The offset voltage correction circuit provided in this embodiment is described in detail.

[0031] refer to Figure 1 The offset voltage correction circuit 100 includes: a data acquisition module 101, a trimming enabling module 102 and an offset correction module 103.

[0032] The data acquisition module 101 is used to receive a data signal and a reference signal, and acquire a data indication signal according to a comparison result between the reference signal and the misaligned data signal, wherein the misaligned data signal is a data signal with the misaligned signal superimposed thereon.

[0033] The adjustment enable module 102 is used to receive a data signal, a reference signal, a data indication signal and an enable signal; if the enable signal is at a high level, a theoretical indication signal is obtained according to the comparison result of the data signal and the reference signal, and an enable identification signal is generated based on the comparison result of the theoretical indication signal and the data indication signal.

[0034] The offset correction module 103 is used to offset the offset signal generated in the data acquisition module 101 based on the enable identification signal.

[0035] Specifically, the data acquisition module 101 includes a data receiving unit 111 and a data comparing unit 121 .

[0036] The data receiving unit 111 has a first input terminal and a second input terminal. The first input terminal is used to receive a data signal, and the second input terminal is used to receive a reference signal.

[0037] The data comparison unit 121 has an input end connected to the output end of the data receiving unit 111 and is used to compare the reference signal with the data signal after the detuning signal is superimposed, so as to obtain a data indication signal.

[0038] Specifically, refer to Figure 2 , the data receiving unit 111 is an amplifier, and the data receiving unit 121 is a comparator; the first input end of the data receiving unit 111 is used to receive a data signal, that is, the positive input end is used to receive a data signal, the data signal is a DQ signal, and the DQ signal is a continuous analog signal; the second input end of the data receiving unit 121 is used to receive a reference signal, that is, the negative input end is used to receive a reference signal, the reference signal is a VREFDQ signal, and the VREFDQ signal is a continuous analog signal. The data receiving unit 111 amplifies the received DQ signal and VREFDQ signal and inputs them into the data comparison unit 121, and the data receiving unit 121 compares the received signals to obtain a data indication signal.

[0039] Specifically, if the DQ signal is smaller than the VREFDQ signal, the data indication signal obtained by the data comparison unit 121 is low, that is, the DQ_int signal is low; if the DQ signal is greater than the VREFDQ signal, the data indication signal obtained by the data comparison unit 121 is high, that is, the DQ_int signal is high.

[0040] In the process of the data receiving unit 111 receiving the data signal and the reference signal, an offset signal will be introduced and superimposed on the data signal. The data signal after the offset signal is superimposed will cause the result of the data signal to be too large or too small, causing the data signal that was originally larger than the reference signal to become smaller, or the data signal that was originally smaller than the reference signal to become larger, thereby causing the acquired data indication signal to be wrong.

[0041] It should be noted that the above-mentioned use of the data receiving unit 111 as an amplifier and the data comparing unit 121 as a comparator is an implementation method of the data receiving unit 111 and the data comparing unit 121 provided in this embodiment, and does not constitute a limitation on this embodiment.

[0042] In this embodiment, the data receiving unit 111 at least includes a receiving differential amplifier circuit for amplifying the received data signal and the reference signal. The data signal and the reference signal are received by the differential amplifier circuit, so that the offset voltage correction circuit has a wide range of applications.

[0043] refer to Figure 3 The receiving differential amplifier circuit includes a first differential MOS transistor 305 and a second differential MOS transistor 304. The gate of the first differential MOS transistor 305 is used to receive a data signal, and the source of the first differential MOS transistor 305 is used to connect to a first load 302. The gate of the second differential MOS transistor 304 is used to receive a reference signal, and the source of the second differential MOS transistor is used to connect to a second load 301. The drain of the first differential MOS transistor 305 and the drain of the second differential MOS transistor 304 are connected to the same current source 303, so that the first differential MOS transistor 305 and the second differential MOS transistor 304 form a differential pair.

[0044] In one example, the first load 302 and the second load 301 may use the same load circuit.

[0045] The second differential MOS transistor 304 is connected in parallel with a correction MOS transistor correction circuit, which includes a correction switch MOS transistor 306 and a correction MOS transistor 307. The width-to-length ratio of the correction MOS transistor 307 is smaller than that of the second differential MOS transistor 304, and is used to change the equivalent width-to-length ratio of the second differential MOS transistor 304, thereby changing the amplification effect on the reference signal to offset the offset signal.

[0046] Continue to refer Figure 1The adjustment enabling module 102 includes: a receiving unit 112 , a judging unit 122 , a first comparing unit 132 and a second comparing unit 142 .

[0047] The receiving unit 112 is used to receive a data signal, a reference signal, a data indication signal and an enable signal.

[0048] The enable signal is generated based on the ZQCL (ZQ Calibration Long) command. The ZQCL command is an internal memory command used for system power-on initialization and device reset in ZQ calibration. That is, the offset voltage correction circuit in this embodiment works based on the internal command and has a stable working environment and safety.

[0049] The judging unit 122 is used to judge whether the enable signal is at a high level, and when the enable signal is at a high level, the first comparing unit 132 and the second comparing unit 142 are turned on.

[0050] That is, the trimming enable module 102 works based on the enable signal. When the enable signal is at a high level, the first comparison unit 132 and the second comparison unit 142 are turned on, and the trimming enable module 102 starts working; when the enable signal is at a low level, the first comparison unit 132 and the second comparison unit 142 are turned off, and the trimming enable module 102 stops working.

[0051] The first comparing unit 132 is used to compare the data signal with the reference signal, and obtain a theoretical indication signal based on the comparison result of the data signal and the reference signal.

[0052] The second comparing unit 142 is used to compare the theoretical indication signal with the data indication signal, and generate an enable identification signal based on the comparison result of the theoretical indication signal and the data indication signal.

[0053] Specifically, when the theoretical indication signal and the data indication signal are the same, that is, the introduction of the offset voltage has little effect on the acquired data indication signal, and the enable identification signal generated at this time is a low level; when the theoretical indication signal and the data indication signal are different, that is, the introduction of the offset voltage has a greater impact on the acquired data indication signal, and the enable identification signal generated at this time is a high level.

[0054] Continue to refer Figure 1 The offset correction module 103 includes: a control unit 113 and a correction unit 123 .

[0055] The control unit 113 is used to receive the enable identification signal and generate a corresponding control signal based on the enable identification signal.

[0056] The correction unit 123 changes the conduction state of the internal transistor array based on the control signal to offset the offset signal generated in the data acquisition module 101 .

[0057] Specifically, in this embodiment, refer to Figure 4 , the correction unit 123 includes: a correction MOS tube array connected in parallel with the second differential MOS tube.

[0058] The correction MOS transistor array includes N parallel branch correction MOS transistors, the width-to-length ratios of the N branch correction MOS transistors increase exponentially according to a 2 relationship, and the equivalent width-to-length ratio of the N branch MOS transistors is smaller than that of the second differential MOS transistor 304, and N is a natural number greater than or equal to 1.

[0059] Specifically, if the width-to-length ratio of the correction MOS tube 407 of the first branch is m, the width-to-length ratio of the correction MOS tube 417 of the second branch is 2m, the width-to-length ratio of the correction MOS tube 427 of the third branch is 4m, and the width-to-length ratio of the correction MOS tube 437 of the Nth branch is 2m, then N-1 m. At this time, the sum of the equivalent width-to-length ratios of the correction MOS tubes of the N branches is (2 N -1) m is smaller than the width-to-length ratio of the second differential MOS transistor 304, so the value of m is determined based on the set number of array branches N.

[0060] In this embodiment, the correction MOS transistor array further includes: a switch MOS transistor connected in series with the correction MOS transistor on each branch; the drain of the correction MOS transistor is connected to the drain of the second differential MOS transistor, the source of the correction MOS transistor is connected to the source of the switch MOS transistor, and the source of the switch MOS transistor is connected to the source of the second differential MOS transistor.

[0061] In one example, refer to Figure 4 The correction MOS transistor 407 on the first branch of the correction MOS transistor array is connected to the first switch MOS transistor 406; the correction MOS transistor 417 on the second branch of the correction MOS transistor array is connected to the second switch MOS transistor 416; the correction MOS transistor 427 on the third branch of the correction MOS transistor array is connected to the third switch MOS transistor 426; the correction MOS transistor 437 on the Nth branch of the correction MOS transistor array is connected to the Nth switch MOS transistor 436. The switch MOS transistor is used to determine whether to conduct the branch according to the control signal, so as to change the equivalent width-to-length ratio of the second differential MOS transistor 304, so as to correspondingly amplify the received reference signal to offset the offset signal.

[0062] Specifically, the control signal is Figure 2 and Figure 3 The code shown in <n:0>,Code <n:0>is an N-bit binary number, see Figure 4 , Code <n>Indicates control signal Code <n:0>The Nth binary number in the MOS transistor array, 1 represents a high level, 0 represents a low level, the high level is used to turn on the corresponding branch of the correction MOS transistor array, and the low level is used to turn off the corresponding branch of the correction MOS transistor array. In an example, the signal Code<4:0> of 4 branches is used for explanation, for example, Code<4:0> is 1110, that is, Code<4:0> is 1110. <0> =0, Code <1> =1, Code <2> =1, Code <3> =1; the second branch, the third branch and the fourth branch of the correction MOS tube are turned on accordingly, and the first branch of the correction MOS tube array is turned off.

[0063] refer to Figure 5 After receiving the ZQCL command, after a clock delay, the DQ_BFenable signal and the enable signal turned on based on the ZQCL command jump from a low level to a high level, the enable signal is used to control the operation of the trimming enable module 102, and the DQ_BF enable signal is used to control the operation of the offset correction module 103, until the DQ_BF enable signal and the enable signal jump from a high level to a low level, and the correction stops; the period from receiving the ZQCL command to stopping the correction is the correction time TZQoper controlled by the ZQCL command.

[0064] Compared with the prior art, the adjustment enable module is turned on by an enable signal, the adjustment enable module generates an enable identification signal based on the comparison result of the theoretical indication signal and the data indication signal, and the offset correction module offsets the offset signal generated in the data acquisition module based on the enable identification signal, thereby ensuring that the data indication signal is consistent with the theoretical indication signal, thereby avoiding the error of the acquired data indication signal caused by the offset signal.

[0065] It is worth mentioning that all modules involved in this embodiment are logic modules. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, this embodiment does not introduce units that are not closely related to solving the technical problem proposed by the present invention, but this does not mean that there are no other units in this embodiment.

[0066] A second embodiment of the present invention relates to an offset voltage correction method.

[0067] Figure 6 The flowchart of the offset voltage correction method provided in this embodiment is as follows. Figure 6 The offset voltage correction method provided in this embodiment is described in detail, and parts identical or corresponding to those in the first embodiment will not be described in detail below.

[0068] refer to Figure 6 , an offset voltage correction method, comprising the following steps:

[0069] Step 501: Receive a data signal and a reference signal.

[0070] The data signal is the actual DQ signal received by the data acquisition module, and the actual DQ signal is a continuous analog signal. The reference signal is the VREFDQ signal, and the reference signal is used to compare with the actual DQ signal to obtain a signal for characterizing high and low levels, thereby controlling the corresponding functions of the memory.

[0071] Step 502: Acquire a data indication signal.

[0072] Specifically, based on the comparison result of the reference signal and the detuned data signal, the data indication signal is obtained, and the detuned data signal is the data signal after the detuned signal is superimposed. If the reference signal is greater than the data signal after the detuned signal is superimposed, the obtained data indication signal is low level, that is, the DQ_int signal is low level; if the reference signal is less than the data signal after the detuned signal is superimposed, the obtained data indication signal is high level, that is, the DQ_int signal is high level.

[0073] Step 503, obtaining an enable signal, and determining whether the enable signal is at a high level.

[0074] Specifically, an enable signal is obtained. If the enable signal is at a high level, the correction of the offset signal is started, that is, step 504 is entered; if the enable signal is at a low level, the correction of the offset signal is not performed, that is, the end step is entered.

[0075] The enable signal is generated based on the ZQCL (ZQ Calibration Long) command. The ZQCL command is an internal memory command used for system power-on initialization and device reset in ZQ calibration. That is, the offset voltage correction circuit in this embodiment works based on the internal command and has a stable working environment and safety.

[0076] Step 504, obtaining a theoretical indication signal.

[0077] Specifically, based on the comparison result of the data signal and the reference signal, a theoretical indication signal is obtained. If the reference signal is greater than the data signal, the obtained theoretical indication signal is a low level; if the reference signal is less than the data signal, the obtained theoretical indication signal is a high level.

[0078] Step 505: Generate an enable identification signal.

[0079] Specifically, based on the comparison result of the data indication signal and the theoretical indication signal, an enable identification signal is generated. When the theoretical indication signal and the data indication signal are the same, that is, the offset voltage does not have much impact on the acquired data indication signal, the enable identification signal generated at this time is a low level; when the theoretical indication signal and the data indication signal are different, that is, the offset voltage has a greater impact on the acquired data indication signal, the enable identification signal generated at this time is a high level.

[0080] Step 506: Compensate for the offset signal superimposed on the data signal.

[0081] Specifically, based on the enable identification signal, the offset signal superimposed in the data signal is offset.

[0082] More specifically, the state of the enable identification signal is determined, and if the enable identification signal is at a high level, a corresponding control signal is generated according to the enable identification signal; if the enable identification signal is at a low level, no control signal is generated. According to the control signal, the offset correction module is adjusted to offset the offset signal.

[0083] In one example, a method for adjusting an offset correction module includes: obtaining a target on-off state of each MOS tube in a correction MOS tube array based on a control signal; obtaining an actual on-off state of each MOS tube in the correction MOS tube array; adjusting the actual on-off state based on the target on-off state shown; and offsetting an offset signal superimposed in a data signal by changing a reference signal.

[0084] Compared with the prior art, the offset voltage correction method is started by an enable signal, an enable identification signal is generated based on the comparison result of the theoretical indication signal and the data indication signal, and the offset signal generated is offset based on the enable identification signal, thereby ensuring that the data indication signal is consistent with the theoretical indication signal, thereby avoiding the error of the acquired data indication signal caused by the offset signal.

[0085] The above-mentioned various steps are divided only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the protection scope of this patent. Adding insignificant modifications to the process or introducing insignificant designs that do not change the core design of the process are all within the protection scope of this patent.

[0086] Since the first embodiment corresponds to this embodiment, this embodiment can be implemented in conjunction with the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

[0087] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present invention, and that in actual applications, various changes may be made in form and detail without departing from the spirit and scope of the present invention. < / n>

Claims

1. An offset voltage correction circuit, characterized in that: include: A data acquisition module, used for receiving a data signal and a reference signal, and acquiring a data indication signal according to a comparison result between the reference signal and the misaligned data signal, wherein the misaligned data signal is a data signal after superimposing the misaligned signal introduced by the data receiving unit, and the data acquisition module includes the data receiving unit; A trimming and enabling module, configured to receive the data signal, the reference signal, the data indication signal and an enabling signal; If the enable signal is at a high level, a theoretical indication signal is obtained according to a comparison result of the data signal and the reference signal, and an enable identification signal is generated based on a comparison result of the theoretical indication signal and the data indication signal; An offset correction module is used to offset the offset signal based on the enable identification signal.

2. The offset voltage correction circuit according to claim 1, characterized in that: The data acquisition module comprises: The data receiving unit has a first input terminal and a second input terminal, the first input terminal is used to receive the data signal, and the second input terminal is used to receive the reference signal; A data comparison unit, whose input end is connected to the output end of the data receiving unit, is used to compare the reference signal with the data signal after the offset signal is superimposed, and obtain the data indication signal.

3. The offset voltage correction circuit according to claim 1 or 2, characterized in that: The data receiving unit at least includes a receiving differential amplifier circuit, which is used to amplify the received data signal and the reference signal.

4. The offset voltage correction circuit according to claim 3, characterized in that: The receiving differential amplifier circuit comprises: a first differential MOS transistor and a second differential MOS transistor; The gate of the first differential MOS transistor is used to receive the data signal, and the source of the first differential MOS transistor is used to connect to a first load; the gate of the second differential MOS transistor is used to receive the reference signal, and the source of the second differential MOS transistor is used to connect to a second load; The drain of the first differential MOS transistor and the drain of the second differential MOS transistor are connected to the same current source, so that the first differential MOS transistor and the second differential MOS transistor form a differential pair.

5. The offset voltage correction circuit according to claim 4, characterized in that: The first load and the second load use the same load circuit.

6. The offset voltage correction circuit according to claim 2, characterized in that: The data comparison unit includes a comparator.

7. The offset voltage correction circuit according to claim 1, characterized in that: The adjustment enabling module comprises: A receiving unit, configured to receive the data signal, the reference signal, the data indication signal and the enable signal; A judging unit, used for judging whether the enable signal is at a high level, and when the enable signal is at a high level, turning on the first comparing unit and the second comparing unit; The first comparing unit is used to compare the data signal with the reference signal, and obtain the theoretical indication signal based on the comparison result of the data signal and the reference signal; The second comparison unit is used to compare the theoretical indication signal and the data indication signal, and generate the enable identification signal based on the comparison result of the theoretical indication signal and the data indication signal.

8. The offset voltage correction circuit according to claim 4, characterized in that: The offset correction module comprises: A control unit, configured to receive the enable identification signal and generate a corresponding control signal based on the enable identification signal; The correction unit changes the conduction condition of the internal transistor array based on the control signal to offset the offset signal.

9. The offset voltage correction circuit according to claim 8, characterized in that: The correction unit comprises: a correction MOS transistor array connected in parallel with the second differential MOS transistor; The correction MOS tube array comprises: N parallel branch correction MOS tubes; The width-to-length ratios of the correction MOS tubes of the N branches increase exponentially according to a 2 relationship, and the sum of the equivalent width-to-length ratios of the MOS tubes of the N branches is less than that of the second differential MOS tube; The N is a natural number greater than or equal to 1.

10. The offset voltage correction circuit according to claim 9, characterized in that: The correction MOS tube array further comprises: a switch MOS tube connected in series with the correction MOS tube on each branch; The drain of the correction MOS tube is connected to the drain of the second differential MOS tube, the source of the correction MOS tube is connected to the drain of the switch MOS tube, and the source of the switch MOS tube is connected to the source of the second differential MOS tube; The switch MOS tube is used to determine whether to conduct the branch circuit according to the control signal.

11. A method for correcting an offset voltage, applied to a memory, characterized in that: include: receiving a data signal and a reference signal; Based on the comparison result of the reference signal and the misaligned data signal, a data indication signal is obtained, wherein the misaligned data signal is a data signal after the misaligned signal introduced in the process of superimposing the received data signal and the reference signal; Acquire an enable signal, and when the enable signal is at a high level, acquire a theoretical indication signal based on a comparison result of the data signal and the reference signal; Based on the comparison result of the data indication signal and the theoretical indication signal, generating an enable identification signal; Based on the enable identification signal, the offset signal is offset.

12. The offset voltage correction method according to claim 11, characterized in that: The canceling the offset signal based on the enable identification signal includes: Determining the state of the enable identification signal; If the enable identification signal is at a high level, a corresponding control signal is generated according to the enable identification signal; if the enable identification signal is at a low level, no control signal is generated; The offset correction module is adjusted according to the control signal to offset the offset signal.

13. The offset voltage correction method according to claim 12, characterized in that: The step of adjusting the offset correction module according to the control signal to offset the offset signal comprises: Based on the control signal, a target on-off state of each MOS tube in the MOS tube array is obtained and corrected; Acquiring the actual on / off state of each MOS tube in the correction MOS tube array; Based on the target on-off state, the actual on-off state is adjusted.

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