Method for manufacturing trench gate
By using chemical mechanical grinding and etching technology to form the gate bottom oxide layer during the manufacturing process of the trench gate, the problems of complex and high cost in the prior art are solved, and the effect of simplifying the process and reducing costs is achieved.
Patent Information
- Application Number
- CN202111542456.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-13
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2041-12-13
AI Technical Summary
In the prior art, the process of forming the gate bottom oxide layer (BTO) of the trench gate is complex and costly, making it difficult to realize a low-cost manufacturing method.
The second trench is formed by forming a trench on the surface of the semiconductor substrate and forming a first oxide layer on the bottom and sides of the trench. The second dielectric layer is then deposited on the surface of the first oxide layer, and performs a first chemical mechanical grinding, removing the second dielectric layer and retaining a partial thickness of the first oxide layer. A second etching is then performed, and the first oxide layer is etched using the second dielectric layer as a mask to form the gate bottom oxide layer.
The formation process of the gate bottom oxide layer is simplified, the process cost is reduced, and the complexity of the lithography process is avoided.
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Figure CN114242577B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a trench gate. Background Art
[0002] In a MOS transistor, the gate structure includes a gate oxide layer and a polysilicon gate formed on the surface of the gate oxide layer. The polysilicon gate usually covers the channel region and is used to form a channel connecting the source and drain on the surface of the channel region. In order to provide high controllability of the gate, a thinner gate oxide layer is generally required; however, for high gate reliability and small Miller capacitance, a thicker gate oxide layer is required. That is, a thinner gate oxide layer is conducive to the control of channel opening, but a thinner gate oxide layer will reduce the etching property and increase the Miller capacitance.
[0003] The gate structure includes two types: planar gate and trench gate. Trench gate can obtain a higher current density and a lower on-resistance and is often used in power devices.
[0004] The trench gate generally includes a trench, a gate oxide layer formed on the inner surface of the trench including the bottom surface and the side surface, and a polysilicon gate that completely fills the trench. The trench gate needs to pass through the channel region so that the polysilicon gate can cover the channel region from the side so that a channel can be formed on the surface of the channel region covered by the side of the polysilicon gate when the gate is turned on.
[0005] As can be seen from the above description, there is a contradiction between the thickness of the gate oxide layer and the requirements of gate controllability, reliability and Miller capacitance. For the trench gate, in order to compromise between the contradictions, it is usually necessary to adopt a trench bottom thick oxide (Bottom Thick Oxide, BTO) process in the trench gate. In the specification of the present invention, BTO is referred to as the gate bottom oxide layer. The "thick" in the trench bottom thick oxide layer means that the thickness of the trench bottom thick oxide layer is thicker than the gate oxide layer.
[0006] In this way, there are two kinds of oxide layers in the trench gate, one is BTO and the other is gate oxide layer. The oxide layer between the polysilicon gate and the channel region is a thinner gate oxide layer, which can ensure the gate control force. In the bottom and bottom corners (Corner) where reliability problems are prone to occur, a thick oxide layer, namely BTO, is used to ensure the high reliability of the device.
[0007] However, the use of BTO technology will increase the process flow, which will also increase the manufacturing cost. It is very important to realize this structure at a low cost. There are two mainstream methods for realizing BTO in the prior art.
[0008] The first existing method is to fill the trench with a high density plasma (HDP) oxide layer, and then achieve planarization and etching back through chemical mechanical polishing (CMP), which is very costly.
[0009] The second existing method is: first form a thicker BTO layer, which will be located on the entire inner surface and outer surface of the groove after formation; then apply photoresist to completely fill the entire groove, and the photoresist will also fill the surface outside the groove; adjust the exposure amount by the thickness difference between the photoresist on the outer surface of the groove and the inside of the groove to ensure that the surface is fully exposed and the inside of the groove is underexposed, so that after development, the photoresist of the required thickness will be retained inside the groove; the thick gate oxide, i.e., the BTO layer, which has been formed in advance, is protected by the photoresist retained inside the groove, and the thick gate oxide in other areas is removed by wet process; then, the thin gate oxide in the channel area, i.e., the gate oxide layer described above, is realized by forming a film again. As can be seen from the above, the second existing method requires an additional photolithography, and the cost is relatively high. Moreover, due to the coating characteristics of the photoresist, this method is also difficult to implement for a groove structure with a low aspect ratio.
[0010] like Figure 1 , which is a schematic diagram of a trench gate with BTO formed by an existing method; it can be seen that a thicker BTO layer 102 is formed at the bottom of the trench 101, a thinner gate oxide layer 103 is formed on the side of the trench 101 at the top of the BTO layer 102, and finally the polysilicon gate 104 completely fills the trench 101.
[0011] like Figure 2 As shown, it is a schematic diagram of the photoresist pattern after layout in the second method of forming a trench gate with BTO; it can be seen that the groove 201 has a small aspect ratio, that is, the depth is shallow and the width is wide, and the thicker oxide layer 202 used to form the BTO layer is formed and then coated with the photoresist 203. It can be seen that due to the small depth-to-width ratio of the groove 201, the filling morphology of the groove 201 by the photoresist 203 is not good, and a depression as shown by the dotted circle 204 will be formed at the top of the groove 201, which is not conducive to the subsequent exposure and development of the photoresist 203 and the subsequent wet etching of the oxide layer 202. Summary of the invention
[0012] The technical problem to be solved by the present invention is to provide a method for manufacturing a trench gate, which can simplify the formation process of the oxide layer at the bottom of the gate, namely, BTO, thereby reducing the process cost.
[0013] In order to solve the above technical problems, the present invention provides a method for manufacturing a trench gate, comprising the following steps:
[0014] Step 1: forming a groove on the surface of the semiconductor substrate.
[0015] Step 2: forming a first oxide layer on the bottom surface and side surfaces of the trench and the surface outside the trench;
[0016] The growth rate of the first oxide layer at the top corner of the groove is greater than the growth rate at the side of the groove. After the first oxide layer is formed, the top of the groove needs to be kept open; in the groove, a second groove is formed in the area surrounded by the first oxide layer.
[0017] Step three: depositing a second dielectric layer on the surface of the first oxide layer.
[0018] The growth rate of the second dielectric layer at the top corner of the trench is greater than the growth rate at the side of the trench. After the second dielectric layer is formed, the top of the trench remains open or the top opening is closed.
[0019] Step 4: performing a first chemical mechanical polishing process, wherein the first chemical mechanical polishing process removes the second dielectric layer exposed on the surface of the first oxide layer outside the second groove and retains a portion of the thickness of the first oxide layer outside the second groove or removes the first oxide layer entirely.
[0020] After the first chemical mechanical polishing process, in the groove region, the retained second dielectric layer covers the side and bottom surfaces of the second groove, and the surface of the first oxide layer outside the second groove is exposed.
[0021] Step 5: Perform a second etching on the first oxide layer. After the second etching, the first oxide layer is only retained on the bottom surface of the groove and the bottom area of the side to form a gate bottom oxide layer. The second etching uses the retained second dielectric layer as a mask to etch the first oxide layer from top to bottom.
[0022] Step six: removing the second dielectric layer.
[0023] Step seven: growing a gate oxide layer, wherein the gate oxide layer is located on the side of the trench at the top of the gate bottom oxide layer, and the thickness of the gate oxide layer is less than the thickness of the gate bottom oxide layer.
[0024] A further improvement is that the method further comprises the following steps:
[0025] Step eight: filling the trench with a gate electrode material layer.
[0026] A further improvement is that the gate electrode material layer is a polysilicon gate.
[0027] A further improvement is that the semiconductor substrate is a silicon substrate.
[0028] A further improvement is that the first oxide layer is silicon oxide, and the gate oxide layer is silicon oxide.
[0029] A further improvement is that the process of forming the first oxide layer in step 2 adopts a thermal oxidation process or a chemical vapor deposition process or a thermal oxidation process plus a chemical vapor deposition process.
[0030] A further improvement is that in step seven, a thermal oxidation process is used to form the gate oxide layer.
[0031] A further improvement is that in step 2, after the first oxide layer is formed, the width of the top opening of the groove is greater than
[0032] A further improvement is that the material of the second dielectric layer includes silicon nitride.
[0033] A further improvement is that the selectivity ratio of the first chemical mechanical polishing to the first oxide layer and the second dielectric layer in step 4 is less than 5:1.
[0034] A further improvement is that before performing step four, a third oxide layer is formed, and the third oxide layer closes the top opening of the groove; in the first chemical mechanical polishing of step four, the third oxide layer protects the second dielectric layer in the groove.
[0035] A further improvement is that in step six, wet etching is used to remove the second dielectric layer.
[0036] A further improvement is that in step five, the second etching is performed by wet etching.
[0037] A further improvement is that the trench gate is a gate structure of a MOS transistor, and further includes the following steps:
[0038] Step nine, forming a channel region, the depth of the channel region is less than the depth of the gate oxide layer; the gate electrode material layer covers the channel region through the side of the gate oxide layer, and the surface of the channel region covered by the side of the gate electrode material layer is used to form a channel; the semiconductor substrate is doped with a first conductivity type, and the channel region is doped with a second conductivity type.
[0039] Step ten: forming a heavily doped source region of the first conductivity type on the surface of the channel region.
[0040] Step 11: forming a heavily doped drain region of the first conductivity type on the back side of the semiconductor substrate.
[0041] A further improvement is that the MOS transistor is an NMOS transistor, the first conductivity type is N type, and the second conductivity type is P type; the MOS transistor is a PMOS transistor, the first conductivity type is P type, and the second conductivity type is N type.
[0042] The present invention ensures that the top of the groove will not be sealed when the first oxide layer is filled in the groove, and the first oxide layer in the groove surrounds the second groove. After that, a second dielectric layer is deposited, and after the first chemical mechanical polishing, the second dielectric layer only covers the side and bottom surfaces of the second groove, and the second dielectric layer outside the second groove is removed, so that the surface of the first oxide layer outside the second groove is exposed, and the exposed first oxide layer can be etched from top to bottom by using the remaining second dielectric layer as a mask, that is, the second etching is etching from top to bottom, so that the required gate bottom oxide layer can be obtained. As can be seen from the above, the present invention does not need to use a photolithography process to define the mask for the second etching of the first oxide layer, but can be achieved by adding a second dielectric layer deposition and the first chemical mechanical polishing. Compared with the photolithography process, the process of the present invention is simpler, so the present invention can simplify the formation process of the gate bottom oxide layer, thereby reducing the process cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0044] Figure 1 is a schematic diagram of a trench gate with BTO formed by a conventional method;
[0045] Figure 2 It is a schematic diagram of the second method of forming a trench gate with BTO in the prior art after the photoresist pattern is laid;
[0046] Figure 3 is a flow chart of a method for manufacturing a trench gate according to an embodiment of the present invention;
[0047] Figure 4A-4G It is a schematic structural diagram of a device of a method for manufacturing a trench gate according to an embodiment of the present invention. DETAILED DESCRIPTION
[0048] like Figure 3 As shown, it is a flow chart of a method for manufacturing a trench 302 gate according to an embodiment of the present invention; FIG. 4A to FIG. 4G FIG. 1 is a schematic diagram of the structure of a device of a method for manufacturing a trench 302 gate according to an embodiment of the present invention. The method for manufacturing a trench 302 gate according to an embodiment of the present invention comprises the following steps:
[0049] Step 1: Figure 4A As shown, a trench 302 is formed on the surface of a semiconductor substrate 301 .
[0050] In the method of the embodiment of the present invention, the semiconductor substrate 301 is a silicon substrate.
[0051] Step 2: Figure 4A As shown, a first oxide layer 303 is formed on the bottom surface and side surfaces of the trench 302 and the surface outside the trench 302 .
[0052] The growth rate of the first oxide layer 303 at the top corner of the groove 302 is greater than the growth rate at the side of the groove 302. After the first oxide layer 303 is formed, the top of the groove 302 needs to be kept open; within the groove 302, the second groove 304 is formed in the area surrounded by the first oxide layer 303.
[0053] In the method of the embodiment of the present invention, the first oxide layer 303 is silicon oxide.
[0054] The process for forming the first oxide layer 303 is a thermal oxidation process, a chemical vapor deposition process, or a thermal oxidation process plus a chemical vapor deposition process.
[0055] Preferably, after the first oxide layer 303 is formed, the width of the top opening of the trench 302 is greater than Typical value is The thicker the first oxide layer 303 is, the smaller the top opening of the trench 302 is.
[0056] Step 3: Figure 4B As shown, a second dielectric layer 305 is deposited on the surface of the first oxide layer 303 .
[0057] The growth rate of the second dielectric layer 305 at the top corner of the trench 302 is greater than the growth rate at the side of the trench 302. After the second dielectric layer 305 is formed, the top of the trench 302 remains open or the top opening is closed. Figure 4B In the embodiment, the top of the groove 302 remains open; in other embodiments, the top opening of the groove 302 can also be closed by the second dielectric layer 305.
[0058] In the method of the embodiment of the present invention, the thickness of the second dielectric layer 305 can be moderate. For example, after the deposition in step 3 is completed, the thickness of the second dielectric layer 305 on the surface of the first oxide layer 303 outside the groove 302 is
[0059] The material of the second dielectric layer 305 includes silicon nitride.
[0060] Step 4: Figure 4CAs shown, a first chemical mechanical polishing process is performed to remove the second dielectric layer 305 exposed on the surface of the first oxide layer 303 outside the second groove 304 and to retain a partial thickness of the first oxide layer 303 outside the second groove 304 or remove it completely. Figure 4C In the process, the first oxide layer 303 outside the second trench 304 is completely removed, and the surface of the semiconductor substrate 301 is directly used as the stop layer of the first chemical mechanical polishing process.
[0061] After the first chemical mechanical polishing process, in the region of the groove 302 , the retained second dielectric layer 305 covers the side and bottom surfaces of the second groove 304 , and the surface of the first oxide layer 303 outside the second groove 304 is exposed.
[0062] In the embodiment of the present invention, the first chemical mechanical polishing selects chemical mechanical polishing with a low OX / SiN selectivity ratio. For example, the selectivity ratio of the first chemical mechanical polishing to the first oxide layer and the second dielectric layer 305 is less than 5:1.
[0063] In other embodiments, the method may further include: before performing step 4, forming a third oxide layer, the third oxide layer sealing the top opening of the trench 302; in the first chemical mechanical polishing of step 4, the third oxide layer protects the second dielectric layer 305 in the trench 302. In this way, the second dielectric layer 305 in the trench 302 can be prevented from being damaged during the first chemical mechanical polishing process.
[0064] In some other embodiments, if the first chemical mechanical polishing process does not polish the surface of the semiconductor substrate 301 , an etching process such as wet etching may be performed subsequently to completely remove the first oxide layer 303 outside the second trench 304 .
[0065] Step 5: Figure 4D As shown, the first oxide layer 303 is etched for the second time. After the second etching, the first oxide layer 303 is only retained on the bottom surface of the groove 302 and the bottom area of the side to form a gate bottom oxide layer 303a. The second etching uses the retained second dielectric layer 305 as a mask to etch the first oxide layer 303 from top to bottom.
[0066] In the method of the embodiment of the present invention, the second etching is performed by wet etching.
[0067] Step 6: Figure 4E As shown, the second dielectric layer 305 is removed.
[0068] In the method of the embodiment of the present invention, wet etching is used to remove the second dielectric layer 305 .
[0069] Step 7: Figure 4F As shown, a gate oxide layer 306 is grown, and the gate oxide layer 306 is located on the side of the trench 302 at the top of the gate bottom oxide layer 303a, and the thickness of the gate oxide layer 306 is less than the thickness of the gate bottom oxide layer 303a.
[0070] In the method of the embodiment of the present invention, the gate oxide layer 306 is silicon oxide.
[0071] Preferably, the gate oxide layer 306 is formed by a thermal oxidation process.
[0072] Before forming the gate oxide layer 306 , a sacrificial oxide layer is formed and then removed to eliminate defects on the side of the trench 302 .
[0073] Step 8: Figure 4F As shown, a gate electrode material layer 307 is filled in the trench 302 .
[0074] In the method of the embodiment of the present invention, the gate electrode material layer 307 is a polysilicon gate.
[0075] The trench gate is a gate structure of a MOS transistor, and further includes the following steps:
[0076] Step 9: Figure 4G As shown, a channel region 308 is formed, and the depth of the channel region 308 is less than the depth of the gate oxide layer 306; the gate electrode material layer 307 covers the channel region 308 through the side of the gate oxide layer 306, and the surface of the channel region 308 covered by the side of the gate electrode material layer 307 is used to form a channel; the semiconductor substrate 301 is doped with the first conductivity type, and the channel region 308 is doped with the second conductivity type.
[0077] Step 10: Figure 4G As shown, a source region 309 heavily doped with the first conductivity type is formed on the surface of the channel region 308 .
[0078] Step 11: forming a heavily doped drain region of the first conductivity type on the back side of the semiconductor substrate 301 .
[0079] In the embodiment of the present invention, the MOS transistor is an NMOS transistor, the first conductivity type is N type, and the second conductivity type is P type. In other embodiments, the MOS transistor can also be a PMOS transistor, the first conductivity type is P type, and the second conductivity type is N type.
[0080] In the embodiment of the present invention, when the first oxide layer 303 is filled in the groove 302, it is ensured that the top of the groove 302 is not sealed and the first oxide layer 303 in the groove 302 surrounds the second groove 304. Then, a second dielectric layer 305 is deposited and after the first chemical mechanical polishing, the second dielectric layer 305 only covers the side and bottom surfaces of the second groove 304, and the second dielectric layer 305 outside the second groove 304 is removed, so that the surface of the first oxide layer 303 outside the second groove 304 is exposed, so that the exposed first oxide layer 303 can be used as the residual The second dielectric layer 305 is used as a mask to achieve etching from top to bottom, that is, the second etching is etching from top to bottom, so that the required gate bottom oxide layer 303a can be obtained. From the above, it can be seen that the embodiment of the present invention does not need to use a photolithography process to define the mask for the second etching of the first oxide layer 303, but can be achieved by adding a second dielectric layer 305 deposition and a first chemical mechanical polishing. Compared with the photolithography process, the process of the embodiment of the present invention is simpler, so the embodiment of the present invention can simplify the formation process of the gate bottom oxide layer 303a, thereby reducing the process cost.
[0081] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A method for manufacturing a trench gate, characterized in that: The steps include: Step 1: forming a groove on the surface of the semiconductor substrate; Step 2: forming a first oxide layer on the bottom surface and side surfaces of the trench and the surface outside the trench; The growth rate of the first oxide layer at the top corner of the groove is greater than the growth rate at the side of the groove. After the first oxide layer is formed, the top of the groove needs to be kept in an open state; in the groove, a second groove is formed in the area surrounded by the first oxide layer; Step 3, depositing a second dielectric layer on the surface of the first oxide layer; The growth rate of the second dielectric layer at the top corner of the trench is greater than the growth rate at the side of the trench, and after the second dielectric layer is formed, the top of the trench remains in an open state or the top opening is closed; Step 4: performing a first chemical mechanical polishing process, wherein the first chemical mechanical polishing process removes all of the second dielectric layer exposed on the surface of the first oxide layer outside the second trench and leaves a portion of the first oxide layer outside the second trench thick or removes all of the first oxide layer; After the first chemical mechanical polishing process, in the groove region, the retained second dielectric layer covers the side and bottom surfaces of the second groove, and the surface of the first oxide layer outside the second groove is exposed; Step 5, etching the first oxide layer for a second time, wherein after the second etching, the first oxide layer is only retained on the bottom surface of the trench and the bottom area of the side surface to form a gate bottom oxide layer, and the second etching uses the retained second dielectric layer as a mask to etch the first oxide layer from top to bottom; Step six, removing the second dielectric layer; Step seven: growing a gate oxide layer, wherein the gate oxide layer is located on the side of the trench at the top of the gate bottom oxide layer, and the thickness of the gate oxide layer is less than the thickness of the gate bottom oxide layer.
2. The method for manufacturing a trench gate according to claim 1, wherein: The following steps are also included: Step eight: filling the trench with a gate electrode material layer.
3. The method for manufacturing a trench gate according to claim 2, wherein: The gate electrode material layer is a polysilicon gate.
4. The method for manufacturing a trench gate according to claim 1, wherein: The semiconductor substrate is a silicon substrate.
5. The method for manufacturing a trench gate according to claim 4, wherein: The first oxide layer is silicon oxide, and the gate oxide layer is silicon oxide.
6. The method for manufacturing a trench gate according to claim 5, wherein: Step 2: The process of forming the first oxide layer adopts a thermal oxidation process, a chemical vapor deposition process, or a thermal oxidation process plus a chemical vapor deposition process.
7. The method for manufacturing a trench gate according to claim 5, wherein: In step seven, a thermal oxidation process is used to form the gate oxide layer.
8. The method for manufacturing a trench gate according to claim 1, wherein: In step 2, after the first oxide layer is formed, the width of the top opening of the groove is greater than 500Å.
9. The method for manufacturing a trench gate according to claim 5, wherein: The material of the second dielectric layer includes silicon nitride.
10. The method for manufacturing a trench gate according to claim 9, wherein: The selectivity ratio of the first chemical mechanical polishing to the first oxide layer and the second dielectric layer in step 4 is less than 5:
1.
11. The method for manufacturing a trench gate according to claim 10, wherein: Before performing step 4, the method further includes forming a third oxide layer, wherein the third oxide layer seals the top opening of the groove; during the first chemical mechanical polishing of step 4, the third oxide layer protects the second dielectric layer in the groove.
12. The method for manufacturing a trench gate according to claim 10, wherein: In step six, the second dielectric layer is removed by wet etching.
13. The method for manufacturing a trench gate according to claim 1, wherein: In step five, the second etching is performed by wet etching.
14. The method for manufacturing a trench gate according to claim 2, wherein: The trench gate is a gate structure of a MOS transistor, and further includes the following steps: Step nine, forming a channel region, wherein the depth of the channel region is less than the depth of the gate oxide layer; the gate electrode material layer covers the channel region through the side of the gate oxide layer, and the surface of the channel region covered by the side of the gate electrode material layer is used to form a channel; The semiconductor substrate is doped with a first conductivity type, and the channel region is doped with a second conductivity type; Step 10: forming a heavily doped source region of the first conductivity type on the surface of the channel region; Step 11: forming a heavily doped drain region of the first conductivity type on the back side of the semiconductor substrate.
15. The method for manufacturing a trench gate according to claim 14, wherein: The MOS transistor is an NMOS transistor, the first conductivity type is N type, and the second conductivity type is P type; the MOS transistor is a PMOS transistor, the first conductivity type is P type, and the second conductivity type is N type.
Citation Information
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