A single-particle burnout-resistant rectifier diode and a reinforced manufacturing method thereof

Abstract

The present invention provides a single-particle burnout-resistant rectifier diode and a reinforced preparation method thereof, aiming to enhance the radiation resistance of high-voltage fast-recovery rectifier diodes for spacecraft and provide component protection for a new generation of spacecraft. In view of the phenomenon that high-voltage fast-recovery rectifier diodes are prone to form failure points at the edge of the main junction under high-energy particle irradiation, the present invention proposes a main junction edge local carrier lifetime control technology, which uses high-energy helium ion implantation to form local lattice damage at the edge of the main junction to introduce additional recombination centers, improve the recombination efficiency of carriers at the edge of the main junction, thereby reducing the current density and heat accumulation at the edge of the main junction, and achieving the purpose of improving the radiation resistance of high-voltage fast-recovery rectifier diodes. The radiation-resistant reinforcement preparation method for high-voltage fast-recovery rectifier diodes proposed by the present invention has the technical advantages of simple process preparation flow, mature technology, significant radiation-resistant reinforcement effect, and simultaneous consideration of device electrical performance, and has high application value.

Description

Technical Field

[0001] The invention relates to a method for reinforcing a single particle burnout effect rectifier diode, which is suitable for improving the radiation resistance of high-voltage fast recovery rectifier diodes for spacecraft and belongs to the technical field of radiation resistance reinforcement preparation of high-voltage fast recovery rectifier diodes. Background Art

[0002] The new generation of long-life satellites will use electric propulsion technology. In order to improve performance and reduce weight, high-voltage fast recovery rectifier diodes are needed. At the same time, the weight reduction of spacecraft power systems has also put forward application requirements for high-voltage power devices. High-voltage fast recovery rectifier diodes have become key components urgently needed for the new generation of spacecraft. In the early satellite model applications, the reverse breakdown voltage requirements for high-voltage fast recovery rectifier diodes were not high, and it was generally believed that they were not sensitive to single-particle burnout. However, as technologies such as electric propulsion have put forward higher requirements for the reverse breakdown voltage of high-voltage fast recovery rectifier diodes, the single-particle burnout problem caused by high reverse bias voltage has become one of the bottlenecks restricting the application of high-voltage fast recovery rectifier diode models, and it is urgent to solve the problem. Summary of the invention

[0003] The technical problem solved by the present invention is: in view of the problem that the radiation resistance of high-voltage fast recovery rectifier diodes cannot meet the needs of aerospace applications, the shortcomings of the existing process preparation flow are overcome, and a reinforced preparation method for rectifier diodes resistant to single particle burnout effect is provided to improve the radiation resistance of high-voltage fast recovery rectifier diodes and provide component protection for the new generation of spacecraft.

[0004] The technical solution of the present invention is: a single-particle burnout-resistant rectifier diode, wherein the edge region of the main junction region of the diode is a helium ion implantation region, and the edge region of the main junction region refers to a non-planar junction region generated at the edge during the formation of the main junction region.

[0005] The helium ion implantation energy in the helium ion implantation area is 630KeV to 700KeV, and the implantation dose is 1e14cm -2 ~5e14cm -2 .

[0006] Another technical solution of the present invention is: a method for reinforcing a rectifier diode resistant to single-particle burnout effect, the method comprising the following steps:

[0007] S1, field oxide layer growth: on N + Growing N on silicon substrate - Silicon epitaxial layer, and in N - A field oxide layer is grown on the surface of the silicon epitaxial layer;

[0008] S2, P + Field limiting ring and main junction region formation: In N -P is formed inside the silicon epitaxial layer + Field limiting ring and main junction region;

[0009] S3, Helium ion implantation: Helium ions are implanted and activated in the edge area of ​​the main junction region;

[0010] S4, front metallization: on P + An anode metal contact is formed on the surface of the main junction region;

[0011] S5, back metallization: on N + A cathode metal contact is formed on the back side of the silicon substrate.

[0012] Preferably, the specific steps of growing the field oxide layer in step S1 are:

[0013] A1.1、N - Epitaxial growth: on N + A layer of N is grown on the silicon substrate. - Silicon epitaxial layer; N - The silicon epitaxial layer is used to form a field limiting ring and a main junction region therein;

[0014] A1.2. Cleaning the silicon wafer surface before field oxidation: The silicon wafer formed in step A1.1 is subjected to RCA cleaning to remove impurities, dust particles, organic matter and metal ions on the surface of the silicon wafer while removing the natural silicon oxide on the surface of the silicon wafer;

[0015] A1.3. Growth of field oxide layer on silicon wafer surface: A field oxide layer is grown on the surface of the cleaned silicon wafer using a dry-wet-dry three-step thermal oxidation method. The thickness of the formed field oxide layer is

[0016] Preferably, the P in step S2 + The specific steps for forming the field limiting ring and the main junction region are:

[0017] A2.1、P + Boron implantation lithography: Using the photolithography process, the pattern on the photolithography mask is transferred to the photoresist to form a P + Boron implantation window region; the P + The boron implantation window area is P + Field limiting ring and main junction region;

[0018] A2.2. Wet etching of field oxide layer and photoresist: + Wet etching is performed in the boron implantation window area to remove N - A field oxide layer is grown in the corresponding area on the surface of the silicon epitaxial layer, and the remaining photoresist is removed;

[0019] A2.3. Surface cleaning before ion implantation protection oxidation: Clean the surface of the silicon wafer after etching in step A2.2;

[0020] A2.4, ion implantation to protect the oxide layer growth: the cleaned silicon wafer is placed in an oxidation furnace for growth. + A protective oxide layer grows in the boron implantation window area. The thickness of the protective oxide layer is

[0021] A2.5, P + Boron ion implantation: + Boron ions are implanted into the boron implantation window area, and the implantation dose of boron ions is 1e15cm -2 ~6e15cm -2 , the implantation energy is 75KeV~85KeV, in N - P is formed inside the silicon epitaxial layer + N - Knot;

[0022] A2.6, wet etching ion implantation protective oxide layer: remove P + Ion implantation of boron in the window area protects the oxide layer;

[0023] A2.7. Surface cleaning before ion propulsion: cleaning the surface of the silicon wafer formed after step A2.6;

[0024] A2.8, ion propulsion: Place the silicon wafer cleaned in step A2.7 into a diffusion furnace for diffusion, so that P + N - The junction depth increases, and the implanted boron ions are activated to form P + Field limiting ring and P + Main junction area.

[0025] Preferably, the specific steps of helium ion implantation in step S3 are:

[0026] A3.1、N - Growth of thermal oxide layer on epitaxial layer: Dry-wet-dry three-step thermal oxidation method is adopted. - A thermal oxide layer is grown on the surface of the epitaxial layer;

[0027] A3.2. Helium injection lithography: Using the photolithography process, the pattern on the photolithography mask is transferred to the photoresist to form a helium injection window area; the helium injection window area is P + The edge region of the main junction;

[0028] A3.3. Wet etching of thermal oxide layer: Wet etching is performed in the helium injection window area to remove N - A thermal oxide layer grown in the corresponding area on the surface of the silicon epitaxial layer;

[0029] A3.4. Helium ion implantation: Helium ion implantation is performed in the helium injection window area with a helium ion implantation dose of 1e14cm-2 ~5e14cm -2 , the injection energy is 630KeV~700KeV, and local lattice damage is introduced in the helium injection window area to achieve local carrier lifetime control;

[0030] A3.5. Wet etching of photoresist: Wet etching of silicon wafers, using stripping solution to remove the remaining photoresist;

[0031] A3.6. Impurity activation, i.e. activation of the injected helium ions.

[0032] Preferably, the specific steps of the front metallization in step S4 are:

[0033] A4.1、N - Growth of thermal oxide layer on epitaxial layer: Dry-wet-dry three-step thermal oxidation method is adopted. - A thermal oxide layer is deposited on the surface of the epitaxial layer;

[0034] A4.2. Front metal contact window lithography: Using the photolithography process, the pattern on the photolithography mask is transferred to the photoresist to form a front metal contact window area above the P+ main junction area;

[0035] A4.3, wet etching the thermal oxide layer and photoresist, wet etching the silicon wafer treated in step A4.2 to remove the thermal oxide layer deposited in the front metal contact window area, and remove the remaining photoresist with a stripping solution;

[0036] A4.4, evaporating metal: performing electron beam evaporation on the silicon wafer treated in step A4.3 to deposit metal on the silicon wafer, the metal is aluminum, and the metal thickness is 4 μm to 6 μm;

[0037] A4.5. Metal photolithography: Photolithography is performed on the silicon wafer after metal deposition to transfer the pattern on the photolithography mask to the photoresist so that the metal deposited outside the front metal contact window area can be removed in the subsequent process.

[0038] A4.6, Wet etching of metal and photoresist: Remove the metal outside the metal contact window area on the front side, and use a stripping solution to remove the photoresist applied during metal lithography;

[0039] A4.7 Metal alloying: Place the silicon wafer into an alloy furnace tube, and the metal part forms a metal alloy, which is used as the anode contact.

[0040] Preferably, the specific steps of back metallization in step S5 are:

[0041] A5.1. Surface passivation layer deposition: A passivation layer is deposited on the surface of the silicon wafer after the treatment in step S4. The thickness of the passivation layer is The passivation material is SiN;

[0042] A5.2. Surface passivation layer photolithography: The silicon wafer processed in step A5.1 is subjected to photolithography to transfer the pattern on the photolithography mask to the photoresist so as to remove the surface passivation layer above the anode metal contact area in the subsequent process;

[0043] A5.3. Wet-etch the surface passivation layer and photoresist to remove the surface passivation layer above the anode metal contact area, and use a stripping solution to remove the photoresist applied during photolithography of the surface passivation layer;

[0044] A5.4, Back thinning: Thin the silicon substrate from the back to reduce the thickness of the silicon wafer to 220μm~230μm, so as to reduce the forward on-resistance of the device;

[0045] A5.5. Back metal deposition: DC plasma sputtering is performed on the back side of the silicon substrate to deposit back metal to form a back metal contact. The back metal is TiNiAg.

[0046] The technical advantages of the present invention compared with the prior art are:

[0047] (1) The present invention carries out targeted radiation resistance reinforcement design for radiation failure sensitive areas, which can effectively improve the radiation resistance performance of high-voltage fast recovery rectifier diodes.

[0048] (2) The present invention controls the local carrier lifetime at the edge of the main junction, thereby improving the radiation resistance and improving the reverse recovery characteristics of the high-voltage fast recovery rectifier diode, which is beneficial to increasing the reverse recovery speed and reducing the reverse recovery charge.

[0049] (3) The present invention only realizes local carrier lifetime control at the edge of the main junction, and has little effect on the forward conduction voltage drop of the device. The preparation method proposed in the present invention can simultaneously take into account the electrical characteristics and radiation resistance characteristics of the high-voltage fast recovery rectifier diode.

[0050] (4) Based on the conventional high-voltage fast recovery rectifier diode process preparation process, the present invention realizes local carrier lifetime control through high-energy helium ion injection. Compared with the conventional process preparation process, only one more mask layer is needed to achieve the improvement of radiation resistance reinforcement capability. The technology is mature, easy to implement and low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a schematic diagram of the structure of an embodiment of the present invention.

[0052] Figure 2 The present invention is a process flow chart for preparing an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0054] A large amount of experimental data shows that under high-energy particle irradiation, high-voltage fast recovery rectifier diodes are prone to forming failure points at the edge of the main junction. This is related to the curvature effect at the edge of the main junction. Under high electric field strength, carrier avalanche multiplication is very likely to occur at the edge of the main junction, resulting in very high current density and power consumption density. If the heat accumulation at the edge of the main junction is high enough, it will cause lattice thermal damage, resulting in single particle burnout of the high-voltage fast recovery rectifier diode. This is an irreversible hard damage that will cause permanent failure of the device and even endanger the normal operation of the spacecraft power system.

[0055] Based on this, the present invention proposes a method for reinforcing a single-particle burnout-resistant rectifier diode. The edge region of the main junction region of the single-particle burnout-resistant rectifier diode is a helium ion implantation region, which is used to reduce the current density and heat accumulation at the edge of the main junction and improve the radiation resistance of the high-voltage fast recovery rectifier diode. The main junction region edge region refers to the non-planar junction region generated at the edge during the formation of the main junction region. Figure 1 shown.

[0056] Preferably, the helium ion implantation energy in the helium ion implantation zone is 630KeV to 700KeV, and the implantation dose is 1e14cm -2 ~5e14cm -2 .

[0057] The above-mentioned single-particle burnout-resistant rectifier diode utilizes high-energy helium ion implantation to introduce additional recombination centers at the edge of the main junction, thereby realizing local carrier lifetime control at the edge of the main junction, enhancing the recombination efficiency of carriers at the edge of the main junction, reducing the current density and heat accumulation at the edge of the main junction, and improving the radiation resistance of the high-voltage fast recovery rectifier diode.

[0058] like Figure 2 As shown, the specific process flow of the above-mentioned single-particle burnout resistant rectifier diode is as follows: field oxide layer growth, P + Field limiting ring and main junction region formation, helium ion implantation, front metallization, back metallization.

[0059] S1, field oxide layer growth: on N + Growing N on silicon substrate - Silicon epitaxial layer, and in N - A field oxide layer is grown on the surface of the silicon epitaxial layer;

[0060] The field oxide layer growth is to carry out N - Epitaxial growth, cleaning of silicon wafer surface before field oxidation, growth of field oxide layer on silicon wafer surface and other process operations; the specific steps are:

[0061] A1.1、N - Epitaxial growth: on N+ A layer of N is grown on the silicon substrate. - Silicon epitaxial layer; N - Silicon epitaxial layer

[0062] For forming a field limiting ring and a main junction region therein;

[0063] A1.2. Cleaning the silicon wafer surface before field oxidation: The silicon wafer formed in step A1.1 is subjected to RCA cleaning to remove the impurities, dust particles, organic matter and metal ions on the surface of the silicon wafer while removing the natural silicon oxide on the surface of the silicon wafer to prevent these impurities from affecting the subsequent processes; Liquid No. 1 and Liquid No. 2 can be used to clean the surface of the silicon wafer for 55 minutes to 65 minutes.

[0064] Wherein, the No. 1 liquid is obtained by mixing ammonia water: hydrogen peroxide solution: water in a volume ratio of 1:1:5 to 1:2:7, and the mass concentration of the ammonia water is 27%;

[0065] The No. 2 liquid is obtained by mixing hydrogen chloride: hydrogen peroxide solution: water in a volume ratio of 1:1:6 to 1:2:8, the mass concentration of the hydrogen chloride is 37%, and the mass concentration of the hydrogen peroxide solution is 30%.

[0066] A1.3. Growth of field oxide layer on silicon wafer surface: A field oxide layer is grown on the surface of the cleaned silicon wafer using a dry-wet-dry three-step thermal oxidation method. The thickness of the formed field oxide layer is

[0067] As a preferred solution, the temperature of the oxidation furnace is preferably controlled at 1120°C ± 1°C, and the duration is 200min to 220min.

[0068] S2, P + Field limiting ring and main junction region formation: In N - P is formed inside the silicon epitaxial layer + Field limiting ring and main junction region;

[0069] The P + The formation of field limiting ring and main junction region refers to the P + Boron diffusion lithography, wet etching field oxide layer, ion implantation protection oxidation surface cleaning, ion implantation protection oxide layer growth, P + Boron ion implantation, wet etching ion implantation to protect the oxide layer, surface cleaning before ion propulsion, ion propulsion and other process operations; the specific steps are:

[0070] A2.1、P + Boron implantation lithography: Using the photolithography process, the pattern on the photolithography mask is transferred to the photoresist to form a P + Boron implantation window region; the P + The boron implantation window area is P+ Field limiting ring and main junction region;

[0071] A2.2. Wet etching of field oxide layer and photoresist: + Wet etching is performed in the boron implantation window area to remove N - A field oxide layer is grown in the corresponding area on the surface of the silicon epitaxial layer, and the remaining photoresist is removed;

[0072] A2.3. Surface cleaning before ion implantation protection oxidation: Clean the surface of the silicon wafer after etching in step A2.2;

[0073] A2.4, ion implantation to protect the oxide layer growth: the cleaned silicon wafer is placed in an oxidation furnace for growth. + A protective oxide layer grows in the boron implantation window area. The thickness of the protective oxide layer is The temperature of the oxidation furnace is preferably 1100°C ± 1°C, and the duration is 20min to 30min.

[0074] A2.5, P + Boron ion implantation: + Boron ions are implanted into the boron implantation window area, and the implantation dose of boron ions is 1e15cm -2 ~6e15cm -2 , the implantation energy is 75KeV~85KeV, in N - P is formed inside the silicon epitaxial layer + N - Knot;

[0075] A2.6, wet etching ion implantation protective oxide layer: remove P + The ion implantation of the boron implant window area protects the oxide layer; the protective oxide layer can be removed using a solution of ammonium fluoride and hydrofluoric acid in a volume ratio of 6:1.

[0076] A2.7. Surface cleaning before ion propulsion: cleaning the surface of the silicon wafer formed after step A2.6;

[0077] A2.8, ion propulsion: Place the silicon wafer cleaned in step A2.7 into a diffusion furnace for diffusion. + N - The junction depth increases, and the implanted boron ions are activated to form P + Field limiting ring and P + Main junction area. The temperature of the diffusion furnace is preferably controlled at 1050℃±1℃, and the duration is 180min~240min.

[0078] S3, Helium ion implantation: Helium ions are implanted and activated in the edge area of ​​the main junction region;

[0079] The helium ion implantation refers to the process operations of helium implantation lithography, helium ion implantation, wet etching of photoresist, impurity activation, etc.; the specific steps are:

[0080] A3.1、N - Growth of thermal oxide layer on epitaxial layer: Dry-wet-dry three-step thermal oxidation method is adopted. - A thermal oxide layer is grown on the surface of the epitaxial layer;

[0081] A3.2. Helium injection lithography: Using the photolithography process, the pattern on the photolithography mask is transferred to the photoresist to form a helium injection window area; the helium injection window area is P + The edge region of the main junction;

[0082] A3.3. Wet etching of thermal oxide layer: Wet etching is performed in the helium injection window area to remove N - A thermal oxide layer grown in the corresponding area on the surface of the silicon epitaxial layer;

[0083] A3.4. Helium ion implantation: Helium ion implantation is performed in the helium injection window area with a helium ion implantation dose of 1e14cm -2 ~5e14cm -2 , the injection energy is 630KeV~700KeV, and local lattice damage is introduced in the helium injection window area to achieve local carrier lifetime control;

[0084] A3.5. Wet etching of photoresist: Wet etching of silicon wafers, using stripping solution to remove the remaining photoresist at room temperature;

[0085] A3.6. Impurity activation, i.e., activation of the implanted helium ions. This step is preferably performed at a temperature of 680°C to 750°C and lasts for 30 to 40 minutes.

[0086] S4, front metallization: on P + An anode metal contact is formed on the surface of the main junction region;

[0087] The front metallization refers to the process of performing front metal contact window photolithography, wet etching of thermal oxide layer, evaporation of front metal, front metal photolithography, wet etching of front metal, front metal alloy and the like. The specific steps are:

[0088] A4.1、N - Growth of thermal oxide layer on epitaxial layer: Dry-wet-dry three-step thermal oxidation method is adopted. - A thermal oxide layer is grown on the surface of the epitaxial layer;

[0089] A4.2. Front metal contact window lithography: Using the photolithography process, the pattern on the photolithography mask is transferred to the photoresist. +A front metal contact window region is formed above the main junction region;

[0090] A4.3. Wet-etch the thermal oxide layer and photoresist. Wet-etch the silicon wafer treated in step A4.2 to remove the thermal oxide layer deposited in the front metal contact window area, and use a stripping solution to remove the remaining photoresist at room temperature. You can use a 6:1 volume ratio of ammonium fluoride and hydrofluoric acid solution to remove the oxide layer.

[0091] A4.4, evaporating metal: performing electron beam evaporation on the silicon wafer treated in step A4.3 to deposit metal on the silicon wafer (surface), the metal being aluminum with a metal thickness of 4 μm to 6 μm;

[0092] A4.5. Metal photolithography: Photolithography is performed on the silicon wafer after metal deposition to transfer the pattern on the photolithography mask to the photoresist so that the metal deposited outside the front metal contact window area can be removed in the subsequent process.

[0093] A4.6. Wet etching of metal and photoresist: Remove the metal outside the metal contact window area on the front side, and use a stripping solution to remove the photoresist applied during metal photolithography at room temperature; the metal can be removed using a phosphoric acid solution with a volume ratio of 85% at room temperature.

[0094] A4.7. Metal alloying: Place the silicon wafer into the alloy furnace tube, and the metal part forms a metal alloy. The temperature of the alloy furnace tube is 420℃±1℃, and the alloying time is 10min~20min.

[0095] S5, back metallization: on N + A cathode metal contact is formed on the back side of the silicon substrate.

[0096] Back metallization refers to the process operations of surface passivation layer photolithography, wet etching of surface passivation layer, back thinning, back metal deposition, etc. The specific steps are:

[0097] A5.1. Surface passivation layer deposition: A passivation layer is deposited on the surface of the silicon wafer after the treatment in step S4. The thickness of the passivation layer is The passivation material is SiN;

[0098] A5.2. Surface passivation layer photolithography: The silicon wafer processed in step A5.1 is subjected to photolithography to transfer the pattern on the photolithography mask to the photoresist so as to remove the surface passivation layer above the anode metal contact area in the subsequent process;

[0099] A5.3. Wet-etch the surface passivation layer and photoresist to remove the surface passivation layer above the anode metal contact area, and use a stripping solution to remove the photoresist applied during photolithography of the surface passivation layer at room temperature; a phosphoric acid solution with a volume ratio of 85% can be used to remove the surface passivation layer above the anode metal contact area.

[0100] A5.4, Back thinning: Thin the thickness of the silicon substrate from the back to reduce the thickness of the silicon wafer to 220μm~230μm, so as to reduce the forward on-resistance of the device;

[0101] A5.5. Back metal deposition: DC plasma sputtering is performed on the back side of the silicon substrate to deposit back metal to form a back metal contact. The back metal is TiNiAg.

[0102] Parts of the present invention that are not described in detail belong to common knowledge among those skilled in the art.

Claims

1. A method for reinforcing a single-particle burnout-resistant rectifier diode, wherein the edge region of the main junction region of the diode is a helium ion implantation region, and the edge region of the main junction region refers to a non-planar junction region generated at the edge during the formation of the main junction region; characterized in that The steps include: S1, field oxide layer growth: on N + Growing N on silicon substrate - Silicon epitaxial layer, and in N - A field oxide layer is grown on the surface of the silicon epitaxial layer; S2, P + Field limiting ring and main junction region formation: In N - P is formed inside the silicon epitaxial layer + Field limiting ring and main junction region; S3, Helium ion implantation: Helium ions are implanted and activated in the edge area of ​​the main junction region; S4, front metallization: on P + An anode metal contact is formed on the surface of the main junction region; S5, back metallization: on N + A cathode metal contact is formed on the back side of the silicon substrate; The specific steps of growing the field oxide layer in step S1 are: A1.1、N - Epitaxial growth: on N + A layer of N is grown on the silicon substrate. - Silicon epitaxial layer; N - The silicon epitaxial layer is used to form a field limiting ring and a main junction region therein; A1.

2. Cleaning the silicon wafer surface before field oxidation: The silicon wafer formed in step A1.1 is subjected to RCA cleaning to remove impurities, dust particles, organic matter and metal ions on the surface of the silicon wafer while removing the natural silicon oxide on the surface of the silicon wafer; A1.

3. Growth of field oxide layer on silicon wafer surface: A dry-wet-dry three-step thermal oxidation method is used to grow a field oxide layer on the surface of the cleaned silicon wafer. The thickness of the formed field oxide layer is 10500Å~11500Å; The P of step S2 + The specific steps for forming the field limiting ring and the main junction region are: A2.1、P + Boron implantation lithography: Using the photolithography process, the pattern on the photolithography mask is transferred to the photoresist to form a P + Boron implantation window region; the P + The boron implantation window area is P + Field limiting ring and main junction region; A2.

2. Wet etching of field oxide layer and photoresist: + Wet etching is performed in the boron implantation window area to remove N - A field oxide layer is grown in the corresponding area on the surface of the silicon epitaxial layer, and the remaining photoresist is removed; A2.

3. Surface cleaning before ion implantation protection oxidation: Clean the surface of the silicon wafer after etching in step A2.2; A2.4, ion implantation to protect the oxide layer growth: the cleaned silicon wafer is placed in an oxidation furnace for growth. + A protective oxide layer is grown in the boron implantation window area, and the thickness of the protective oxide layer is 900Å~1100Å; A2.5, P + Boron ion implantation: + Boron ions are implanted into the boron implantation window area, and the implantation dose of boron ions is 1e15cm -2 ~6e15cm -2 , the implantation energy is 75KeV~85KeV, in N - P is formed inside the silicon epitaxial layer + N - Knot; A2.6, wet etching ion implantation protective oxide layer: remove P + Ion implantation of boron in the window area protects the oxide layer; A2.

7. Surface cleaning before ion propulsion: cleaning the surface of the silicon wafer formed after step A2.6; A2.8, ion propulsion: Place the silicon wafer cleaned in step A2.7 into a diffusion furnace for diffusion, so that P + N - The junction depth increases, and the implanted boron ions are activated to form P + Field limiting ring and P + main knot region; The specific steps of helium ion implantation in step S3 are: A3.1、N - Growth of thermal oxide layer on epitaxial layer: Dry-wet-dry three-step thermal oxidation method is adopted. - A thermal oxide layer is grown on the surface of the epitaxial layer; A3.

2. Helium injection lithography: Using the photolithography process, the pattern on the photolithography mask is transferred to the photoresist to form a helium injection window area; the helium injection window area is P + The edge region of the main junction; A3.

3. Wet etching of thermal oxide layer: Wet etching is performed in the helium injection window area to remove N - A thermal oxide layer grown in the corresponding area on the surface of the silicon epitaxial layer; A3.

4. Helium ion implantation: Helium ion implantation is performed in the helium injection window area with a helium ion implantation dose of 1e14cm -2 ~5e14cm -2 , the injection energy is 630KeV~700KeV, and local lattice damage is introduced in the helium injection window area to achieve local carrier lifetime control; A3.

5. Wet etching of photoresist: Wet etching of silicon wafers, using stripping solution to remove the remaining photoresist; A3.

6. Impurity activation, i.e. activation of the injected helium ions.

2. The method for reinforcing a single-particle burnout-resistant rectifier diode according to claim 1, characterized in that The specific steps of the front metallization in step S4 are: A4.1、N - Growth of thermal oxide layer on epitaxial layer: Dry-wet-dry three-step thermal oxidation method is adopted. - A thermal oxide layer is deposited on the surface of the epitaxial layer; A4.

2. Front metal contact window lithography: Using the photolithography process, the pattern on the photolithography mask is transferred to the photoresist to form a front metal contact window area above the P+ main junction area; A4.3, wet etching the thermal oxide layer and photoresist, wet etching the silicon wafer treated in step A4.2 to remove the thermal oxide layer deposited in the front metal contact window area, and remove the remaining photoresist with a stripping solution; A4.4, evaporating metal: performing electron beam evaporation on the silicon wafer treated in step A4.3 to deposit metal on the silicon wafer, the metal is aluminum, and the metal thickness is 4μm~6μm; A4.

5. Metal photolithography: Photolithography is performed on the silicon wafer after metal deposition to transfer the pattern on the photolithography mask to the photoresist so that the metal deposited outside the front metal contact window area can be removed in the subsequent process. A4.6, Wet etching of metal and photoresist: Remove the metal outside the metal contact window area on the front side, and use a stripping solution to remove the photoresist applied during metal lithography; A4.7 Metal alloying: Place the silicon wafer into an alloy furnace tube, and the metal part forms a metal alloy, which is used as the anode contact.

3. The method for reinforcing a single-event burnout-resistant rectifier diode according to claim 1, characterized in that The specific steps of back metallization in step S5 are: A5.

1. Surface passivation layer deposition: a passivation layer is deposited on the surface of the silicon wafer after the treatment in step S4. The thickness of the passivation layer is 1000Å~2000Å, and the passivation material is SiN; A5.

2. Surface passivation layer photolithography: The silicon wafer processed in step A5.1 is subjected to photolithography to transfer the pattern on the photolithography mask to the photoresist so as to remove the surface passivation layer above the anode metal contact area in the subsequent process; A5.

3. Wet-etch the surface passivation layer and photoresist to remove the surface passivation layer above the anode metal contact area, and use a stripping solution to remove the photoresist applied during photolithography of the surface passivation layer; A5.4, Back thinning: Thin the silicon substrate from the back to reduce the thickness of the silicon wafer to 220μm~230μm, in order to reduce the forward on-resistance of the device; A5.

5. Back metal deposition: DC plasma sputtering is performed on the back side of the silicon substrate to deposit back metal to form a back metal contact. The back metal is TiNiAg.

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