Stacked chips and stacked chip testing methods

Abstract

The present application provides a stacked chip and a test method for stacked chips, wherein the stacked chip includes multiple chips, the multiple chips include at least a first chip, the first chip includes at least one input-output interface, one end of the input-output interface is used to receive at least one group of test signals sent by a test machine, and the other ends of the multiple input-output interfaces are respectively electrically connected to the test modules of the multiple chips, wherein a group of test signals output by the input-output interface is input to the corresponding test module, and each test module is connected to at least one input-output interface, so that only one test machine is needed to input multiple groups of test signals to the input-output interface of the first chip, and multiple chips can be tested at the same time. The scheme of the present application can reduce the test cost and ensure high test efficiency, thereby solving the problem in the prior art that multiple chips in the stacked chip require multiple test machines, resulting in large resource consumption.

Description

Technical Field

[0001] The present application relates to the field of stacked chip testing, and in particular, to a stacked chip and a stacked chip testing method. Background Art

[0002] Chip testing technology is a key area of ​​the semiconductor industry. Chip testing includes wafer testing, the main purpose of which is to pick out defective chips from the wafer. During the wafer testing process, the chip needs to be tested for electrical performance to ensure that the chip on the wafer is a qualified product before packaging.

[0003] The 3D stacking platform is a technology that connects logic chips and memory chips through hybrid bonding technology to achieve near-memory computing. The platform is mainly composed of three parts: logic chip, memory chip and connection layer. Compared with a single logic (or memory) chip, the 3D stacking platform contains both logic chips and memory chips. Therefore, when conducting electrical performance testing, all the logic chips and memory chips inside need to be covered.

[0004] At present, the common test methods are independent of each other for testing logic or memory chips. They are mainly designed in the logic chip and memory chip respectively by designing test modules, using the corresponding test machine to send test stimuli through the corresponding pins to activate the test modules, thereby completing the electrical performance test of the logic chip or memory chip. The schematic diagram is shown in Figure 1 shown.

[0005] During the actual testing process, the logic chips and memory chips in the three-dimensional stacking platform need to be tested separately using corresponding test machines to ensure the integrity of the electrical performance of the three-dimensional stacking platform. In addition, the tested logic chips and memory chips cannot be automatically switched during the testing process, resulting in a low degree of automation, low test efficiency, and high test costs.

[0006] The above-mentioned testing method needs to use different testing platforms to test the logic chip and the memory chip respectively, which has low test coverage, large resource consumption and low test efficiency.

[0007] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country for those skilled in the art. Summary of the invention

[0008] The main purpose of the present application is to provide a stacked chip and a test method for the stacked chip, so as to solve the problem in the prior art that multiple chips in the stacked chip require multiple test machines, resulting in large resource consumption.

[0009] According to one aspect of an embodiment of the present invention, a stacked chip is provided, the stacked chip includes multiple chips, the multiple chips include at least a first chip, the first chip includes at least one input-output interface, one end of the input-output interface is used to receive at least one group of test signals issued by a test machine, and the other ends of the multiple input-output interfaces are respectively electrically connected to the test modules of the multiple chips, wherein a group of test signals output by the input-output interface is input into the corresponding test modules.

[0010] Optionally, each of the test modules is integrated into the chip.

[0011] Optionally, the test modules are integrated into the corresponding chips one by one, and the other end of the input / output interface is electrically connected to other test modules, which are test modules other than the test module for testing the first chip.

[0012] Optionally, each of the test modules is integrated in the first chip, and other test modules are electrically connected to the corresponding chip, and the other test modules are test modules other than the test modules for testing the first chip.

[0013] Optionally, the first chip includes a first multiplexer, the first multiplexer includes each of the input and output interfaces, the first multiplexer also includes multiple output interfaces, the output interface is connected to the other end of the input and output interface, the multiple output interfaces are respectively connected to the input ends of multiple test modules, and the first multiplexer is used to judge the test signal and send the test signal to the corresponding test module.

[0014] Optionally, the first chip also includes a second multiplexer, one end of the second multiplexer is connected to the other test modules, and the other end of the second multiplexer is connected to other chips, and the second multiplexer is used to judge the test signal received by the other test modules and send the test signal to the corresponding other chips, where the other chips are chips other than the first chip.

[0015] Optionally, the test module of the first chip is selected from at least one of the following: a BSC test module, a built-in self-test (BIST) test module, and a DFT test technology (DFT) module.

[0016] Optionally, a plurality of the chips are stacked by hybrid bonding.

[0017] According to another aspect of an embodiment of the present invention, a method for testing a stacked chip is provided, wherein the stacked chip includes a plurality of chips, and the plurality of chips include at least a first chip. The testing method includes: the first chip receives at least one group of test signals emitted by a testing machine; the first chip sends the received at least one group of test signals to a corresponding testing module to test the chip.

[0018] Optionally, when each of the test modules is integrated into the first chip, or, when each of the test modules is integrated one-to-one into the corresponding chip, after the first chip receives at least one group of test signals issued by a testing machine, the testing method includes: the first chip sends the at least one group of received test signals to the test module of the first chip to test the first chip, and / or; the first chip sends the at least one group of received test signals to other test modules to test other chips, the other test modules are the test modules other than the test module for testing the first chip, and the other chips are the chips other than the first chip.

[0019] Optionally, when each of the test modules is integrated in the first chip, after the first chip receives at least one group of test signals sent by the test machine, the testing method includes: the first chip sends the at least one group of test signals received to the test module of the first chip to test the first chip, and / or; the first chip sends the at least one group of test signals received to other test modules, the other test modules send the at least one group of test signals received to a second multiplexer, the second multiplexer sends the at least one group of test signals received to other chips to test the other chips, the other test modules are the test modules other than the test module for testing the first chip, and the other chips are the chips other than the first chip.

[0020] In the stacked chip, the stacked chip includes multiple chips, the multiple chips include at least a first chip, the first chip includes at least one input-output interface, one end of the input-output interface is used to receive at least one group of test signals sent by a test machine, and the other ends of the multiple input-output interfaces are respectively electrically connected to the test modules of the multiple chips, and each test module is connected to at least one input-output interface, so that each group of test signals can be input into the corresponding test module through the input-output interface, so that only one test machine is needed to input multiple groups of test signals to the input-output interface of the first chip, and multiple chips can be tested at the same time. Compared with the prior art of testing chips by different test machines, the solution of the present application can reduce the testing cost and ensure high testing efficiency, thereby solving the problem of the prior art that multiple chips in the stacked chip require multiple test machines, resulting in large resource consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0022] Figure 1 A schematic diagram of a chip testing method in the prior art is shown;

[0023] Figure 2 A schematic diagram of stacked chips according to an embodiment of the present application is shown;

[0024] Figure 3 A schematic diagram of stacked chips according to another embodiment of the present application is shown;

[0025] Figure 4 A schematic diagram of a stacked chip system according to an embodiment of the present application is shown;

[0026] Figure 5 A schematic diagram of a stacked chip system according to another embodiment of the present application is shown.

[0027] The above drawings include the following reference numerals:

[0028] 01. Test machine; 02. First chip; 03. First test module; 05. Second test module; 06. Second chip; 07. First multiplexer; 08. Second multiplexer; 09. Third chip; 10. Third test module. DETAILED DESCRIPTION

[0029] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0030] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0033] For the convenience of description, some nouns or terms involved in the embodiments of the present application are explained below:

[0034] Test pin: TEST PAD;

[0035] ATE machine: Automatic Test Equipment;

[0036] Design for Test (DFT);

[0037] Built-in Self Test (BIST);

[0038] Hybrid Bonding: Hybrid Bonding.

[0039] As mentioned in the background technology, multiple chips in a stacked chip in the prior art require multiple testing machines, resulting in large resource consumption. In order to solve the above problem, a typical embodiment of the present application provides a stacked chip and a stacked chip testing method.

[0040] In one embodiment of the present application, a stacked chip is provided, which includes multiple chips, and the multiple chips include at least a first chip. The first chip includes at least one input-output interface, and one end of the input-output interface is used to receive at least one group of test signals issued by a test machine, that is, when there is one test module in the first chip, the input-output interface receives a group of test signals issued by the test machine, and when there are multiple test modules in the first chip, the input-output interface receives multiple groups of test signals issued by the test machine, and the other ends of the multiple input-output interfaces are electrically connected to the test modules of the multiple chips, respectively, wherein the group of test signals output by the input-output interface is input into the corresponding test modules.

[0041] In the above-mentioned stacked chips, the plurality of the above-mentioned chips at least include a first chip, and the first chip includes a plurality of input and output interfaces, one end of the plurality of input and output interfaces is used to receive test signals sent by a test machine, and the other end of the plurality of input and output interfaces is respectively electrically connected to the test modules of the plurality of the above-mentioned chips, and each test module is connected to at least one input and output interface, so that each group of test signals can be input into the corresponding test module through the input and output interface, so that only one test machine is needed to input multiple groups of test signals to the input and output interface of the first chip, and multiple chips can be tested at the same time. Compared with the prior art of testing chips by different test machines, the scheme of the present application can reduce the testing cost and ensure high testing efficiency, thereby solving the problem that multiple chips in the chip structure in the prior art require multiple test machines, resulting in large resource consumption.

[0042] Specifically, the chip can be at least one of a die or a wafer, but is not limited thereto, and can also be any replacement that a person skilled in the art can think of. Wafer refers to a silicon wafer used to make a silicon semiconductor circuit, and a die or a chip refers to a silicon wafer obtained by dividing the wafer made with the semiconductor circuit. The specific embodiments of the present application are introduced by taking a die as an example. For example, the die can be a dynamic storage array die.

[0043] In order to facilitate testing of the above-mentioned chip and improve the integration of the chip, in another embodiment of the present application, each of the above-mentioned test modules is integrated into the above-mentioned chip.

[0044] In another embodiment of the present application, the above-mentioned test modules are integrated into the corresponding above-mentioned chips one by one, that is, one chip corresponds to one test module, and the test module is integrated in the chip, and the other end of the above-mentioned input-output interface is electrically connected to other test modules, and the above-mentioned other test modules are other above-mentioned test modules except the above-mentioned test module for testing the above-mentioned first chip. In this embodiment, the other test modules are electrically connected to the other end of the above-mentioned input-output interface, that is, the test machine sends out multiple groups of test signals, and the corresponding test signals are input into the corresponding test modules through the input-output interface, so as to test other chips.

[0045] In a specific embodiment of the present application, Figure 2 As shown, there are two chips in the stacked chip, namely a first chip 02 and a second chip 06, wherein a test module is integrated in the first chip 02, which is the first test module 03, and a test module is integrated in the second chip 06, which is the second test module 05. The input and output interface of the first chip 02 is electrically connected to the second test module 05 of the second chip 06. For the two groups of test signals input into the first chip 02 by the above-mentioned input and output interface, one group of test signals is input into the first test module 03 through the above-mentioned input and output interface, which is used to test the first chip 02, and the other group of test signals is input into the second test module 05 through the input and output interface, which is used to test the second chip 06.

[0046] In addition, it should be noted that Figure 2 As shown, the first chip 02 and the second chip 06 of the present application are electrically connected through an input-output interface, but the electrical connection between the first chip 02 and the second chip 06 is independent of each other. For example, the electrical connection for transmitting command signals and the electrical connection for transmitting data are independent.

[0047] In another embodiment of the present application, each of the above-mentioned test modules is integrated in the above-mentioned first chip, that is, the test modules corresponding to other chips are also integrated in the first chip, and the other test modules are electrically connected to the corresponding chips, and the above-mentioned other test modules are other test modules except the above-mentioned test modules of the above-mentioned first chip. In this embodiment, multiple groups of test signals sent by the test machine are input into the corresponding test modules through the input and output interface, so that multiple chips can be tested by multiple groups of test signals sent by a test machine.

[0048] The chips in the stacked chip can be connected through Cu metal wires, for example, Cu-Cu bonding is achieved through hybrid bonding technology (Hybid Bonding), so as to realize the connection between the test module and the corresponding chip; the connection between the previous chip and the next chip is mainly guaranteed by Cu-Cu bonding and the electrolyte layer connection (insulation effect) between the two chips.

[0049] In actual application, the stacked chip may be integrated with one test module or multiple test modules. When one test module is integrated in the chip, the test module may be integrated in the chip or in other chips. When there are multiple test modules in the chip, the test module may be fully integrated in the chip. Of course, the test module may be partially integrated in the chip, partially integrated in other chips, or fully integrated in other chips.

[0050] In a specific embodiment of the present application, Figure 3 As shown, the chip structure includes two chips, namely, a first chip 02 and a second chip 06, wherein the first chip 02 is integrated with two test modules, namely, a first test module 03 and a second test module 05, and the second test module 05 is electrically connected to the second chip 06. For the two groups of test signals input into the first chip 02 by the input-output interface, one group of test signals is input into the first test module 03 by the input-output interface for testing the first chip 02, and the other group of test signals is input into the second test module 05 by the input-output interface, and then input into the second chip 06 for testing the second chip 06.

[0051] In one embodiment of the present application, the first chip includes a first multiplexer, the first multiplexer includes each of the above-mentioned input and output interfaces, the first multiplexer also includes multiple output interfaces, the output interface is connected to the other end of the input and output interface, the multiple output interfaces are respectively connected to the input ends of the multiple test modules, and the first multiplexer is used to judge the test signal and send the test signal to the corresponding test module. In this embodiment, the first multiplexer includes multiple input and output interfaces and multiple output interfaces, and the multiple output interfaces are connected to the input ends of multiple test modules. When the test machine sends out a test signal, the first multiplexer makes a judgment based on the received test signal, obtains the test module corresponding to the test signal, and then sends the test signal to the corresponding test module to test the chip.

[0052] Of course, in actual application, the above-mentioned input-output interface is not limited to being an interface on the structure of the above-mentioned first chip other than the first multiplexer and the test module, and may also be an interface on the first multiplexer, or an interface on the test module. When the above-mentioned input-output interface is an interface on the structure of the above-mentioned first chip other than the first multiplexer and the test module, the test signal may be input from the input-output interface to the interface on the structure of the above-mentioned first chip other than the first multiplexer and the test module, and then input from the interface on the structure of the above-mentioned first chip other than the first multiplexer and the test module to the test module; when the above-mentioned input-output interface is an interface on the first multiplexer, the test signal may be input from the input-output interface to the first multiplexer, and then input from the first multiplexer to the test module; when the above-mentioned input-output interface is an interface on the test module, the test signal may be directly input from the input-output interface to the test module.

[0053] When the above-mentioned test modules are all integrated in the first chip, in order to efficiently send the test signals received by other test modules to the corresponding other chips, in another embodiment of the present application, the above-mentioned first chip also includes a second multiplexer, one end of the above-mentioned second multiplexer is connected to the above-mentioned other test modules, and the other end of the above-mentioned second multiplexer is connected to the other chips, and the above-mentioned second multiplexer is used to judge the above-mentioned test signals received by the above-mentioned other test modules and send the above-mentioned test signals to the corresponding other chips. The above-mentioned other chips are the above-mentioned chips other than the above-mentioned first chip.

[0054] In another embodiment of the present application, the multiple chips mentioned above also include a second chip, the first chip mentioned above is one of the logic chip and the memory chip, and the second chip mentioned above is the other of the logic chip and the memory chip, and subsequently corresponding test modules are set in the first chip and / or the second chip to test the chip.

[0055] Of course, the first chip and the second chip of the present application are not limited to the above-mentioned logic chip and memory chip, but may also be existing chip types such as analog chips.

[0056] In a specific embodiment of the present application, the external Cu metal leads of the logic chip and the memory chip are bonded by Cu-Cu bonding through hybrid bonding technology (Hybid Bonding), thereby realizing the connection between the test module and the corresponding chip; the connection between the previous chip and the next chip is mainly ensured by Cu-Cu bonding and the electrolyte layer connection (insulation effect) between the two chips.

[0057] In another embodiment of the present application, the first chip is the logic chip, and the second chip is the memory chip. Due to the limitation of the traditional computer "von Neumann" architecture, the gap between memory bandwidth and computing requirements (i.e., the "memory wall" problem) is becoming increasingly prominent. By directly stacking the logic chip and the memory chip, the memory chip can be directly accessed, which effectively solves the "memory wall" problem and achieves ultra-high energy efficiency (i.e., high bandwidth, low power consumption).

[0058] In another embodiment of the present application, the test module of the first chip is selected from at least one of the following: a BSC test module, a built-in self-test BIST test module, and a testability technology DFT module, and the chip can be tested through the test module.

[0059] Of course, in actual applications, the test module of the first chip is not limited to the BSC test module, the built-in self-test BIST test module, and the testability technology DFT module, but can also be other test modules for testing the first chip, which will not be described one by one here.

[0060] In one embodiment of the present application, the test module of the second chip is selected from at least one of the following: a BSC test module, a built-in self-test BIST test module, and a testability technology DFT module, and the chip can be tested through the test module.

[0061] Of course, in actual applications, the test module of the second chip is not limited to the BSC test module, the built-in self-test BIST test module, and the testability technology DFT module, but can also be other test modules for testing the second chip, which will not be described one by one here.

[0062] In a specific embodiment of the present application, a BSC / BIST test module may also be integrated in the above-mentioned logic chip. Since the BSC / BIST module can reuse the external test interface of the DFT module, it also supports one end of other test modules to be connected to the memory chip through Hybrid Bonding, so as to facilitate the testing of the memory chip through the test module in the logic chip.

[0063] In another embodiment of the present application, the above-mentioned stacked chip is a three-dimensional chip. The three-dimensional chip is a new chip structure formed by manufacturing different circuit units on multiple planar chips and stacking and interconnecting multiple chips in the vertical direction through silicon via interlayer vertical interconnection technology. The three-dimensional chip has the characteristics of high integration, low power consumption, high bandwidth, small area, short interconnection lines, and support for heterogeneous integration.

[0064] In another embodiment of the present application, a plurality of the above chips are stacked by hybrid bonding.

[0065] In a specific embodiment of the present application, the first chip and the second chip may be connected together by using a hybrid bonding technology.

[0066] In a typical embodiment of the present application, a test method for a stacked chip is also provided, wherein the stacked chip includes multiple chips, and the multiple chips include at least a first chip. The test method includes: the first chip receives at least one group of test signals emitted by a test machine; the first chip sends the received at least one group of test signals to a corresponding test module to test the chip.

[0067] In the test method of the stacked chip, the stacked chip includes a plurality of chips, and the plurality of chips include at least a first chip. The test method includes: for at least one group of test signals sent by the test machine, the first chip receives at least one group of test signals, and after the first chip receives at least one group of test signals, the first chip sends the received at least one group of test signals to the corresponding test module to test the chip. In this scheme, each group of test signals sent by the test machine can be sent to the corresponding test module, so that only one test machine is needed to input multiple groups of test signals to the input and output interface of the first chip, so that multiple chips can be tested at the same time. Compared with the prior art of testing chips by different test machines, the scheme of the present application can reduce the testing cost and ensure high testing efficiency, thereby solving the problem that multiple chips in the chip structure in the prior art require multiple test machines, resulting in large resource consumption.

[0068] In one implementation of the present application, when each of the above-mentioned test modules is integrated into the above-mentioned first chip, or, when each of the above-mentioned test modules is integrated one-to-one into the corresponding above-mentioned chip, after the above-mentioned first chip receives at least one group of test signals issued by the testing machine, the above-mentioned testing method includes: the above-mentioned first chip sends the at least one group of the above-mentioned test signals received to the above-mentioned test module of the above-mentioned first chip to test the above-mentioned first chip, and / or; the above-mentioned first chip sends the at least one group of the above-mentioned test signals received to other test modules to test other chips, the above-mentioned other test modules are the other above-mentioned test modules except the above-mentioned test module for testing the above-mentioned first chip, and the above-mentioned other chips are the above-mentioned chips except the above-mentioned first chip. In this embodiment, when all the above-mentioned test modules are integrated in the first chip, at least one group of test signals sent by a test machine and received by the first chip are sent to its own test module and other test modules respectively. After the other test modules receive the test signals, they are sent to the corresponding other chips. When all the test modules are integrated in the corresponding chips, the first chip sends at least one group of test signals sent by a test machine to its own test module and other test modules in other chips to test the other chips, thereby realizing the testing of multiple chips by at least one group of test signals sent by a test machine, further ensuring low testing costs and high testing efficiency.

[0069] In another embodiment of the present application, when each of the above-mentioned test modules is integrated in the above-mentioned first chip, after the above-mentioned first chip receives at least one group of test signals sent by the testing machine, the above-mentioned testing method includes: the above-mentioned first chip sends the at least one group of the above-mentioned test signals received to the above-mentioned test module of the above-mentioned first chip to test the above-mentioned first chip, and / or; the above-mentioned first chip sends the at least one group of the above-mentioned test signals received to other test modules, the above-mentioned other test modules send the at least one group of the above-mentioned test signals received to the second multiplexer, the above-mentioned second multiplexer sends the at least one group of the above-mentioned test signals received to other chips to test the above-mentioned other chips, the above-mentioned other test modules are the other above-mentioned test modules except the above-mentioned test modules for testing the above-mentioned first chip, and the above-mentioned other chips are the above-mentioned chips except the above-mentioned first chip. In this scheme, after the first chip sends at least one group of received test signals to other test modules, the other test modules send at least one group of test signals to a second multiplexer. The second multiplexer determines which test module to forward the test signal to based on the address information, specific identifier or received TEST PAD (i.e., test pin) carried in the test signal, thereby further avoiding the test signal from being mistakenly sent to an inappropriate chip and further ensuring that other chips can be tested more efficiently.

[0070] In one embodiment of the present application, a chip system is also provided, including any one of the above-mentioned chip structures; a test machine, including multiple test interfaces, the test interfaces are connected to the input and output interfaces one by one, and the above-mentioned test interfaces are connected to the input and output interfaces of the above-mentioned first chip to input at least one group of test signals to the above-mentioned input and output interfaces.

[0071] The above chip system includes any one of the above chip structures and a test machine, wherein the above chip structure includes multiple chips, the above chip includes multiple input and output interfaces, the above test machine includes multiple test interfaces, the test interfaces are connected to the input and output interfaces in a one-to-one correspondence, and each group of test signals sent by the test machine can be input into the corresponding test module through the input and output interface, so that only one test machine is needed to input multiple groups of test signals to the input and output interface of the first chip, so that multiple chips can be tested at the same time. Compared with the prior art of testing chips through different test machines, the solution of the present application can reduce the testing cost and ensure high testing efficiency, thereby solving the problem of the prior art that multiple chips in the stacked chip require multiple test machines, resulting in large resource consumption.

[0072] In a specific embodiment of the present application, the test machine can be connected to the test module in the above-mentioned chip through a test pin (TEST PAD). The number of TEST PADs may vary depending on the selected test modules, and the present application does not limit the number of TEST PADs.

[0073] Example 1

[0074] In a specific embodiment of the present application, Figure 4As shown, the stacked chip system includes: a test machine 01, a first chip 02, and a second chip 06, wherein the first chip 02 is a logic chip, and the second chip 06 is a memory chip. The logic chip includes two test modules, namely a first test module 03 and a second test module 05, namely a BIST test module and a DFT test module, and a first multiplexer 07, namely a MUX module. The DFT test module in the logic chip is electrically connected to the memory chip. The test machine 01 can test the memory chip through the external interface of the DFT test module. The specific test process is as follows: the test machine 01 sends two groups of The MUX module judges the test signal according to the received test signal, obtains the test module corresponding to the test signal, inputs one group of test signals to the BIST test module (i.e., the first test module 03) in the logic chip (the first chip 02) for testing the logic chip, and inputs another group of test signals to the DFT test module (i.e., the second test module 05), which is then input to the memory chip by the DFT test module for testing the memory chip (i.e., the second chip 06). That is to say, in the test process, only one test machine 01 needs to send multiple groups of test signals to complete the test of the logic chip and the memory chip.

[0075] Example 2

[0076] In another specific embodiment of the present application, Figure 5As shown, the stacked chip system includes: a test machine 01, a first chip 02, a second chip 06, a third chip 09, a first multiplexer 07 and a second multiplexer 08, wherein the first chip 02 integrates three test modules, namely a first test module 03, a second test module 05 and a third test module 10, that is, the first test module 03 is used to test the first chip 02, the second test module 05 is used to test the second chip 06, and the third test module 10 is used to test the third chip 09. The second multiplexer 08 is located in the first chip 02, one end of the second multiplexer 08 is electrically connected to the second test module 05 and the third test module 10 respectively, and the other end of the second multiplexer 08 is electrically connected to the second chip 06 and the third chip 09 respectively. The process is as follows: for the three groups of test signals sent by the test machine 01, the first multiplexer 07, that is, the MUX module, makes a judgment based on the received test signals to obtain the test module corresponding to the test signal, that is, the first group of test signals is sent to the first test module 03 for testing the first chip, and the second group of test signals and the third group of test signals are sent to the second test module 05 and the third test module 10 respectively. The second test module 05 and the third test module 10 send the received test signals to the second multiplexer 08 respectively. The second multiplexer 08 judges the two groups of test signals received. The second multiplexer 08 sends one group of test signals to the second chip 06 for testing the second chip 06, and sends the other group of test signals to the third chip 09 for testing the third chip 09.

[0077] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0078] 1) In the stacked chip of the present application, the stacked chip includes multiple chips, the multiple chips include at least a first chip, the first chip includes at least one input-output interface, one end of the input-output interface is used to receive at least one group of test signals sent by a test machine, the other ends of the multiple input-output interfaces are respectively electrically connected to the test modules of the multiple chips, and each test module is connected to at least one input-output interface, so that each group of test signals can be input into the corresponding test module through the input-output interface, so that only one test machine is needed to input multiple groups of test signals to the input-output interface of the first chip, and multiple chips can be tested at the same time. Compared with the prior art of testing chips by different test machines, the solution of the present application can reduce the testing cost and ensure high testing efficiency, thereby solving the problem of large resource consumption caused by the need for multiple test machines for multiple chips in the stacked chip in the prior art.

[0079] 2) In the test method of the stacked chip of the present application, the stacked chip includes a plurality of chips, and the plurality of the chips include at least a first chip. The test method includes: for at least one group of test signals sent by the test machine, the first chip receives at least one group of test signals, and after the first chip receives at least one group of test signals, the first chip sends the received at least one group of test signals to the corresponding test module to test the chip. In this scheme, each group of test signals sent by the test machine can be sent to the corresponding test module, so that only one test machine is needed to input multiple groups of test signals to the input and output interface of the first chip, so that multiple chips can be tested at the same time. Compared with the prior art of testing chips by different test machines, the scheme of the present application can reduce the testing cost and ensure high testing efficiency, thereby solving the problem of large resource consumption caused by the need for multiple test machines for multiple chips in the stacked chip in the prior art.

[0080] 3) The stacked chip system of the present application includes any of the above-mentioned stacked chips and a test machine, wherein the above-mentioned stacked chip includes multiple chips, the above-mentioned chip includes multiple input and output interfaces, the above-mentioned test machine includes multiple test interfaces, the test interfaces are connected to the input and output interfaces in a one-to-one correspondence, and each group of test signals sent by the test machine can be input into the corresponding test module through the input and output interface, so that only one test machine is needed to input multiple groups of test signals to the input and output interface of the first chip, so that multiple chips can be tested at the same time. Compared with the prior art of testing chips through different test machines, the solution of the present application can reduce the testing cost and ensure high testing efficiency, thereby solving the problem of the prior art that multiple chips in the stacked chip require multiple test machines, resulting in large resource consumption.

[0081] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A stacked chip, characterized in that: The stacked chip includes a plurality of chips, the plurality of chips include at least a first chip, the first chip includes a plurality of input and output interfaces, one end of the input and output interfaces is used to receive a plurality of groups of test signals sent by a test machine, and the other ends of the plurality of input and output interfaces are respectively electrically connected to the test modules of the plurality of chips, wherein a group of the test signals output by the input and output interfaces are input into the corresponding test modules; Each of the test modules is integrated in the chip; Each of the test modules is integrated in the first chip, and other test modules are electrically connected to the corresponding chip, and the other test modules are test modules other than the test module for testing the first chip; The first chip includes a first multiplexer, the first multiplexer includes the input and output interfaces, the first multiplexer also includes a plurality of output interfaces, the output interface is connected to the other end of the input and output interface, the plurality of output interfaces are respectively connected to the input ends of the plurality of test modules, the first multiplexer is used to judge the test signal and send the test signal to the corresponding test module; The first chip further includes a second multiplexer, one end of the second multiplexer is connected to the other test modules, and the other end of the second multiplexer is connected to other chips, the second multiplexer is used to judge the test signal received by the other test modules, and send the test signal to the corresponding other chip, the other chip is the chip other than the first chip; Each group of the test signals is input into the corresponding test module through the input / output interface, so that only one test machine is needed to input multiple groups of the test signals into the input / output interface of the first chip, and multiple chips are tested at the same time.

2. The stacked chip according to claim 1, characterized in that: The test module of the first chip is selected from at least one of the following: a BSC test module, a built-in self-test (BIST) test module, and a DFT testability technology (DFT) module.

3. The stacked chip according to claim 1, characterized in that: The multiple chips are stacked in a hybrid bonding manner.

4. A test method for stacked chips according to any one of claims 1 to 3, characterized in that: The stacked chip includes a plurality of chips, the plurality of chips include at least a first chip, and the testing method includes: The first chip receives at least one set of test signals sent by the test machine; The first chip sends the received at least one group of test signals to a corresponding test module to test the chip; In the case where each of the test modules is integrated into the first chip, After the first chip receives at least one set of test signals sent by a test machine, the test method includes: The first chip sends the received at least one group of test signals to the test module of the first chip to test the first chip; The first chip sends at least one group of the received test signals to other test modules, and the other test modules send at least one group of the received test signals to a second multiplexer. The second multiplexer sends at least one group of the received test signals to other chips to test the other chips. The other test modules are the test modules other than the test module for testing the first chip, and the other chips are the chips other than the first chip.

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