Chip screening method, device and chip screening equipment

Abstract

The present application provides a chip screening method, device and screening equipment, the method comprising: performing board-level testing on multiple sample chips, determining a sample chip that works normally at an extreme temperature and whose junction temperature value is within a first predetermined range as a first target chip, obtaining static current values ​​and oscillation frequency values ​​of multiple first target chips, and determining a static current threshold and an oscillation frequency threshold; performing FT testing on the first target chip, determining a first target chip whose junction temperature rise value within a predetermined time is within a second predetermined range as a second target chip; performing board-level testing on the second target chip, determining a second target chip that works normally at an extreme temperature as a third target chip, obtaining a junction temperature rise value of the third target chip in the FT test, and obtaining a junction temperature rise threshold; screening the chips to be tested according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold, thereby solving the problem of low chip yield caused by low power consumption limit of the screening chip.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip screening method, device and screening equipment. Background Art

[0002] As the power consumption problem faced by chips becomes more and more serious, excessive chip power consumption is one of the main reasons for the loss of chip mass production yield. Between different wafers and different batches, the range of variation of MOSFETs parameters is relatively large due to external factors such as doping, etching, and temperature. In order to reduce the difficulty of design, it is necessary to limit the performance of the device within a certain range and scrap the chips that exceed this range. Generally, the screening chip in the mass production process mainly limits the power consumption from two aspects, one of which is the upper limit of the static current at room temperature, and the other is the OSC oscillation circuit loop integrated on the chip to monitor the process speed. Based on these two tests alone, some chips will have high-temperature reversal near the power consumption boundary value, that is, some chips within the power consumption limit range have abnormal high-temperature power consumption, which is specifically manifested as the junction temperature of the chip exceeding the preset value or the upper limit of the chip junction temperature specified by the manufacturer when the chip is working, and some chips outside the power consumption limit range have normal high-temperature performance. If in order to prevent chips with high-temperature reversal within the power consumption limit from entering the market, it is necessary to continue to reduce the power consumption limit, which will cause a huge loss in the yield of mass-produced chips.

[0003] Therefore, a new chip screening method is urgently needed to solve the problem of low chip yield caused by low power consumption limit during chip mass production screening. Summary of the invention

[0004] The main purpose of the present application is to provide a chip screening method, device and screening equipment to solve the problem of low chip yield caused by low power consumption limit of the screening method in the prior art.

[0005] According to one aspect of an embodiment of the present invention, a chip screening method is provided, the screening method comprising: performing a board-level test on a plurality of sample chips, the ambient temperature of the board-level test being an extreme temperature, determining the sample chip that meets a first predetermined condition as a first target chip, obtaining static current values ​​and oscillation frequency values ​​of the plurality of first target chips, and determining a static current threshold and an oscillation frequency threshold, the extreme temperature being the highest ambient temperature of the application scenario of the sample chip, the first predetermined condition being that the test chip works normally and the junction temperature value is within a first predetermined range; performing an FT test on the first target chip, determining the first target chip that meets a second predetermined condition as a second target chip, the second predetermined condition being that the junction temperature rise value of the test chip within a predetermined time is within a second predetermined range; performing a board-level test on the second target chip, the ambient temperature of the board-level test being an extreme temperature, determining the second target chip that meets the first predetermined condition and the second predetermined condition as a third target chip, obtaining the junction temperature rise value of the third target chip in the FT test, and determining a junction temperature rise threshold; screening the chips to be tested according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold, the chips to be tested and the sample chips are chips of the same model.

[0006] Optionally, before performing FT testing on the first target chip and determining the first target chip that meets the second predetermined condition as the second target chip, the method further includes: performing board-level testing on multiple first target chips, the ambient temperature of the board-level testing is an extreme temperature, and when the junction temperature value of the first target chip is detected to be the predetermined temperature, the junction temperature rise value of the first target chip within the predetermined time is obtained to obtain a first junction temperature rise value; and determining the second predetermined range based on the first junction temperature rise value.

[0007] Optionally, an FT test is performed on the first target chip, and the first target chip that meets a second predetermined condition is determined as a second target chip, including: when the test temperature is a set temperature and the test excitation is a set test excitation, detecting the junction temperature rise value of the first target chip at the predetermined time to obtain a second junction temperature rise value, the test temperature being the ambient temperature for performing the FT test on the first target chip, and the test excitation being the excitation for performing the FT test on the first target chip; adjusting the set temperature and the set test excitation until the second target chip is obtained.

[0008] Optionally, the chip to be tested is screened according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold, including: when the ambient temperature is the production temperature, obtaining the static current value of the chip to be tested and the oscillation frequency value of the oscillation circuit of the chip to be tested to obtain a target static current value and a target oscillation frequency value, and the production temperature is the temperature of the environment in which the chip to be tested is produced; when the junction temperature value of the chip to be tested is the predetermined temperature, detecting the junction temperature rise value of the chip to be tested within the predetermined time to obtain a target junction temperature rise value; when the target static current value is less than or equal to the static current threshold, the target oscillation frequency value is less than or equal to the oscillation frequency threshold, and the target junction temperature rise value is less than or equal to the junction temperature rise threshold, determining that the chip to be tested is qualified.

[0009] Optionally, the predetermined temperature is between 110°C and 120°C.

[0010] Optionally, the predetermined time is greater than or equal to 100 ms.

[0011] Optionally, the first predetermined range is 115°C to 125°C.

[0012] Optionally, the minimum value of the second predetermined range is the first temperature rise value, the maximum value of the second predetermined range is the second temperature rise value, the first temperature rise value is 70% to 90% of the first junction temperature rise value, and the second temperature rise value is 110% to 130% of the first junction temperature rise value.

[0013] According to another aspect of an embodiment of the present invention, a chip screening device is provided, the device comprising: a first test unit, used to perform board-level testing on a plurality of sample chips, the ambient temperature of the board-level testing being a limit temperature, the sample chip that meets a first predetermined condition being determined as a first target chip, static current values ​​and oscillation frequency values ​​of the plurality of first target chips being obtained, and a static current threshold and an oscillation frequency threshold being determined, the limit temperature being the highest ambient temperature of an application scenario of the sample chip, the first predetermined condition being that the test chip is working normally and the junction temperature value is within a first predetermined range; a second test unit, used to perform FT testing on the first target chip, and to determine all the chips that meet the second predetermined condition The first target chip is determined as the second target chip, and the second predetermined condition is that the junction temperature rise value of the test chip within a predetermined time is within a second predetermined range; a third test unit is used to perform board-level testing on the second target chip, and the ambient temperature of the board-level test is the extreme temperature. The second target chip that meets the first predetermined condition and the second predetermined condition is determined as the third target chip, and the junction temperature rise value of the third target chip in the FT test is obtained to determine the junction temperature rise threshold; a judgment unit is used to screen the chip to be tested according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold, and the chip to be tested and the sample chip are chips of the same model.

[0014] According to another aspect of the embodiments of the present invention, a screening device is provided, comprising a processor and a memory, wherein the processor is used to run a program, wherein the program executes any one of the above-mentioned screening methods when running.

[0015] In an embodiment of the present invention, the chip screening method performs board-level testing on multiple sample chips at extreme temperatures, selects a chip that can work normally at the extreme temperature and whose junction temperature is within a first predetermined range, namely, a first target chip, obtains static current values ​​and oscillation frequency values ​​of multiple first target chips, and obtains a static current threshold and an oscillation frequency threshold; then performs FT testing on multiple first target chips, selects a chip whose junction temperature rise within a predetermined time is within a second predetermined range, and determines it as a second target chip; then performs board-level testing on the second target chip at extreme temperatures, and selects a chip that can work normally at the extreme temperature and whose junction temperature is within a first predetermined range. A second target chip whose value is within the first predetermined range and whose junction temperature rise value within the predetermined time is within the second predetermined range is determined as the third target chip, and the junction temperature rise value of the third target chip in the above FT test is obtained to obtain the junction temperature rise threshold. Screening is performed through three screening conditions: static current threshold, oscillation frequency threshold and junction temperature rise threshold, so that high-temperature reversal phenomenon can be avoided in chips that meet the power consumption limit conditions, so that there is no need to reduce the power consumption limit, that is, there is no need to reduce the static current threshold and the oscillation frequency threshold, thereby improving the chip yield and solving the problem of low chip yield caused by low power consumption limit of the screening method in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A flow chart of a chip screening method according to an embodiment of the present application is shown;

[0018] Figure 2 A schematic diagram of a chip screening device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0020] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0021] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0023] For the convenience of description, some nouns or terms involved in the embodiments of the present application are explained below:

[0024] Board-level testing is mainly used for functional testing. It uses PCB board + chip to build a "simulated" chip working environment, bring out all the interfaces of the chip, test the function of the chip, or see if the chip can work normally in various harsh environments. The equipment that needs to be applied is mainly instruments and meters, and the main thing that needs to be made is the EVB evaluation board.

[0025] CP test: The full name in English is Circuit Probing\Chip Probing, also known as wafer test. The test object is each die in the whole wafer. The purpose is to ensure that each die in the whole wafer can basically meet the characteristics of the device or the design specification, usually including voltage, current, timing and function verification.

[0026] FT test: The full name of FT test is Final Test, which is the last interception before the chip leaves the factory. The test object is the packaged chip. FT test is generally divided into two steps: 1) automatic test equipment; 2) system level test.

[0027] As mentioned in the background technology, in the screening method in the prior art, a high-temperature reversal phenomenon occurs within the power consumption limit range, resulting in the need to lower the power consumption limit, thereby causing low chip yield. In order to solve the above problem, the present application provides a chip screening method, device and screening equipment.

[0028] According to an embodiment of the present application, a chip screening method is provided.

[0029] Figure 1 1 is a flow chart of a chip screening method according to an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0030] Step S101, performing board-level testing on multiple sample chips, the ambient temperature of the board-level testing is the limit temperature, determining the sample chip that meets the first predetermined condition as the first target chip, obtaining static current values ​​and oscillation frequency values ​​of the multiple first target chips, and determining the static current threshold and oscillation frequency threshold, the limit temperature is the highest ambient temperature of the application scenario of the sample chip, and the first predetermined condition is that the test chip works normally and the junction temperature value is within the first predetermined range;

[0031] Step S102, performing an FT test on the first target chip, and determining the first target chip that meets a second predetermined condition as a second target chip, wherein the second predetermined condition is that a junction temperature rise value of the test chip within a predetermined time is within a second predetermined range;

[0032] Step S103, performing a board-level test on the second target chip, wherein the ambient temperature of the board-level test is the limit temperature, determining the second target chip that meets the first predetermined condition and the second predetermined condition as the third target chip, obtaining the junction temperature rise value of the third target chip in the FT test, and determining the junction temperature rise threshold;

[0033] Step S104 , screening the chips to be tested according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold, wherein the chips to be tested and the sample chips are chips of the same model.

[0034] The screening method performs board-level testing on multiple sample chips at an extreme temperature, selects a chip that can work normally at the extreme temperature and whose junction temperature value is within a first predetermined range, namely, a first target chip, obtains static current values ​​and oscillation frequency values ​​of multiple first target chips, and obtains a static current threshold value and an oscillation frequency threshold value; then performs FT testing on multiple first target chips, selects a chip whose junction temperature rise value within a predetermined time is within a second predetermined range, and determines it as a second target chip; then performs board-level testing on the second target chip at an extreme temperature, determines a second target chip that can work normally at the extreme temperature, whose junction temperature value is within the first predetermined range, and whose junction temperature rise value within the predetermined time is within the second predetermined range, as a third target chip, obtains the junction temperature rise value of the third target chip in the above FT test, and obtains a junction temperature rise threshold value; screening is performed by using three screening conditions, namely, static current threshold value, oscillation frequency threshold value, and junction temperature rise threshold value, so that high-temperature reversal phenomenon can be avoided in chips that meet power consumption limit conditions, so that there is no need to reduce power consumption limit, namely, there is no need to reduce static current threshold value and oscillation frequency threshold value, thereby improving chip yield, and solving the problem of low chip yield caused by low power consumption limit in the screening method in the prior art.

[0035] Specifically, because the static current value and the oscillation frequency value are obtained in the CP test phase, after the first target chip is obtained by the board-level test at the extreme temperature, the static current value and the oscillation frequency value of these first target chips are directly read through OTP, and the static current threshold and the oscillation frequency threshold can be determined according to the static current value and the oscillation frequency value of these first target chips. In a specific embodiment, when there are multiple first target chips, the static current threshold can be the static current value of any first target chip, or the average value or maximum value of the static current values ​​of multiple first target chips, the oscillation frequency threshold can be the oscillation frequency value of the oscillation circuit of any first target chip, or the average value or maximum value of the oscillation frequency values ​​of the oscillation circuit of multiple first target chips, and when there are multiple third target chips, the junction temperature rise threshold can be the junction temperature rise value of any third target chip in the FT test, or the average value or maximum value of the junction temperature rise values ​​of multiple third target chips in the FT test.

[0036] Preferably, the quiescent current threshold is the maximum value of the quiescent current values ​​of the plurality of the first target chips, the oscillation frequency threshold is the maximum value of the oscillation frequency values ​​of the oscillation circuits of the plurality of the first target chips, and the junction temperature rise threshold is the maximum value of the junction temperature rise values ​​of the plurality of third target chips in the FT test. Specifically, there are a plurality of the first target chips and the third target chips, the quiescent current threshold and the oscillation frequency threshold are both the maximum values ​​of the quiescent current and the oscillation frequency of the plurality of the first target chips, and the junction temperature rise threshold is the maximum value of the junction temperature rise values ​​of the plurality of third target chips in the FT test, so as to further improve the chip yield.

[0037] It should also be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be executed in an order different from that shown here.

[0038] In one embodiment of the present application, before performing FT testing on the above-mentioned first target chip and determining the above-mentioned first target chip that meets the second predetermined condition as the second target chip, the above-mentioned method also includes: performing board-level testing on multiple above-mentioned first target chips, the ambient temperature of the above-mentioned board-level testing is the extreme temperature, and when the junction temperature value of the above-mentioned first target chip is detected to be the above-mentioned predetermined temperature, the junction temperature rise value of the above-mentioned first target chip within the above-mentioned predetermined time is obtained to obtain a first junction temperature rise value; and determining the above-mentioned second predetermined range according to the above-mentioned first junction temperature rise value.

[0039] Specifically, the junction temperature rise value of the first target chip within the predetermined time is detected to obtain a first junction temperature rise value, and the appropriate second predetermined range is determined based on the first junction temperature rise value.

[0040] In one embodiment of the present application, an FT test is performed on the above-mentioned first target chip, and the above-mentioned first target chip that meets the second predetermined condition is determined as the second target chip, including: when the test temperature is a set temperature and the test excitation is a set test excitation, detecting the junction temperature rise value of the above-mentioned first target chip at the above-mentioned predetermined time to obtain a second junction temperature rise value, the above-mentioned test temperature is the ambient temperature for performing the above-mentioned FT test on the above-mentioned first target chip, and the above-mentioned test excitation is the excitation for performing the above-mentioned FT test on the above-mentioned first target chip; adjusting the above-mentioned set temperature and the above-mentioned set test excitation until the above-mentioned second target chip is obtained.

[0041] Specifically, by continuously adjusting the set test temperature and the set test excitation in a cyclic calibration manner, the second junction temperature rise value is continuously approached to the second predetermined range until a chip whose second junction temperature rise value is within the second predetermined range is screened out, i.e., the second target chip. The test excitation is the test information input to the chip to be tested in the FT test. Different test information can make the chip operate in different working states.

[0042] In one embodiment of the present application, the chips to be tested are screened according to the above-mentioned static current threshold, the above-mentioned oscillation frequency threshold and the above-mentioned junction temperature rise threshold, including: when the above-mentioned ambient temperature is the production temperature, obtaining the static current value of the above-mentioned chip to be tested and the oscillation frequency value of the oscillation circuit of the above-mentioned chip to be tested, and obtaining the target static current value and the target oscillation frequency value, and the above-mentioned production temperature is the temperature of the environment in which the above-mentioned chip to be tested is produced; when the junction temperature value of the above-mentioned chip to be tested is the above-mentioned predetermined temperature, detecting the junction temperature rise value of the above-mentioned chip to be tested within the above-mentioned predetermined time, and obtaining the target junction temperature rise value; when the above-mentioned target static current value is less than or equal to the above-mentioned static current threshold, the above-mentioned target oscillation frequency value is less than or equal to the above-mentioned oscillation frequency threshold and the above-mentioned target junction temperature rise value is less than or equal to the above-mentioned junction temperature rise threshold, it is determined that the above-mentioned chip to be tested is qualified.

[0043] Specifically, the static current of the chip to be tested and the oscillation frequency of the oscillation circuit of the chip to be tested, as well as the junction temperature rise value within the predetermined time at a predetermined temperature are detected to obtain the target static current, target oscillation frequency and target junction temperature rise value, and screening is performed through the three screening conditions of static current threshold, oscillation frequency threshold and junction temperature rise threshold. That is, when the chip to be tested meets the conditions that the target static current is less than or equal to the static current threshold, the target oscillation frequency is less than or equal to the oscillation frequency threshold and the target junction temperature rise value is less than or equal to the junction temperature rise threshold, the chip to be tested is qualified, and the high-temperature reversal phenomenon of the chip that meets the power consumption limit condition can be avoided, so that there is no need to reduce the power consumption limit, that is, there is no need to reduce the static current threshold and the oscillation frequency threshold, thereby improving the chip yield.

[0044] In one embodiment of the present application, the predetermined temperature is between 110°C and 120°C.

[0045] Specifically, the upper limit of the junction temperature at which the chip can work normally is 125°C. The above-mentioned predetermined temperature is set within the above-mentioned range, and a certain junction temperature rise space is reserved to avoid the chip junction temperature exceeding the upper limit and being damaged during the detection of the junction temperature rise value, and to make it possible for the chip junction temperature to have a high temperature reversal phenomenon after reaching the predetermined temperature. Preferably, the predetermined temperature can be set to 110°C. The second predetermined range is set by the junction temperature rise value of the chip junction temperature reaching the predetermined temperature detection time, so as to screen out the second target chip according to the second predetermined range, so that the junction temperature rise threshold obtained by detecting the second target chip can screen out the chip that may have a high temperature reversal phenomenon, thereby ensuring the quality of the chip.

[0046] In an embodiment of the present application, the predetermined time is greater than or equal to 100 ms.

[0047] Specifically, because the FT test is expensive, in order to save costs, the scheduled time can be set to 100ms. Of course, the longer the scheduled time, the smaller the error in the obtained junction temperature rise value. The scheduled time can be greater than 100ms to further improve the yield of the screen.

[0048] In an embodiment of the present application, the first predetermined range is 115°C to 125°C.

[0049] Specifically, since the upper limit of the junction temperature for which the chip can work normally is 125°C, the first predetermined range is set to 115°C to 125°C, so that the sample chips that work normally at the extreme temperature and whose junction temperature values ​​are within the above-mentioned first predetermined range can be screened out as the first target chip, thereby improving the accuracy of the measurement of the junction temperature rise threshold and further improving the yield.

[0050] In one embodiment of the present application, the minimum value of the above-mentioned second predetermined range is the first temperature rise value, the maximum value of the above-mentioned second predetermined range is the second temperature rise value, the above-mentioned first temperature rise value is between 70% and 90% of the above-mentioned first junction temperature rise value, and the above-mentioned second temperature rise value is between 110% and 130% of the above-mentioned first junction temperature rise value.

[0051] Specifically, the above-mentioned first temperature rise value and the above-mentioned second temperature rise value can be selected according to actual conditions. Preferably, the first temperature rise value is set to 80% of the first junction temperature rise value, and the second temperature rise value is set to 120% of the first junction temperature rise value. This is because the upper limit of the junction temperature for the normal operation of the chip is 125°C, and the predetermined temperature is set between 110°C and 120°C. Too high or too low may cause inaccurate testing, so the second predetermined range is set to be closer to the first junction temperature rise value to improve the yield of chip mass production.

[0052] The present application also provides a chip screening device. It should be noted that the chip screening device of the present application can be used to perform the chip screening method provided in the present application. The chip screening device provided in the present application is introduced below.

[0053] Figure 2 Schematic diagram of a chip screening device according to an embodiment of the present application. Figure 2 As shown, the device comprises:

[0054] The first test unit 10 is used to perform board-level testing on multiple sample chips, the ambient temperature of the board-level testing is the limit temperature, the sample chip that meets the first predetermined condition is determined as the first target chip, the static current value and the oscillation frequency value of the multiple first target chips are obtained, and the static current threshold value and the oscillation frequency threshold value are determined, the limit temperature is the highest ambient temperature of the application scenario of the sample chip, and the first predetermined condition is that the test chip works normally and the junction temperature value is within the first predetermined range;

[0055] The second test unit 20 is used to perform FT test on the first target chip, and determine the first target chip that meets the second predetermined condition as the second target chip, wherein the second predetermined condition is that the junction temperature rise value of the test chip within a predetermined time is within a second predetermined range;

[0056] The third test unit 30 is used to perform a board-level test on the second target chip, wherein the ambient temperature of the board-level test is the limit temperature, and the second target chip that meets the first predetermined condition and the second predetermined condition is determined as the third target chip, and the junction temperature rise value of the third target chip in the FT test is obtained to determine the junction temperature rise threshold value;

[0057] The judgment unit 40 is used to screen the chips to be tested according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold, and the chips to be tested and the sample chips are chips of the same model.

[0058] The screening device performs board-level testing on multiple sample chips at an extreme temperature, selects a chip that can work normally at the extreme temperature and whose junction temperature value is within a first predetermined range, namely, a first target chip, obtains static current values ​​and oscillation frequency values ​​of multiple first target chips, and obtains a static current threshold value and an oscillation frequency threshold value; then performs FT testing on multiple first target chips, selects a chip whose junction temperature rise value within a predetermined time is within a second predetermined range, and determines it as a second target chip; then performs board-level testing on the second target chip at an extreme temperature, determines a second target chip that can work normally at the extreme temperature, whose junction temperature value is within the first predetermined range, and whose junction temperature rise value within the predetermined time is within the second predetermined range, as a third target chip, obtains the junction temperature rise value of the third target chip in the above FT test, and obtains a junction temperature rise threshold value; screening is performed by using three screening conditions, namely, static current threshold value, oscillation frequency threshold value, and junction temperature rise threshold value, so that high-temperature reversal phenomenon can be avoided in chips that meet the power consumption limit condition, so that there is no need to reduce the power consumption limit, that is, there is no need to reduce the static current threshold value and the oscillation frequency threshold value, thereby improving the chip yield, and solving the problem of low chip yield caused by low power consumption limit in the screening method in the prior art.

[0059] In an embodiment of the present application, the above-mentioned device also includes a fourth testing unit, and the above-mentioned fourth testing unit includes a first detection module and a first determination module.

[0060] The first detection module is used to perform board-level testing on the multiple first target chips mentioned above. The ambient temperature of the board-level testing is the extreme temperature. When the junction temperature value of the first target chip is detected to be the predetermined temperature, the junction temperature rise value of the first target chip within the predetermined time is obtained to obtain the first junction temperature rise value. The first determination module is used to determine the second predetermined range according to the first junction temperature rise value.

[0061] In an embodiment of the present application, the second testing unit further includes a second detection module and an adjustment module.

[0062] The second detection module is used to detect the junction temperature rise value of the above-mentioned first target chip at the above-mentioned predetermined time when the test temperature is the set temperature and the test excitation is the set test excitation, so as to obtain the second junction temperature rise value, the above-mentioned test temperature is the ambient temperature for performing the above-mentioned FT test on the above-mentioned first target chip, and the above-mentioned test excitation is the excitation for performing the above-mentioned FT test on the above-mentioned first target chip; the adjustment module is used to adjust the above-mentioned set temperature and the above-mentioned set test excitation until the above-mentioned second target chip is obtained.

[0063] In an embodiment of the present application, the above-mentioned judgment unit includes a third detection module, a fourth detection module and a second determination module.

[0064] The third detection module is used to obtain the static current value of the above-mentioned chip to be tested and the oscillation frequency value of the oscillation circuit of the above-mentioned chip to be tested when the above-mentioned ambient temperature is the production temperature, and obtain the target static current value and the target oscillation frequency value. The above-mentioned production temperature is the temperature of the environment in which the above-mentioned chip to be tested is in production operation.

[0065] The fourth detection module is used to detect the junction temperature rise value of the above-mentioned chip to be tested within the above-mentioned predetermined time when the junction temperature value of the above-mentioned chip to be tested is the above-mentioned predetermined temperature, so as to obtain the target junction temperature rise value.

[0066] The second determination module is used to determine that the chip to be tested is qualified when the target static current value is less than or equal to the static current threshold, the target oscillation frequency value is less than or equal to the oscillation frequency threshold, and the target junction temperature rise value is less than or equal to the junction temperature rise threshold.

[0067] In one embodiment of the present application, the predetermined temperature is between 110°C and 120°C.

[0068] In an embodiment of the present application, the predetermined time is greater than or equal to 100 ms.

[0069] In one embodiment of the present application, the minimum value of the above-mentioned second predetermined range is the first temperature rise value, the maximum value of the above-mentioned second predetermined range is the second temperature rise value, the above-mentioned first temperature rise value is between 70% and 90% of the above-mentioned first junction temperature rise value, and the above-mentioned second temperature rise value is between 110% and 130% of the above-mentioned first junction temperature rise value.

[0070] In an embodiment of the present application, the first predetermined range is 115°C to 125°C.

[0071] The chip screening device includes a processor and a memory. The first test unit 10, the second test unit 20, the third test unit 30 and the judgment unit 40 are all stored in the memory as program units. The processor executes the program units stored in the memory to realize corresponding functions.

[0072] The processor includes a kernel, which retrieves the corresponding program unit from the memory. One or more kernels can be set, and the problem of low chip yield caused by low power consumption limit of the screening method in the prior art can be solved by adjusting kernel parameters.

[0073] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0074] An embodiment of the present invention provides a sieving device, which includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, any one of the above sieving methods is implemented:

[0075] The screening device in this article can be an electronic device such as a server, PC, PAD, mobile phone, etc.

[0076] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0077] In order to make the technical scheme and technical effects of the present application more clearly understood by those skilled in the art, the present invention will be described below in conjunction with specific embodiments.

[0078] Example 1

[0079] The chip to be tested is required to work normally below 50°C, that is, the limit temperature is 50°C. The chip screening method of this embodiment includes the following steps:

[0080] Step 1: Perform board-level testing on multiple sample chips at an ambient temperature of 50°C, record the sample chips that can work normally at 50°C and whose junction temperature values ​​are within a first predetermined range as first target chips, obtain static current values ​​and oscillation frequency values ​​of multiple first target chips, take the maximum value of multiple static current values ​​as the static current threshold, and take the maximum value of multiple oscillation frequency values ​​as the oscillation frequency threshold;

[0081] Step 2: Using the CPU to monitor the temperature sensor inside the chip, the junction temperature rise value of the first target chip at a predetermined temperature of 110° C. and a predetermined time of 100 ms is tested to obtain a first junction temperature rise value;

[0082] Step 3: Performing an FT test on the first target chip, detecting a junction temperature rise value of the first target chip within a predetermined time of 100ms by using a temperature sensor inside the chip in the FT test, and obtaining a second junction temperature rise value;

[0083] Step 4: Change the set temperature of the FT test and set the test stimulus so that the temperature rise value at the second junction temperature approaches the temperature rise value at the first junction temperature;

[0084] Step 5: Repeat step 4 until a first target chip whose second junction temperature rise value is between 80% and 120% of the first junction temperature rise value is screened out to obtain a second target chip;

[0085] Step 6: Perform board-level tests on multiple second target chips at an ambient temperature of 50°C, detect the junction temperature value and the third junction temperature rise value within a predetermined time of 100ms, and record the second target chip that can work normally at 50°C, whose junction temperature value is within the first predetermined range, and whose third junction temperature rise value is between 80% and 120% of the first junction temperature rise value as the third target chip, obtain the second junction temperature rise values ​​of multiple third target chips, and take the maximum value as the junction temperature rise threshold;

[0086] Step 7: Finally, the quiescent current threshold, the oscillation frequency threshold and the junction temperature rise threshold are used as upper limits of screening conditions to screen the chips to be tested.

[0087] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the above-mentioned units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0088] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0089] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0090] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a computer-readable storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present invention. The aforementioned computer-readable storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0091] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0092] The screening method, screening device, and screening equipment of the present application perform board-level testing on multiple sample chips, select a chip from the sample chips that can work normally at the maximum ambient temperature of the application scenario and whose junction temperature value is within a first predetermined range through an extreme temperature test, i.e., a first target chip, and detect the static current and the corresponding oscillation frequency of the first target chip at the extreme temperature to obtain a static current threshold and an oscillation frequency threshold, then perform an FT test on the first target chip, select a first target chip whose junction temperature rise value is within a second predetermined range within a predetermined time during the above-mentioned FT test, obtain a second target chip, and perform board-level testing on the above-mentioned second target chip During the level test, when the junction temperature value of the above-mentioned second target chip is a predetermined temperature, the junction temperature rise value of the above-mentioned second target chip within the above-mentioned predetermined time is detected to obtain the junction temperature rise threshold value, and the chips meeting the power consumption limit conditions are screened by three screening conditions: static current threshold value, oscillation frequency threshold value and junction temperature rise threshold value. This can avoid high-temperature reversal phenomenon in chips that meet the power consumption limit conditions, thereby eliminating the need to reduce the power consumption limit, that is, eliminating the need to reduce the static current threshold value and the oscillation frequency threshold value, thereby improving the chip yield and solving the problem of high-temperature reversal phenomenon within the power consumption limit range in the screening method in the prior art, which leads to the need to reduce the power consumption limit and thus leads to low chip yield.

[0093] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip screening method, characterized in that: The method comprises: Performing board-level testing on multiple sample chips, wherein the ambient temperature of the board-level testing is an extreme temperature, determining the sample chip that meets a first predetermined condition as a first target chip, obtaining static current values ​​and oscillation frequency values ​​of multiple first target chips, and determining a static current threshold and an oscillation frequency threshold, wherein the extreme temperature is the highest ambient temperature of an application scenario of the sample chip, and the first predetermined condition is that the test chip operates normally and the junction temperature value is within a first predetermined range; Performing an FT test on the first target chip, and determining the first target chip that meets a second predetermined condition as a second target chip, wherein the second predetermined condition is that a junction temperature rise value of the test chip within a predetermined time is within a second predetermined range; Performing a board-level test on the second target chip, wherein the ambient temperature of the board-level test is an extreme temperature, determining the second target chip that meets the first predetermined condition and the second predetermined condition as a third target chip, obtaining a junction temperature rise value of the third target chip in the FT test, and determining a junction temperature rise threshold; Screening the chip to be tested according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold, wherein the chip to be tested and the sample chip are chips of the same model, and screening the chip to be tested according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold includes: When the ambient temperature is the production temperature, the static current value of the chip to be tested and the oscillation frequency value of the oscillation circuit of the chip to be tested are obtained to obtain the target static current value and the target oscillation frequency value, and the production temperature is the temperature of the environment in which the chip to be tested is located during the production operation; when the junction temperature value of the chip to be tested is a predetermined temperature, the junction temperature rise value of the chip to be tested within the predetermined time is detected to obtain the target junction temperature rise value; when the target static current value is less than or equal to the static current threshold, the target oscillation frequency value is less than or equal to the oscillation frequency threshold, and the target junction temperature rise value is less than or equal to the junction temperature rise threshold, it is determined that the chip to be tested is qualified.

2. The method according to claim 1, characterized in that Before performing the FT test on the first target chip and determining the first target chip that meets the second predetermined condition as the second target chip, the method further includes: Performing a board-level test on a plurality of the first target chips, wherein the ambient temperature of the board-level test is an extreme temperature, and detecting that the junction temperature value of the first target chip is a predetermined temperature, and obtaining a first junction temperature rise value by measuring the junction temperature rise value of the first target chip within the predetermined time; The second predetermined range is determined according to the first junction temperature rise value.

3. The method according to claim 1, characterized in that Performing an FT test on the first target chip and determining the first target chip that meets a second predetermined condition as a second target chip includes: Under the condition that the test temperature is a set temperature and the test stimulus is a set test stimulus, detecting the junction temperature rise value of the first target chip at the predetermined time to obtain a second junction temperature rise value, the test temperature is the ambient temperature of performing the FT test on the first target chip, and the test stimulus is the stimulus for performing the FT test on the first target chip; The set temperature and the set test stimulus are adjusted until the second target chip is obtained.

4. The method according to claim 2, characterized in that: The predetermined temperature is between 110°C and 120°C.

5. The method according to claim 1, characterized in that The predetermined time is greater than or equal to 100 ms.

6. The method according to claim 1, characterized in that The first predetermined range is 115°C to 125°C.

7. The method according to claim 2, characterized in that The minimum value of the second predetermined range is the first temperature rise value, the maximum value of the second predetermined range is the second temperature rise value, the first temperature rise value is 70% to 90% of the first junction temperature rise value, and the second temperature rise value is 110% to 130% of the first junction temperature rise value.

8. A chip screening device, characterized in that: The device comprises: A first test unit is used to perform a board-level test on a plurality of sample chips, wherein the ambient temperature of the board-level test is a limit temperature, the sample chip that meets a first predetermined condition is determined as a first target chip, static current values ​​and oscillation frequency values ​​of the plurality of first target chips are obtained, and a static current threshold value and an oscillation frequency threshold value are determined, wherein the limit temperature is the highest ambient temperature of an application scenario of the sample chip, and the first predetermined condition is that the test chip operates normally and the junction temperature value is within a first predetermined range; A second test unit is used to perform an FT test on the first target chip, and determine the first target chip that meets a second predetermined condition as a second target chip, wherein the second predetermined condition is that the junction temperature rise value of the test chip within a predetermined time is within a second predetermined range; A third testing unit is configured to perform a board-level test on the second target chip, wherein the ambient temperature of the board-level test is an extreme temperature, determine the second target chip that meets the first predetermined condition and the second predetermined condition as a third target chip, obtain a junction temperature rise value of the third target chip in the FT test, and determine a junction temperature rise threshold; A judgment unit is used to screen the chip to be tested according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold, the chip to be tested and the sample chip are chips of the same model, the judgment unit includes a third detection module, a fourth detection module and a second determination module, the third detection module is used to obtain the static current value of the chip to be tested and the oscillation frequency value of the oscillation circuit of the chip to be tested when the ambient temperature is the production temperature, and obtain the target static current value and the target oscillation frequency value, the production temperature is the temperature of the environment in which the chip to be tested is produced, the fourth detection module is used to detect the junction temperature rise value of the chip to be tested within the predetermined time when the junction temperature value of the chip to be tested is a predetermined temperature, and obtain the target junction temperature rise value, the second determination module is used to determine that the chip to be tested is qualified when the target static current value is less than or equal to the static current threshold, the target oscillation frequency value is less than or equal to the oscillation frequency threshold, and the target junction temperature rise value is less than or equal to the junction temperature rise threshold.

9. A sieve device, comprising a processor and a memory, characterized in that: The processor is used to run a program, wherein the program executes the method according to any one of claims 1 to 7 when running.

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