Thin film transistor, manufacturing method, driving method and display panel

Abstract

The present application discloses a thin film transistor, a manufacturing method, a driving method and a display panel. The thin film transistor includes: a substrate; a bottom gate electrode, which is arranged on the substrate; a bottom gate insulating layer, which covers the bottom gate electrode and the substrate; a metal layer, which is arranged on the bottom gate insulating layer; a metal oxide semiconductor layer, which is stuck in the metal layer, and one side of the metal oxide semiconductor layer is in contact with the bottom gate insulating layer; a top gate insulating layer, which covers the bottom gate insulating layer and the metal layer, and the top gate insulating layer is in contact with the other side of the metal oxide semiconductor layer, and the top gate insulating layer is provided with a via hole, and the via hole exposes a part of the metal layer; a top gate electrode, which is arranged on the top gate insulating layer. In the embodiment of the present application, a first channel and a second channel are respectively arranged on both sides of the metal oxide semiconductor layer, and the bottom gate electrode and the top gate electrode are alternately opened, and the first channel and the second channel are used alternately, which can effectively reduce the drift of the threshold voltage and increase the stability of the TFT device.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor, a manufacturing method, a driving method and a display panel. Background Art

[0002] Compared with the current mainstream LCD display panel with a-Si as the active layer, the IGZO (Indium Gallium Zinc Oxide) active layer has technical advantages such as visible light transparency, high electron mobility, high switching current ratio, flexible display, good uniformity and low production cost, which has been widely favored by the industry. Therefore, in recent years, the research on the preparation technology, process structure and other related aspects of a-IGZO has shown a blowout trend, and various manufacturers have also launched a variety of liquid crystal displays based on IGZO TFT (Thin Film Transistor).

[0003] Currently, LCDs are mostly driven by TFTs with a-Si as the active layer. The a-Si film has no grain boundaries, good film uniformity and low preparation temperature, which can achieve large-area uniform color luminous display. However, the a-Si TFT has a mobility of only 0.5-1, so the shape of the TFT is mostly U-shaped, which occupies a larger area and has a smaller aperture ratio. The carrier mobility of IGZO is significantly higher than that of a-Si TFT (about 20-50 times), so it can be miniaturized and reduce energy consumption. However, the device stability of IGZO is poor, and the device is subjected to strong stress when exposed to high voltage and strong light for a long time, resulting in a shortened panel life. Therefore, how to improve the stability of IGZO devices is an urgent problem to be solved. Summary of the invention

[0004] The embodiments of the present application provide a thin film transistor, a manufacturing method, a driving method and a display panel, wherein a first channel and a second channel are respectively arranged on both sides of a metal oxide semiconductor layer, a bottom gate electrode and a top gate electrode are alternately opened, and the first channel and the second channel are alternately used, which can effectively reduce the drift of the threshold voltage and increase the stability of the TFT device.

[0005] In a first aspect, an embodiment of the present application provides a thin film transistor, including:

[0006] substrate;

[0007] A bottom gate electrode, the bottom gate electrode is disposed on the substrate;

[0008] a bottom gate insulating layer, the bottom gate insulating layer covering the bottom gate electrode and the substrate;

[0009] A metal layer, the metal layer is disposed on the bottom gate insulating layer;

[0010] a metal oxide semiconductor layer, wherein the metal oxide semiconductor layer is disposed in the metal layer, and one side of the metal oxide semiconductor layer is in contact with the bottom gate insulating layer;

[0011] a top gate insulating layer, the top gate insulating layer covering the bottom gate insulating layer and the metal layer, the top gate insulating layer contacting the other side of the metal oxide semiconductor layer, the top gate insulating layer being provided with a via hole, the via hole exposing a portion of the metal layer;

[0012] A top gate electrode is disposed on the top gate insulating layer.

[0013] In some embodiments, a first channel area of ​​the metal oxide semiconductor layer in contact with the bottom gate insulating layer and a second channel area of ​​the metal oxide semiconductor layer in contact with the top gate insulating layer are the same in size.

[0014] In some embodiments, the bottom gate electrode is disposed opposite to the metal oxide semiconductor layer, and an area of ​​a side of the bottom gate electrode close to the bottom gate insulating layer is larger than an area of ​​the first channel.

[0015] In some embodiments, the top gate electrode is disposed opposite to the metal oxide semiconductor layer, and an area of ​​a side of the top gate electrode close to the top gate insulating layer is larger than an area of ​​the second channel.

[0016] In some embodiments, the thin film transistor further comprises:

[0017] A PFA layer, the PFA layer covering the top gate insulating layer and the top gate electrode;

[0018] A common electrode, the common electrode is arranged on the PFA layer;

[0019] a protective layer, wherein the protective layer covers the PFA layer and the common electrode, and the via hole passes through the PFA layer and the protective layer;

[0020] A pixel electrode layer is disposed on the protective layer, and the pixel electrode layer is deposited in the via hole and contacts the metal layer.

[0021] In some embodiments, the material of the metal oxide semiconductor layer is IGZO.

[0022] In a second aspect, the present application provides a method for manufacturing a thin film transistor, comprising:

[0023] Providing a substrate, depositing a layer of metal as a bottom gate electrode on the substrate, and etching a pattern;

[0024] depositing a bottom gate insulating layer on the substrate and the bottom gate electrode;

[0025] Depositing a layer of metal on the bottom gate insulating layer, and etching a pattern to obtain a first metal layer;

[0026] Depositing a metal oxide semiconductor layer at a position corresponding to the bottom gate electrode on the first metal layer, and etching a pattern;

[0027] Depositing a layer of metal on the metal oxide semiconductor layer, and etching a pattern to obtain a second metal layer;

[0028] Depositing a top gate insulating layer on the bottom gate insulating layer, the metal oxide semiconductor layer and the second metal layer;

[0029] A top gate electrode is deposited at a position corresponding to the metal oxide semiconductor layer on the top gate insulating layer, and a pattern is etched to form a via hole, wherein the via hole penetrates the bottom gate insulating layer to expose a portion of the second metal layer.

[0030] In some embodiments, a first channel of the metal oxide semiconductor layer is etched on the first metal layer, and a second channel of the metal oxide semiconductor layer is etched on the second metal layer, and the first channel and the second channel have the same area.

[0031] In a third aspect, the present application provides a thin film transistor driving method, applied to any of the thin film transistors described above, comprising:

[0032] In a first preset time period, controlling the bottom gate electrode of the thin film transistor to be turned on and the top gate electrode to be turned off;

[0033] In a second preset time period after the first preset time period, controlling the bottom gate electrode to be closed and the top gate electrode to be opened;

[0034] The control strategy of the first preset time period and the second preset time period is repeated alternately to drive the thin film transistor.

[0035] In a fourth aspect, the present application provides a display panel, wherein the display panel comprises an array substrate, wherein the array substrate comprises a plurality of thin film transistors as described in any one of the above.

[0036] The thin film transistor, manufacturing method, driving method and display panel provided in the embodiments of the present application respectively set a first channel and a second channel on both sides of the metal oxide semiconductor layer, the bottom gate electrode and the top gate electrode are opened alternately, and the first channel and the second channel are used alternately, which can effectively reduce the drift of the threshold voltage and increase the stability of the TFT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0038] Figure 1 is a schematic diagram of the structure of a thin film transistor in one embodiment of the present application;

[0039] Figure 2 is a schematic structural diagram of a thin film transistor in another embodiment of the present application;

[0040] Figure 3 is a schematic flow chart of a method for manufacturing a thin film transistor in an embodiment of the present application;

[0041] Figure 4 It is a flow chart of the thin film transistor driving method in the embodiment of the present application.

[0042] Figure Number:

[0043] 1. Substrate; 2. Bottom gate electrode; 3. Bottom gate insulating layer; 4. Metal layer; 41. Via hole; 5. Metal oxide semiconductor layer; 6. Top gate insulating layer; 7. Top gate electrode; 8. PFA layer; 9. Common electrode; 10. Protective layer; 11. Pixel electrode layer. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0045] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0046] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0047] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0048] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0049] See also Figure 1 and Figure 2 An embodiment of the present application provides a thin film transistor, which includes a substrate 1, a bottom gate electrode 2, a bottom gate insulating layer 3, a metal layer 4, a metal oxide semiconductor layer 5, a top gate insulating layer 6 and a top gate electrode 7.

[0050] The substrate 1 is a glass substrate, on which the above-mentioned other devices are arranged. The bottom gate electrode 2 is arranged on the substrate 1, and a layer of metal is deposited on the substrate 1 as the bottom gate electrode 2, and a pattern is etched. The bottom gate electrode 2 only occupies a part of the substrate 1, so a bottom gate insulating layer 3 is deposited on the substrate 1 and the bottom gate electrode 2, and the bottom gate insulating layer 3 covers the bottom gate electrode 2 and the substrate 1.

[0051] The metal layer 4 is arranged on the bottom gate insulating layer 3, and the metal oxide semiconductor layer 5 is arranged in the metal layer 4. The metal layer 4 includes a first metal layer and a second metal layer. Therefore, a layer of metal is first deposited on the bottom gate insulating layer 3, and a pattern is etched to obtain the first metal layer, and then the metal oxide semiconductor layer 5 is deposited on the first metal layer and a pattern is etched, and then another layer of metal is deposited on the metal oxide semiconductor layer 5 and a pattern is etched to obtain the second metal layer, that is, the metal oxide semiconductor layer 5 is arranged in the middle of the metal layer 4.

[0052] It should be noted that the metal layer 4 does not completely surround the metal oxide semiconductor layer 5, and the metal layer 4 has openings on the side close to the glass substrate and the side away from the glass substrate to expose the metal oxide semiconductor layer 5, respectively forming a first channel and a second channel of the metal oxide semiconductor layer 5. Among them, the side of the metal oxide semiconductor layer 5 close to the glass substrate, that is, the first channel, contacts the bottom gate insulating layer 3.

[0053] The metal layer 4 only occupies a part of the bottom gate insulating layer 3, so a top gate insulating layer 6 is deposited on the bottom gate insulating layer 3 and the metal layer 4, and the top gate insulating layer 6 covers the bottom gate insulating layer 3 and the metal layer 4. Among them, since the side of the metal oxide semiconductor layer 5 away from the glass substrate is exposed to the outside and not covered by the metal layer 4, and the top gate insulating layer 6 covers the metal oxide semiconductor layer 5 at the same time, the side of the metal oxide semiconductor layer 5 away from the glass substrate, that is, the second channel, is in contact with the top gate insulating layer 6.

[0054] In addition, in order to perform data communication, the metal layer 4 needs to be connected to the outside, so the top gate insulating layer 6 is provided with a via 41, and the via 41 penetrates the top gate insulating layer 6 to expose a portion of the metal layer 4 so as to be connected to other electrodes.

[0055] The top gate electrode 7 is disposed on the top gate insulating layer 6 . The top gate electrode 7 is deposited on the top gate insulating layer 6 and a pattern is etched out.

[0056] GI (gate insulating layer) serves as the gate insulating layer of TFT and has a large number of defect states. When TFT is working, these defect states will capture electrons in the active layer, causing the threshold voltage to drift. At the same time, since the in-plane TFT is in a holding state most of the time, that is, the gate voltage is in a negative voltage state for a long time, the PV layer (protective layer) (the PV layer is covered on the active layer of the basic structure to block the influence of water vapor) will capture a large amount of positive charges to form a parasitic TFT, causing the off-state leakage current to increase.

[0057] In this embodiment, the first channel and the second channel are respectively arranged on both sides of the metal oxide semiconductor layer 5, and the bottom gate electrode 2 and the top gate electrode 7 are opened alternately. The first channel and the second channel are used alternately, which can reduce the effects of the above two channels, effectively reduce the drift of the threshold voltage, and increase the stability of the TFT device.

[0058] In one embodiment, a first channel of the metal oxide semiconductor layer 5 is etched on a first metal layer (not shown in the figure), and a second channel of the metal oxide semiconductor layer 5 is etched on a second metal layer (not shown in the figure), and the etching of the metal layer 4 makes the area of ​​the first channel and the second channel the same.

[0059] In this embodiment, by making SD contact with the upper surface and the lower surface of the active layer respectively, it can be achieved that the geometric shapes of the TFT when the bottom gate electrode 2 and the top gate electrode 7 are respectively opened are completely consistent, that is, the projection sizes of the exposed active layer (the part not in contact with SD) on the bottom gate electrode 2 and the top gate electrode 7 are consistent. In this way, no matter which electrode is opened, the working state of the TFT is consistent, avoiding the flickering phenomenon of the panel caused by inconsistent front and rear voltages of the pixel ITO (pixel electrode layer 11) due to inconsistent working states of the TFT when the electrodes are alternated; and the voltages applied by the bottom gate electrode 2 and the top gate electrode 7 can be completely consistent, and there is no need to set up different circuits and feedback circuits for the dual gates separately (when the front and rear states of the panel are inconsistent, a feedback circuit is required to keep the panel state stable).

[0060] In one embodiment, the bottom gate electrode 2, the metal oxide semiconductor layer 5 and the top gate electrode 7 only occupy a part of the area, and the bottom gate electrode 2, the metal oxide semiconductor layer 5 and the top gate electrode 7 are arranged opposite to each other in sequence, and the area of ​​the side of the bottom gate electrode 2 close to the bottom gate insulating layer 3 is larger than the first channel area, and the area of ​​the side of the top gate electrode 7 close to the top gate insulating layer 6 is larger than the second channel area. In addition, the bottom gate electrode 2 and the top gate electrode 7 can shield the backlight from the upper and lower parts for the active layer, reduce the influence of light on the active layer, and effectively increase the stability of the oxide TFT device.

[0061] In one embodiment, the material of the metal oxide semiconductor layer 5 is IGZO, and the materials of the bottom gate insulating layer 3 and the top gate insulating layer 6 are SiNx, SiOx or a combination of the two.

[0062] In one embodiment, Figure 2As shown, the thin film transistor also includes a PFA (Polymer Film on Array, an organic film on the array substrate side) layer 8, a common electrode 9, a protective layer 10 and a pixel electrode layer 11. The PFA layer 8 covers the top gate insulating layer 6 and the top gate electrode 7, the common electrode 9 is arranged on the PFA layer 8, and the protective layer 10 covers the PFA layer 8 and the common electrode 9. Since the metal layer 4 needs to be connected to the outside, the via 41 penetrates the top gate insulating layer 6, the PFA layer 8 and the protective layer 10 to expose a part of the metal layer 4. The pixel electrode layer 11 is arranged on the protective layer 10, and the pixel electrode layer 11 is deposited in the via 41 and contacts the metal layer 4. The material of the pixel electrode layer 11 is ITO (Indium Tin Oxide, indium tin oxide).

[0063] See also Figure 1 , Figure 2 and Figure 3 , an embodiment of the present application provides a method for manufacturing a thin film transistor, the method comprising:

[0064] A substrate 1 is provided, the substrate 1 is a glass substrate, a layer of metal is deposited on the substrate 1 as a bottom gate electrode 2, and a pattern is etched, and the etching process can be a dry etching process, a wet etching process, other suitable etching processes, or a combination of the foregoing. A bottom gate insulating layer 3 is deposited on the substrate 1 and the bottom gate electrode 2, the bottom gate insulating layer 3 covers the bottom gate electrode 2 and the substrate 1, and the material of the bottom gate insulating layer 3 is SiNx, SiOx, or a combination of the two.

[0065] The metal layer 4 is disposed on the bottom gate insulating layer 3, and the metal oxide semiconductor layer 5 is disposed in the metal layer 4. The metal layer 4 includes a first metal layer and a second metal layer. Therefore, a layer of metal is first deposited on the bottom gate insulating layer 3, and a pattern is etched to obtain the first metal layer. Then, the metal oxide semiconductor layer 5 is deposited at a position corresponding to the bottom gate electrode 2 on the first metal layer, and a pattern is etched. Then, another layer of metal is deposited on the metal oxide semiconductor layer 5, and a pattern is etched to obtain the second metal layer. That is to say, the metal oxide semiconductor layer 5 is disposed in the middle of the metal layer 4. The material of the metal oxide semiconductor layer 5 is IGZO.

[0066] It should be noted that the metal layer 4 does not completely surround the metal oxide semiconductor layer 5. The metal layer 4 has openings on the side close to the glass substrate and the side away from the glass substrate to expose the metal oxide semiconductor layer 5, respectively forming a first channel and a second channel of the metal oxide semiconductor layer 5, and the first channel is arranged opposite to the bottom gate electrode 2. Among them, the side of the metal oxide semiconductor layer 5 close to the glass substrate, that is, the first channel, contacts the bottom gate insulating layer 3.

[0067] The metal layer 4 only occupies a part of the bottom gate insulating layer 3, and the second channel of the metal oxide semiconductor layer 5 is exposed. Therefore, a top gate insulating layer 6 is deposited on the bottom gate insulating layer 3, the metal oxide semiconductor layer 5 and the second metal layer. The top gate insulating layer 6 covers the bottom gate insulating layer 3 and the metal layer 4. The material of the bottom gate insulating layer 3 is SiNx, SiOx or a combination of the two. Finally, a top gate electrode 7 is deposited on the top gate insulating layer 6 at a position corresponding to the metal oxide semiconductor layer 5. The second channel is arranged opposite to the top gate electrode 7. A pattern is etched to form a via 41. The via 41 penetrates the bottom gate insulating layer 3 to expose a part of the second metal layer so as to be connected with other electrodes.

[0068] GI serves as the gate insulating layer of TFT and has a large number of defect states. When TFT is working, these defect states will capture electrons in the active layer, causing the threshold voltage to drift. At the same time, since the in-plane TFT is in a holding state most of the time, that is, the gate voltage is in a negative voltage state for a long time, the PV layer (the PV layer covers the active layer of the basic structure to block the influence of water vapor) will capture a large amount of positive charges and form a parasitic TFT, causing the off-state leakage current to increase.

[0069] In this embodiment, the first channel and the second channel are respectively arranged on both sides of the metal oxide semiconductor layer 5, and the bottom gate electrode 2 and the top gate electrode 7 are opened alternately. The first channel and the second channel are used alternately, which can reduce the effects of the above two channels, effectively reduce the drift of the threshold voltage, and increase the stability of the TFT device.

[0070] In one embodiment, a first channel of the metal oxide semiconductor layer 5 is etched on the first metal layer, and a second channel of the metal oxide semiconductor layer 5 is etched on the second metal layer. The metal layer 4 is etched so that the first channel and the second channel have the same area.

[0071] In this embodiment, by making SD contact with the upper surface and the lower surface of the active layer respectively, it can be achieved that the geometric shapes of the TFT when the bottom gate electrode 2 and the top gate electrode 7 are respectively opened are completely consistent, that is, the projection sizes of the exposed active layer (the part not in contact with SD) on the bottom gate electrode 2 and the top gate electrode 7 are consistent. In this way, no matter which electrode is opened, the working state of the TFT is consistent, avoiding the flickering phenomenon of the panel caused by inconsistent front and rear voltages of the pixel ITO (pixel electrode layer 11) due to inconsistent working states of the TFT when the electrodes are alternated; and the voltages applied by the bottom gate electrode 2 and the top gate electrode 7 can be completely consistent, and there is no need to set up different circuits and feedback circuits for the dual gates separately (when the front and rear states of the panel are inconsistent, a feedback circuit is required to keep the panel state stable).

[0072] In one embodiment, the bottom gate electrode 2, the metal oxide semiconductor layer 5 and the top gate electrode 7 only occupy a part of the area, and the bottom gate electrode 2, the metal oxide semiconductor layer 5 and the top gate electrode 7 are arranged opposite to each other in sequence, and the area of ​​the side of the bottom gate electrode 2 close to the bottom gate insulating layer 3 is larger than the first channel area, and the area of ​​the side of the top gate electrode 7 close to the top gate insulating layer 6 is larger than the second channel area. In addition, the bottom gate electrode 2 and the top gate electrode 7 can shield the backlight from the upper and lower parts for the active layer, reduce the influence of light on the active layer, and effectively increase the stability of the oxide TFT device.

[0073] In one embodiment, Figure 2 As shown, a PFA layer 8 is deposited on the top gate insulating layer 6 and the top gate electrode 7, the PFA layer 8 covers the top gate insulating layer 6 and the top gate electrode 7, a common electrode 9 is arranged on the PFA layer 8, and then a protective layer 10 is deposited on the common electrode 9 and the PFA layer 8, the protective layer 10 covers the PFA layer 8 and the common electrode 9, and finally a pixel electrode layer 11 is deposited on the protective layer 10. Since the metal layer 4 needs to be connected to the outside, the via 41 penetrates the top gate insulating layer 6, the PFA layer 8 and the protective layer 10 to expose a part of the second metal layer, and the pixel electrode layer 11 is deposited in the via 41 and contacts the second metal layer, and the material of the pixel electrode layer 11 is ITO.

[0074] See also Figure 4 The embodiment of the present application provides a thin film transistor driving method, which is applied to the thin film transistor described in any of the above embodiments. The method includes steps S101-S103, which are specifically as follows:

[0075] S101, within a first preset time period, controlling the bottom gate electrode of the thin film transistor to be turned on and the top gate electrode to be turned off;

[0076] S1012, in a second preset time period after the first preset time period, controlling the bottom gate electrode to be closed and the top gate electrode to be opened;

[0077] S1013 , alternately repeating the control strategy of the first preset time period and the second preset time period to drive the thin film transistor.

[0078] Specifically, in the first preset time period, the bottom gate electrode (Bottom M1) is turned on and the top gate electrode (Top M1) is turned off. At this time, the lower part of the metal oxide semiconductor layer (IGZO) serves as the front channel as the main channel for the TFT to be turned on, and the upper part of the IGZO serves as the back channel and plays a major role when the TFT is turned off. In the second preset time period after the first preset time period, the Bottom M1 is turned off and the Top M1 is turned on. At this time, the upper part of the IGZO serves as the front channel as the main channel for the TFT to be turned on, and the lower part of the IGZO serves as the back channel and plays a major role when the TFT is turned off. After the second preset time period, the control strategy in the first preset time period is repeated to drive the thin film transistor. By analogy, by alternately turning on the bottom gate electrode (Bottom M1) and the top gate electrode (Top M1) (the alternating time can be 1 frame, 1s or longer), the front and rear channels of the active layer IGZO can be used alternately, which can effectively reduce the drift of the threshold voltage and increase the stability of the TFT device.

[0079] In addition, the first channel and the second channel respectively arranged on both sides of the metal oxide semiconductor layer have the same area size, so that when the bottom gate electrode and the top gate electrode are respectively turned on, the geometric shapes of the TFT are completely consistent, that is, the projection size of the exposed active layer (the part not in contact with the SD) on the bottom gate electrode and the top gate electrode is consistent, so that no matter which electrode is turned on, the working state of the TFT is consistent, avoiding the flickering of the panel due to inconsistent front and rear voltages of the pixel ITO (pixel electrode layer) caused by inconsistent TFT working states when the electrodes are alternated; and the voltages applied to the bottom gate electrode and the top gate electrode can be completely consistent, and there is no need to set up different circuits and feedback circuits for the dual gates (when the front and rear states of the panel are inconsistent, a feedback circuit is required to keep the panel state stable).

[0080] It should be noted that the first preset time period and the second preset time period may be the same or different. In addition, the specific values ​​of the first preset time period and the second preset time period may be 1 frame, 1s or longer, which are set according to the driving requirements of the thin film transistor and are not specifically limited in this embodiment.

[0081] An embodiment of the present application provides a display panel, wherein the display panel includes an array substrate, and the array substrate includes a plurality of thin film transistors described in any of the above embodiments.

[0082] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0083] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The above is a detailed introduction to a thin film transistor, a manufacturing method, a driving method and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A thin film transistor, characterized in that: include: substrate; A bottom gate electrode, the bottom gate electrode is disposed on the substrate; a bottom gate insulating layer, the bottom gate insulating layer covering the bottom gate electrode and the substrate; A metal layer, the metal layer is disposed on the bottom gate insulating layer; a metal oxide semiconductor layer, wherein the metal oxide semiconductor layer is disposed in the metal layer, and one side of the metal oxide semiconductor layer is in contact with the bottom gate insulating layer; a top gate insulating layer, the top gate insulating layer covering the bottom gate insulating layer and the metal layer, the top gate insulating layer contacting the other side of the metal oxide semiconductor layer, the top gate insulating layer being provided with a via hole, the via hole exposing a portion of the metal layer; A top gate electrode, the top gate electrode being disposed on the top gate insulating layer; The metal layer is provided with openings on a side close to the substrate and a side away from the substrate, so as to partially expose a side of the metal oxide semiconductor layer close to the bottom gate insulating layer and partially expose a side of the metal oxide semiconductor layer close to the top gate insulating layer; A first channel and a second channel of the metal oxide semiconductor layer are formed at the two openings respectively; The first channel area of ​​the metal oxide semiconductor layer in contact with the bottom gate insulating layer and the second channel area of ​​the metal oxide semiconductor layer in contact with the top gate insulating layer are the same in size; The bottom gate electrode and the top gate electrode are opened alternately, and the first channel and the second channel are used alternately.

2. The thin film transistor according to claim 1, wherein: The bottom gate electrode is arranged opposite to the metal oxide semiconductor layer, and an area of ​​a side of the bottom gate electrode close to the bottom gate insulating layer is larger than an area of ​​the first channel.

3. The thin film transistor according to claim 1, wherein: The top gate electrode is arranged opposite to the metal oxide semiconductor layer, and an area of ​​a side of the top gate electrode close to the top gate insulating layer is larger than an area of ​​the second channel.

4. The thin film transistor according to claim 1, wherein: The thin film transistor further comprises: A PFA layer, the PFA layer covering the top gate insulating layer and the top gate electrode; A common electrode, the common electrode is arranged on the PFA layer; a protective layer, wherein the protective layer covers the PFA layer and the common electrode, and the via hole passes through the PFA layer and the protective layer; A pixel electrode layer is disposed on the protective layer, and the pixel electrode layer is deposited in the via hole and contacts the metal layer.

5. The thin film transistor according to claim 1, wherein: The material of the metal oxide semiconductor layer is IGZO.

6. A method for manufacturing a thin film transistor, characterized in that: include: Providing a substrate, depositing a layer of metal as a bottom gate electrode on the substrate, and etching a pattern; depositing a bottom gate insulating layer on the substrate and the bottom gate electrode; Depositing a layer of metal on the bottom gate insulating layer, and etching a pattern to obtain a first metal layer; Depositing a metal oxide semiconductor layer at a position corresponding to the bottom gate electrode on the first metal layer, and etching a pattern; Depositing a layer of metal on the metal oxide semiconductor layer, and etching a pattern to obtain a second metal layer; Depositing a top gate insulating layer on the bottom gate insulating layer, the metal oxide semiconductor layer and the second metal layer; Depositing a top gate electrode at a position corresponding to the metal oxide semiconductor layer on the top gate insulating layer, and etching a pattern to form a via hole, wherein the via hole penetrates the bottom gate insulating layer to expose a portion of the second metal layer; wherein etching is performed on the first metal layer to form openings on a side close to the substrate and a side away from the substrate, so as to partially expose a side of the metal oxide semiconductor layer close to the bottom gate insulating layer and form a first channel of the metal oxide semiconductor layer; Etching on the second metal layer to form an opening on a side away from the glass substrate to partially expose a side of the metal oxide semiconductor layer close to the top gate insulating layer and form a second channel of the metal oxide semiconductor layer, wherein the first channel and the second channel have the same area; The bottom gate electrode and the top gate electrode are opened alternately, and the first channel and the second channel are used alternately.

7. A thin film transistor driving method, applied to the thin film transistor according to any one of claims 1 to 5, characterized in that: include: In a first preset time period, controlling the bottom gate electrode of the thin film transistor to be turned on and the top gate electrode to be turned off; In a second preset time period after the first preset time period, controlling the bottom gate electrode to be closed and the top gate electrode to be opened; The control strategy of the first preset time period and the second preset time period is repeated alternately to drive the thin film transistor.

8. A display panel, characterized in that: The display panel includes an array substrate, and the array substrate includes a plurality of thin film transistors according to any one of claims 1 to 5.

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