Port multiplexing circuit and electronic device
By designing a port multiplexing circuit for chip pins, using power supply modules and selection modules, multi-function multiplexing of single ports is realized, solving the problem of limited PIN, reducing the number of ports and electrostatic discharge risks, and saving costs.
Patent Information
- Application Number
- CN202011050031.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-09-29
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2040-09-29
AI Technical Summary
In some application scenarios, the chip's PIN (pin) is limited, making it difficult to implement multiple testing functions. Traditional circuit testing requires multiple PINs, resulting in an increase in the number of ports, a large area of consumption, and an increase in cost.
Design a port multiplexing circuit, including power supply module, comparator and selection module, realize multi-function multiplexing of single ports through clock signals and comparison signals, reduce the number of ports on the chip and reduce the risk of electrostatic discharge.
Achieving multi-functional multiplexing of single ports reduces the number of ports on the chip, reduces the risk of electrostatic discharge, and saves costs.
Smart Images
Figure CN114337639B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a port multiplexing circuit and electronic equipment for chip pins. Background Art
[0002] With the rapid advancement of science and technology, people can manufacture integrated circuits with large scale, structural load and high integration. They have a large chip core area and more peripheral ports. The core circuit of the chip completes the main functions of the chip; while the port is responsible for the communication between the internal circuit and the peripheral devices of the circuit, and is connected to the outside through bonding wires such as copper wire or gold wire. Both are indispensable. However, in some application scenarios, system designers do not have very high requirements for the functions of integrated circuits, and even some are simple. At this time, the scale of the chip core circuit is relatively small and the integration is low.
[0003] With the advancement of circuit design technology, the area required for devices to complete the same function is getting smaller and smaller, but the ports of the circuit are sometimes limited by the package shape, and the area occupied does not change much. In some ports where large currents flow, larger diameter bonding wires are required, and the layout area of the ports is even larger. Compared with the increasingly smaller internal circuit area, the proportion of the area occupied by the port in the entire circuit is increasing. Reducing the number of circuit ports has become a more realistic and reliable method for layout engineers to reduce circuit area and circuit costs. While keeping the circuit package and the number of ports unchanged, the only direct and effective method is to reduce the number of test ports.
[0004] In the entire integrated circuit design process, circuit testing is a very important step. Before the circuit goes to the market, various parameters of the circuit need to be fully and accurately tested. To this end, circuit design engineers need to add test modules to the circuit, guide the circuit into the test state through the test port, and read the test data through the port.
[0005] Traditional circuit testing generally uses multi-port multiplexing technology to achieve different test functions, which requires the chip to have multiple PINs (pins) to achieve circuit testing. However, in some cases, the number of PINs (pins) that can be used by the chip is very limited. At this time, it is particularly meaningful to use a single pin to achieve multiple test functions. Summary of the invention
[0006] In order to solve the above technical problems, the present disclosure provides a port multiplexing circuit and electronic device for chip pins, which can realize multi-functional multiplexing of a single port and effectively reduce the number of ports on the chip.
[0007] In one aspect, the present disclosure provides a port multiplexing circuit, comprising:
[0008] A power supply module, comprising a first current source and a first capacitor connected in series between a power supply terminal and a ground, wherein a connection node between the first current source and the first capacitor is connected to an external port;
[0009] A first comparator, wherein a non-inverting input terminal of the first comparator is connected to a connection node between the first current source and the first capacitor, an inverting input terminal is connected to a first reference voltage, and an output terminal provides a first comparison signal;
[0010] The selection module is connected to the output end of the first comparator and has a plurality of output ports, and is used for selecting one of the plurality of output ports to be turned on according to the clock signal and the first comparison signal.
[0011] Preferably, the port multiplexing circuit further includes:
[0012] A clock signal generator, the output end of which is connected to the aforementioned selection module to provide the aforementioned clock signal.
[0013] Preferably, the selection module has a first input port connected to the aforementioned clock signal, a second input port connected to the aforementioned first comparison signal, and a third input port connected to the reset signal.
[0014] Furthermore, the plurality of output ports include a first output port, a second output port, a third output port and a fourth output port.
[0015] Preferably, the selection module includes:
[0016] A first selection unit, the first selection unit having a first trigger, a first NOR gate, a second NOR gate, and a second trigger,
[0017] The set end of the first flip-flop is connected to the second state output end of the first flip-flop, the control end is connected to the clock signal as the first input port, and the reset end is connected to the reset signal as the third input port;
[0018] The input end of the first NOR gate is respectively connected to the first state output end of the first trigger and the output end of the second NOR gate;
[0019] The input end of the second NOR gate is respectively connected to the output end of the first NOR gate and the third input port, and the output end of the second NOR gate is connected to the control end of the second trigger;
[0020] The set terminal of the aforementioned second trigger is connected to the aforementioned first comparison signal as the aforementioned second input port, the reset terminal is connected to the aforementioned third input port, and the first state output terminal of the aforementioned second trigger is used as the aforementioned first output port.
[0021] Preferably, the selection module further includes:
[0022] a second selection unit, the second selection unit having a third flip-flop, a third NOR gate, a fourth NOR gate and a fourth flip-flop,
[0023] The set end of the third trigger is connected to the second state output end of the third trigger, the control end is connected to the second state output end of the first trigger, and the reset end is connected to the third input port.
[0024] The input end of the third NOR gate is respectively connected to the first state output end of the third trigger and the output end of the fourth NOR gate;
[0025] The input end of the fourth NOR gate is connected to the output end of the third NOR gate and the third input port respectively, and the output end of the fourth NOR gate is connected to the control end of the fourth trigger;
[0026] The set end of the fourth flip-flop is connected to the aforementioned second input port, the reset end is connected to the aforementioned third input port, and the first state output end of the fourth flip-flop serves as the aforementioned second output port.
[0027] Preferably, the selection module further includes:
[0028] a third selection unit, the third selection unit having a fifth flip-flop, a fifth NOR gate, a sixth NOR gate and a sixth flip-flop,
[0029] Wherein, the set end of the fifth flip-flop is connected to the second state output end of the fifth flip-flop, the control end is connected to the second state output end of the aforementioned fourth flip-flop, and the reset end is connected to the aforementioned third input port;
[0030] The input end of the fifth NOR gate is respectively connected to the first state output end of the fifth flip-flop and the output end of the sixth NOR gate;
[0031] The input end of the sixth NOR gate is connected to the output end of the fifth NOR gate and the third input port respectively, and the output end of the sixth NOR gate is connected to the control end of the sixth trigger;
[0032] The set end of the sixth flip-flop is connected to the aforementioned second input port, the reset end is connected to the aforementioned third input port, and the first state output end of the sixth flip-flop serves as the aforementioned third output port.
[0033] Preferably, the selection module further includes:
[0034] a fourth selection unit, the fourth selection unit having a seventh flip-flop, a seventh NOR gate and an eighth NOR gate,
[0035] Wherein, the set end of the seventh flip-flop is connected to the second state output end of the seventh flip-flop, the control end is connected to the second state output end of the fifth flip-flop, and the reset end is connected to the third input port;
[0036] The input end of the seventh NOR gate is respectively connected to the first state output end of the seventh flip-flop and the output end of the eighth NOR gate;
[0037] The input end of the eighth NOR gate is respectively connected to the output end of the seventh NOR gate and the third input port, and the output end of the eighth NOR gate serves as the fourth output port.
[0038] Preferably, the clock signal generator comprises:
[0039] a second current source and a second capacitor connected in series between the power supply terminal and the ground;
[0040] A second comparator, wherein a non-inverting input terminal of the second comparator is connected to a connection node between the second current source and the second capacitor, and an inverting input terminal of the second comparator is connected to a second reference voltage;
[0041] A buffer connected between the output terminal of the second comparator and the first input port of the selection module;
[0042] A switch tube, wherein the first end of the switch tube is connected to the non-inverting input end of the second comparator, the second end is grounded, and the control end is connected to the output end of the buffer and receives the clock signal.
[0043] Preferably, any one of the first trigger, the second trigger, the third trigger, the fourth trigger, the fifth trigger, the sixth trigger and the seventh trigger is a D trigger.
[0044] On the other hand, the present disclosure provides an electronic device, comprising the port multiplexing circuit described above.
[0045] The beneficial effects of the present invention are as follows: the present disclosure provides a port multiplexing circuit for chip pins and an electronic device using the port multiplexing circuit, wherein the port multiplexing circuit comprises: a power supply module, having a first current source and a first capacitor connected in series between a power supply terminal and a ground, wherein a connection node between the first current source and the first capacitor is connected to an external port (PIN); a first comparator, wherein a non-inverting input terminal of the first comparator is connected to a connection node between the first current source and the first capacitor, an inverting input terminal is connected to a first reference voltage, and an output terminal provides a first comparison signal; a selection module, connected to the output terminal of the first comparator, having a plurality of output ports (such as High, Open, Low_Cn, Low_Ct), for selecting a first comparison signal according to the output terminal of the first comparator. The clock signal (CLK) and the aforementioned first comparison signal (VOUT) select one of the multiple output ports (High, Open, Low_Cn, Low_Ct) to be turned on. The port multiplexing circuit identifies the state of the external port (PIN) with the output result of the first comparator, and determines the different states of the output result in different cycles of the clock signal (CLK) through the selection module to determine the levels of the output signals of the ports such as High, Open, Low_Cn, Low_Ct inside the circuit. When one of the signals becomes a high level, the power-on detection is completed, thereby realizing multi-functional multiplexing of a single port, effectively reducing the number of ports on the chip, reducing the risk of electrostatic discharge (ESD), and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.
[0047] Figure 1 A schematic diagram showing the structure of a port multiplexing circuit provided by an embodiment of the present disclosure is shown;
[0048] Figure 2 Show Figure 1 A circuit diagram of a clock signal generator in a port multiplexing circuit shown;
[0049] Figure 3 Show Figure 1 A circuit diagram of a selection module in the port multiplexing circuit shown;
[0050] Figure 4 Show Figure 1 The timing diagram of each signal when the first output port in the port multiplexing circuit is turned on;
[0051] Figure 5 Show Figure 1 The timing diagram of each signal when the second output port in the port multiplexing circuit is turned on;
[0052] Figure 6 Show Figure 1 The timing diagram of each signal when the third output port in the port multiplexing circuit is turned on;
[0053] Figure 7 Show Figure 1 The timing diagram of each signal when the fourth output port in the port multiplexing circuit is turned on is shown. DETAILED DESCRIPTION
[0054] In order to facilitate the understanding of the present invention, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the content of the present disclosure more thorough and comprehensive.
[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present invention.
[0056] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.
[0057] Figure 1 A schematic diagram of the structure of a port multiplexing circuit provided by an embodiment of the present disclosure is shown. Figure 2 Show Figure 1 The circuit diagram of the clock signal generator in the port multiplexing circuit shown in FIG. Figure 3 Show Figure 1 The circuit diagram of the selection module in the port multiplexing circuit shown.
[0058] refer to Figure 1 The embodiment of the present disclosure provides a port multiplexing circuit 100 for chip pins, which at least includes: a power supply module 110, a first comparator 140 and a selection module 130,
[0059] The power supply module 110 includes a first current source Iref1 and a first capacitor C1 connected in series between a power supply terminal VDD and a ground, and a connection node between the first current source Iref1 and the first capacitor C1 is connected to an external port PIN;
[0060] The first comparator 140 has a non-inverting input terminal connected to a connection node between the first current source Iref1 and the first capacitor C1, an inverting input terminal connected to a first reference voltage Vref1, and an output terminal providing a first comparison signal VOUT;
[0061] The selection module 130 is connected to the output end of the first comparator 140 and has multiple output ports (such as High, Open, Low_Cn, Low_Ct) for selecting one of the multiple output ports (such as High, Open, Low_Cn, Low_Ct) to be turned on according to the clock signal CLK and the first comparison signal VOUT.
[0062] Furthermore, the selection module 130 has a first input port connected to the clock signal CLK, a second input port connected to the first comparison signal VOUT and a third input port connected to the reset signal POR, and the aforementioned multiple output ports include a first output port High, a second output port Open, a third output port Low_Cn and a fourth output port Low_Ct.
[0063] Furthermore, the port multiplexing circuit 100 further includes a clock signal generator 120 , and an output end of the clock signal generator 120 is connected to the selection module 130 to provide the clock signal CLK.
[0064] Furthermore, the clock signal generator 120 is, for example but not limited to, an oscillator (OSC).
[0065] In this embodiment, the oscillator 120 specifically includes: a second current source Iref2, a second capacitor C2, a second comparator 121, a buffer 122 and a switch tube T1, wherein the second current source Iref2 and the second capacitor C2 are connected in series between the power supply terminal VDD and the ground; the non-inverting input terminal of the second comparator 121 is connected to the connection node between the second current source Iref2 and the second capacitor C2, and the inverting input terminal is connected to the second reference voltage Vref2; the buffer 122 is connected between the output terminal of the second comparator 121 and the first input port of the selection module 130; the first terminal of the switch tube T1 is connected to the non-inverting input terminal of the second comparator 121, the second terminal is grounded, and the control terminal is connected to the output terminal of the buffer 122, and is connected to the clock signal CLK.
[0066] In this embodiment, for example, the second comparator 121 participating in forming the oscillator 120 has the same transmission delay as the first comparator 140, which can improve the state detection accuracy of the external port PIN, facilitate circuit design, and avoid logic errors.
[0067] refer to Figure 3 In this embodiment, the selection module 130 at least includes: a first selection unit 131 , a second selection unit 132 , a third selection unit 133 and a fourth selection unit 134 .
[0068] Specifically, in this embodiment, the first selection unit 131 has a first trigger I0, a first NOR gate I5, a second NOR gate I6 and a second trigger I7.
[0069] Among them, the set end D of the first trigger I0 is connected to the second state output end Qnot of the first trigger I0, the control end is connected to the aforementioned clock signal CLK as the aforementioned first input port, and the reset end Set is connected to the reset signal POR as the aforementioned third input port; the input end of the first NOR gate I5 is respectively connected to the first state output end Q of the first trigger I0 and the output end of the second NOR gate I6; the input end of the second NOR gate I6 is respectively connected to the output end of the first NOR gate I5 and the aforementioned third input port, and the output end of the second NOR gate I6 is connected to the control end of the second trigger I7; and the set end D of the second trigger I7 is connected to the first comparison signal VOUT as the aforementioned second input port, the reset end Set is connected to the aforementioned third input port to access the reset signal POR, and the first state output end Q of the second trigger I7 is used as the aforementioned first output port High.
[0070] In this embodiment, the second selection unit 132 has a third trigger I1, a third NOR gate I8, a fourth NOR gate I9 and a fourth trigger I10.
[0071] Among them, the set end of the third trigger I1 is connected to the second state output end Qnot of the third trigger I1, the control end is connected to the second state output end Qnot of the first trigger I0, and the reset end Set is connected to the aforementioned third input port; the input end of the third NOR gate I8 is respectively connected to the first state output end Q of the third trigger I1 and the output end of the fourth NOR gate I9; the input end of the fourth NOR gate I9 is respectively connected to the output end of the aforementioned third NOR gate I8 and the aforementioned third input port, and the output end of the fourth NOR gate I9 is connected to the control end of the aforementioned fourth trigger I10; the set end D of the fourth trigger I10 is connected to the aforementioned second input port to access the first comparison signal VOUT, the reset end Set is connected to the aforementioned third input port to access the reset signal POR, and the first state output end of the fourth trigger I10 serves as the aforementioned second output port Open.
[0072] In this embodiment, the third selection unit 133 has a fifth trigger I3, a fifth NOR gate I11, a sixth NOR gate I12 and a sixth trigger I13.
[0073] Among them, the set end D of the fifth trigger I3 is connected to the second state output end Qnot of the fifth trigger I3, the control end is connected to the second state output end Qnot of the aforementioned fourth trigger I10, the reset end Set is connected to the aforementioned third input port, and is connected to the reset signal POR; the input end of the fifth NOR gate I11 is respectively connected to the first state output end Q of the fifth trigger I3 and the output end of the sixth NOR gate I12; the input end of the sixth NOR gate I12 is respectively connected to the output end of the fifth NOR gate I11 and the aforementioned third input port, and the output end of the sixth NOR gate I12 is connected to the control end of the sixth trigger I13; the set end D of the sixth trigger I13 is connected to the aforementioned second input port to access the first comparison signal VOUT, the reset end Set is connected to the aforementioned third input port to access the reset signal POR, and the first state output end Q of the sixth trigger I13 serves as the aforementioned third output port Low_Cn.
[0074] In this embodiment, the fourth selection unit 134 has a seventh trigger I4, a seventh NOR gate I14 and an eighth NOR gate I15.
[0075] Among them, the set end D of the seventh trigger I4 is connected to the second state output end Qnot of the seventh trigger I4, the control end is connected to the second state output end Qnot of the aforementioned fifth trigger I3, the reset end Set is connected to the aforementioned third input port, and is connected to the reset signal POR; the input end of the seventh NOR gate I14 is respectively connected to the first state output end Q of the seventh trigger I4 and the output end of the eighth NOR gate I15; the input end of the eighth NOR gate I15 is respectively connected to the output end and the third input port of the seventh NOR gate I14, and the output end of the eighth NOR gate I15 serves as the aforementioned fourth output port Low_Ct.
[0076] Further, any one of the first trigger I0, the second trigger, the third trigger I1, the fourth trigger I10, the fifth trigger I3, the sixth trigger I13 and the seventh trigger I4 is a D trigger.
[0077] In this embodiment, the selection module 130 utilizes the serial input clock signal CLK and the pulse width duty cycle of the reset signal POR, and the state level of the second state output terminal Q of the current D flip-flop as the clock control signal of the next level D flip-flop to realize the parallel output of the first flip-flop I0, the third flip-flop I1, the fifth flip-flop I3 and the seventh flip-flop I4 connected in sequence, and utilizes the first state Q1 output by the first flip-flop I0, the first state Q2 output by the third flip-flop I1, the first state Q3 output by the fifth flip-flop I3 and the first state Q4 output by the seventh flip-flop I4 to complete the signal level design of the output port (such as High, Open, Low_Cn, Low_Ct) in the corresponding selection unit through multiple NOR gates and logic components of the D flip-flop. After one of the output signals becomes a high level, the power-on detection is completed and the state is latched, thereby realizing multi-functional multiplexing of a single port.
[0078] Furthermore, the third selection unit 133 can be multiplexed according to application conditions. For example, if n output states are desired, n third selection units 133 can be connected in sequence in the same connection form as shown in the above figure.
[0079] In this embodiment, the port multiplexing circuit 100 for chip pins can use the first current source Iref1 in the power supply module to charge and pull up the first capacitor C1 when the chip is powered on, so as to change the rising speed of the potential of the connection node of the first current source Iref1 and the first capacitor C1 connected to the external port PIN, use the oscillator 120 to generate the clock signal CLK, identify the state of the external port PIN by the output result (first comparison signal VOUT) of the first comparator 140, and determine the different states of the output result (first comparison signal VOUT) in different cycles of the clock signal CLK through the selection module 130 to determine the level of the output signal of the ports such as High, Open, Low_Cn, Low_Ct, etc. in the circuit. After one of the output signals becomes a high level, the power-on detection is completed and the state is latched. In this way, multi-functional multiplexing of a single port is realized, while the number of ports on the chip is effectively reduced, the risk of electrostatic discharge (ESD) is reduced, and cost can also be saved.
[0080] Figure 4 Show Figure 1 The timing diagram of each signal when the first output port in the port multiplexing circuit is turned on is shown in FIG. Figure 5 Show Figure 1 The timing diagram of each signal when the second output port in the port multiplexing circuit is turned on is shown in FIG. Figure 6 Show Figure 1 The timing diagram of each signal when the third output port in the port multiplexing circuit is turned on is shown in FIG. Figure 7 Show Figure 1 The timing diagram of each signal when the fourth output port in the port multiplexing circuit is turned on is shown.
[0081] refer to Figure 4 , when the first output port High of the port multiplexing circuit 100 is turned on and output, after the chip is powered on, the first comparison signal VOUT output by the first comparator 140 is output as 1 before the first rising edge level of the clock signal CLK. When the clock signal CLK arrives at the first rising edge, in the first selection unit 131 of the selection module 130, the state of the first state Q1 output by the first trigger I0 changes to 1, and the state of the output terminal V1 of the RS latch composed of the first NOR gate I5 and the second NOR gate I6 changes from 0 to 1, and the set terminal D of the second trigger I7 is connected to the first comparison signal VOUT, and its first state The output terminal Q serves as the first output port High of the selection module 130, and the signal of the output terminal V1 serves as the clock control signal of the second trigger I7. At this time, the first comparison signal VOUT is transmitted to the first output port High, and the state of the output signal of the first output port High becomes 1. Therefore, the state of the output signal of the output terminal V2 of the RS latch composed of the third NOR gate I8 and the fourth NOR gate I9 in the second selection unit 132 will always be 0. Therefore, the states of the output signals of the second output port Open, the third output port Low_Cn and the fourth output port Low_Ct will always be 0.
[0082] refer to Figure 5 When the second output port Open of the port multiplexing circuit 100 is turned on and the chip is powered on, the first current source Iref1 charges the first capacitor C1. If the charging time is t0, then
[0083] t0=Vref1*C1 / Iref1 (1)
[0084] In formula (1), Vref1 is the first reference voltage, C1 is the capacitance of the first capacitor C1, and Iref1 represents the reference current provided by the first current source Iref1. Without considering the transmission delay of the first comparator 140, if the period of the clock signal CLK is T1, then
[0085] T1=Vref1*C1 / Iref1 (2)
[0086] Each parameter in formula (2) represents the same as in formula (1). By setting the values of C1 and Iref1, such that T1 < t0 < 2*T1, thus, the state of the first comparison signal VOUT output by the first comparator 140 becomes 1 after the first cycle of the clock signal CLK and before the second cycle arrives. Therefore, when the state of the output terminal V1 of the RS latch formed by the first NOR gate I5 and the second NOR gate I6 changes from 0 to 1, the state of the first comparison signal VOUT is 0, which is transmitted to the first output port High, and the state of the signal output by this first output port High remains 0. While when the state of the output terminal V2 of the RS latch formed by the third NOR gate I8 and the fourth NOR gate I9 changes from 0 to 1, the state of the first comparison signal VOUT is 1, which is transmitted to the second output port Open, and the state of the signal output by this second output port Open becomes 1. Therefore, the state of the output terminal V3 of the RS latch formed by the fifth NOR gate I11 and the sixth NOR gate I12 is always 0, that is, the states of the signals output by the third output port Low_Cn and the fourth output port Low_Ct remain 0.
[0087] Wherein, after the first cycle of the clock signal CLK, the magnitude of the reference current provided by the first current source Iref1 can be appropriately increased to make the rising speed of the potential of the external port PIN faster. Because there are usually parasitic capacitances on the pins of the chip, if the parasitic capacitance is too large, when the second cycle of the clock signal CLK arrives, the potential of this external port PIN does not rise above the first reference voltage Vref1, then this first comparator 140 cannot flip, which will lead to logical errors. Therefore, the magnitude of the reference current provided by this first current source Iref1 can be appropriately increased after the first cycle of the clock signal CLK to overcome the influence of the parasitic capacitance, which can reduce the area of the first capacitor C1 and save costs.
[0088] In this embodiment, for example, the external port PIN is also connected to a capacitor (Cap) to the ground. In the following text, if time programming is not required, this externally connected capacitor (Cap) is named Cn, and when time programming is required, this externally connected capacitor (Cap) is named Ct.
[0089] Reference Figure 6 , when the third output port Low_Cn of the port multiplexing circuit 100 conducts and outputs, that is, when time programming is not required, if the charging time of this externally connected capacitor Cn is t1, then
[0090] t1 = Vref1*(Cn + C1) / Iref1 (3)
[0091] In formula (3), Cn is the capacitance value of this externally connected capacitor Cn. When (n - 1)*T1 < t1 < n*T1, such as Figure 6As shown, the state of the first comparison signal VOUT output by the first comparator 140 becomes 1 between the (n-1)*T1th cycle and the n*T1th cycle of the clock signal CLK. When the nth rising edge of the clock signal CLK comes, the state of the output signal of the third output port Low_Cn becomes 1, and the signal states of the other output ports remain 0, and the signal is latched, and the power-on detection is completed.
[0092] In this embodiment, the third selection unit 133 can be multiplexed according to the application. For example, if n output states are required, more than n third selection units 133 can be used. Figure 3 The same connection forms are connected in sequence, and the capacitance of the capacitor Cn is designed to correspond to the cycles of multiple clock signals CLK. Multiple states can be set inside the chip, enriching the chip detection function and improving the practicality of the port multiplexing circuit 100.
[0093] refer to Figure 7 , when the fourth output port Low_Ct of the port multiplexing circuit 100 is turned on for output, that is, time programming is required, the external capacitor is named Ct at this time, after the chip is powered on, after the clock signal CLK counts n cycles, the state of the first comparison signal VOUT output by the first comparator 140 is still 0, and the state of the output signal of the fourth output port Low_Ct becomes 1, at this time, the output signal of the fourth output port Low_Ct received by the chip can be used to adjust the size of the reference current provided by the first current source Iref1 and the first reference voltage Vref1 to generate the time parameter (charging time) t2 of the external capacitor Ct:
[0094] t2=Vref1*(C1+Ct) / Iref1 (4)
[0095] In formula (4), Ct is the capacitance of the external capacitor Ct. Usually, the capacitance of the external capacitor Ct is much larger than the capacitance of the first capacitor C1. Therefore, C1 can be ignored in formula (4) for simplification. If the external capacitor Ct is relatively large, after the clock signal CLK counts n cycles, the first comparator 140 still does not flip the output, then the signal output by the fourth output port LOW_Ct becomes a high level, and the signal state is latched, and the power-on detection is completed. At this time, different time parameters (charging time t2) can be obtained by adjusting the size of the capacitor Ct, thereby realizing the programming function of the time parameter.
[0096] On the other hand, the embodiments of the present disclosure also provide an electronic device (not shown), such as a mobile power supply, a vehicle power supply, etc. The electronic device includes the port multiplexing circuit 100 described in the above embodiments. The port multiplexing circuit 100 is built into the electronic device to realize multi-functional multiplexing of a single port.
[0097] In summary, the embodiment of the present disclosure provides a port multiplexing circuit 100 for chip pins and an electronic device using the port multiplexing circuit 100, wherein the port multiplexing circuit 100 includes: a power supply module 110, having a first current source Iref1 and a first capacitor C1 connected in series between a power supply terminal VDD and a ground, and a connection node between the first current source Iref1 and the first capacitor C1 is connected to an external port PIN; a first comparator 140, wherein the non-inverting input terminal of the first comparator 140 is connected to the connection node between the first current source Iref1 and the first capacitor C1, the inverting input terminal is connected to the first reference voltage Vref1, and the output terminal provides a first comparison signal VOUT; a selection module 130, connected to the output terminal of the first comparator 140, and having multiple output ports (High, Open, Low_C n, Low_Ct), is used to select one of the multiple output ports (High, Open, Low_Cn, Low_Ct) to be turned on according to the clock signal CLK and the first comparison signal VOUT. The port multiplexing circuit 100 identifies the state of the external port PIN with the first comparison signal VOUT output by the first comparator 140, and determines the different states of the first comparison signal VOUT in different cycles of the clock signal CLK through the selection module 130 to determine the levels of the output signals of the ports such as High, Open, Low_Cn, Low_Ct inside the circuit. When one of the signals becomes a high level, the power-on detection is completed, thereby realizing multi-functional multiplexing of a single port, and effectively reducing the number of ports on the chip, reducing the risk of electrostatic discharge (ESD), and saving costs.
[0098] It should be noted that in the description of the present disclosure, it needs to be understood that the terms "upper", "lower", "inner" and the like indicating orientation or positional relationship are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.
[0099] In addition, in this article, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.
[0100] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly illustrating the present disclosure, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present disclosure.
Claims
1. A port multiplexing circuit, comprising: A power supply module, comprising a first current source and a first capacitor connected in series between a power supply terminal and a ground, wherein a connection node between the first current source and the first capacitor is connected to an external port; A first comparator, wherein a non-inverting input terminal of the first comparator is connected to a connection node between the first current source and the first capacitor, an inverting input terminal is connected to a first reference voltage, and an output terminal provides a first comparison signal; A selection module is connected to the output end of the first comparator and has a plurality of output ports, and is used to select one of the plurality of output ports to be turned on according to a clock signal and the first comparison signal. Wherein, the selection module includes: A first selection unit, the first selection unit having a first trigger, a first NOR gate, a second NOR gate, and a second trigger, The set end of the first flip-flop is connected to the second state output end of the first flip-flop, the control end is used as the first input port to access the clock signal, and the reset end is used as the third input port to access the reset signal; The input end of the first NOR gate is respectively connected to the first state output end of the first trigger and the output end of the second NOR gate; The input end of the second NOR gate is connected to the output end of the first NOR gate and the third input port respectively, and the output end of the second NOR gate is connected to the control end of the second trigger; The set terminal of the second flip-flop is used as a second input port to access the first comparison signal, the reset terminal is connected to the third input port, and the first state output terminal of the second flip-flop is used as a first output port.
2. The port multiplexing circuit according to claim 1, wherein: Also includes: A clock signal generator, wherein an output end of the clock signal generator is connected to the selection module to provide the clock signal.
3. The port multiplexing circuit according to claim 2, wherein: The plurality of output ports include the first output port, a second output port, a third output port, and a fourth output port.
4. The port multiplexing circuit according to claim 3, wherein: The selection module also includes: a second selection unit, the second selection unit having a third flip-flop, a third NOR gate, a fourth NOR gate and a fourth flip-flop, The set end of the third trigger is connected to the second state output end of the third trigger, the control end is connected to the second state output end of the first trigger, and the reset end is connected to the third input port; The input end of the third NOR gate is respectively connected to the first state output end of the third trigger and the output end of the fourth NOR gate; The input end of the fourth NOR gate is respectively connected to the output end of the third NOR gate, the first state output end of the second flip-flop and the third input port, and the output end of the fourth NOR gate is connected to the control end of the fourth flip-flop; A set terminal of the fourth flip-flop is connected to the second input port, a reset terminal is connected to the third input port, and a first state output terminal of the fourth flip-flop serves as the second output port.
5. The port multiplexing circuit according to claim 4, wherein: The selection module also includes: a third selection unit, the third selection unit having a fifth flip-flop, a fifth NOR gate, a sixth NOR gate and a sixth flip-flop, The set end of the fifth flip-flop is connected to the second state output end of the fifth flip-flop, the control end is connected to the second state output end of the fourth flip-flop, and the reset end is connected to the third input port; The input end of the fifth NOR gate is respectively connected to the first state output end of the fifth trigger and the output end of the sixth NOR gate; The input end of the sixth NOR gate is respectively connected to the output end of the fifth NOR gate, the first state output end of the fourth flip-flop and the third input port, and the output end of the sixth NOR gate is connected to the control end of the sixth flip-flop; The set terminal of the sixth flip-flop is connected to the second input port, the reset terminal is connected to the third input port, and the first state output terminal of the sixth flip-flop serves as the third output port.
6. The port multiplexing circuit according to claim 5, wherein: The selection module also includes: a fourth selection unit, the fourth selection unit having a seventh flip-flop, a seventh NOR gate and an eighth NOR gate, The set end of the seventh flip-flop is connected to the second state output end of the seventh flip-flop, the control end is connected to the second state output end of the fifth flip-flop, and the reset end is connected to the third input port; The input end of the seventh NOR gate is respectively connected to the first state output end of the seventh trigger and the output end of the eighth NOR gate; The input end of the eighth NOR gate is respectively connected to the output end of the seventh NOR gate, the second state output end of the sixth trigger and the third input port, and the output end of the eighth NOR gate serves as the fourth output port.
7. The port multiplexing circuit according to claim 3, wherein: The clock signal generator comprises: a second current source and a second capacitor connected in series between the power supply terminal and the ground; A second comparator, wherein a non-inverting input terminal of the second comparator is connected to a connection node between the second current source and the second capacitor, and an inverting input terminal of the second comparator is connected to a second reference voltage; a buffer connected between the output terminal of the second comparator and the first input port of the selection module; A switch tube, wherein a first end of the switch tube is connected to the non-inverting input end of the second comparator, a second end is grounded, and a control end is connected to the output end of the buffer and receives the clock signal.
8. The port multiplexing circuit according to claim 6, wherein: Any one of the first flip-flop, the second flip-flop, the third flip-flop, the fourth flip-flop, the fifth flip-flop, the sixth flip-flop and the seventh flip-flop is a D flip-flop.
9. An electronic device comprising the port multiplexing circuit according to any one of claims 1 to 8.