Wafer level packaging structure and packaging method thereof

Abstract

A wafer-level packaging method and structure, wherein the method includes: a substrate; a passivation layer located on the substrate; a seed layer located on part of the passivation layer and a wire layer located on the seed layer, wherein the side wall of the seed layer is recessed relative to the bottom of the side wall of the wire layer; a protective layer located on the surface of the wire layer and the side wall of the seed layer; a solder resist layer located on the surface of the passivation layer, wherein the solder resist layer is also located on the surface of the protective layer. The situation where the end of the protective layer is sandwiched between the passivation layer and the solder resist layer is avoided, and the situation where metal precipitation is generated due to the pulling and deformation of the protective layer is reduced, thereby improving the reliability of device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer-level packaging structure and a packaging method thereof. Background Art

[0002] Wafer Level Packaging (WLP) is a chip packaging method. After the whole wafer is produced, it is packaged and tested directly on the wafer, and then cut into single chips, without wire bonding or glue filling. Wafer level packaging has the advantages of small package size and excellent electrical performance after packaging, and is easily compatible with wafer manufacturing and chip assembly. It can simplify the process from wafer manufacturing to product shipment and reduce overall production costs.

[0003] Rewiring (RDL) is to change the contact position (I / O pad) of the original wafer-designed IC circuit through the wafer-level metal wiring process or bump process, so that the IC can be suitable for different packaging forms. The wafer-level metal wiring process is to apply an insulating protective layer on the IC, and then define the new wire pattern by exposure and development, and then use electroplating technology to make new metal circuits to connect the original aluminum pads and new bumps or pads to achieve the purpose of circuit redistribution. The rewired metal circuit is mainly sputtered copper material, and nickel-gold or nickel-palladium-gold can also be plated on the copper circuit as needed.

[0004] However, the existing rewiring structures need to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a wafer-level packaging structure and a packaging method to improve the reliability of packaging interconnection.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a wafer-level packaging structure, including: a substrate; a passivation layer located on the substrate; a seed layer located on part of the passivation layer and a wire layer located on the seed layer, the side wall of the seed layer is recessed relative to the bottom of the side wall of the wire layer; a protective layer located on the surface of the wire layer and the side wall of the seed layer; a solder resist layer located on the surface of the passivation layer, and the solder resist layer is also located on the surface of the protective layer.

[0007] Optionally, the passivation layer exposed by the protective layer has a groove therein; and the solder resist layer is also located in the groove.

[0008] Optionally, the depth of the groove ranges from 2 μm to 4 μm.

[0009] Optionally, the depth of the seed layer sidewall recessed relative to the bottom of the wire layer sidewall is in a range of 0.3 μm to 2 μm.

[0010] Optionally, the thickness range of the passivation layer is: the thickness range of the seed layer is 1000A to 4000A; the thickness range of the wire layer is 2μm to 10μm; and the thickness range of the protective layer is 2μm to 4μm.

[0011] Optionally, the material of the passivation layer includes polyimide; the material of the seed layer includes titanium; the material of the wire layer includes copper; and the material of the protection layer includes one or both of nickel and gold.

[0012] Optionally, an angle between an extension direction of the side wall of the conductor layer and a normal direction of the substrate surface ranges from 25° to 75°.

[0013] Optionally, the substrate includes a functional device layer, a pad electrically connected to the functional device layer is exposed on the surface of the substrate, and the passivation layer exposes the pad; and the seed layer is also located on the pad.

[0014] Correspondingly, the technical solution of the present invention also provides a wafer-level packaging method, comprising: providing a substrate; forming a passivation layer on the substrate; forming a seed layer and a wire layer located on the surface of the seed layer on a portion of the surface of the passivation layer, wherein the side wall of the seed layer is recessed relative to the bottom of the side wall of the wire layer; after forming the seed layer, forming a protective layer on the surface of the wire layer and the side wall of the seed layer; after forming the protective layer, forming a solder resist layer on the surface of the passivation layer, wherein the solder resist layer is also located on the surface of the protective layer.

[0015] Optionally, the method further includes: after forming the protective layer and before forming the solder resist layer, forming a groove in the passivation layer exposed by the protective layer; the solder resist layer is also located in the groove.

[0016] Optionally, the groove formation process includes a dry etching process; the process parameters of the dry etching process include: the etching gas includes oxygen, the power range is 500W to 1000W, the gas flow range is 100sccm to 200sccm, the chamber pressure range is less than 1mTorr, and the chamber temperature range is 100℃ to 300℃.

[0017] Optionally, the depth of the groove ranges from 2 μm to 4 μm.

[0018] Optionally, the method for forming the seed layer and the wire layer includes: forming a seed material layer on the surface of the passivation layer; forming a wire material layer on the surface of the seed material layer; forming a mask layer on the surface of the wire material layer, wherein the mask layer exposes a portion of the surface of the wire material layer; etching the wire material layer and the seed material layer using the mask layer as a mask, forming the wire layer with the wire material layer, and forming the seed layer with the seed material layer; after forming the seed layer, removing the mask layer.

[0019] Optionally, the method of etching the wire material layer and the seed material layer includes: using a first etching process to etch the wire material layer and the seed material layer until the surface of the passivation layer is exposed, forming the wire layer with the wire material layer, and forming an initial seed layer with the seed material layer; using a second etching process to etch the side wall of the initial seed layer to form the seed layer.

[0020] Optionally, the first etching process includes a dry etching process; the second etching process includes a wet etching process; the process parameters of the wet etching process include: the etching solution includes an acidic solution or an alkaline solution, the acidic solution includes hydrofluoric acid, and the alkaline solution includes a mixed solution of sodium hydroxide and hydrogen peroxide.

[0021] Optionally, the method of etching the wire material layer and the seed material layer includes: using a first etching process to etch the wire material layer until the surface of the seed material layer is exposed, thereby forming the wire layer with the wire material layer; and using a second etching process to etch the seed material layer exposed by the wire layer to form the seed layer.

[0022] Optionally, the first etching process includes a dry etching process; the second etching process includes a wet etching process; the process parameters of the wet etching process include: the etching solution includes an acidic solution or an alkaline solution, the acidic solution includes hydrofluoric acid, and the alkaline solution includes a mixed solution of sodium hydroxide and hydrogen peroxide.

[0023] Optionally, the process for forming the conductor material layer includes an electroplating process; and the process for forming the seed material layer includes a physical vapor deposition process.

[0024] Optionally, the material of the passivation layer includes polyimide; the material of the seed layer includes titanium; the material of the wire layer includes copper; and the material of the protection layer includes one or both of nickel and gold.

[0025] Optionally, the process for forming the protective layer includes a chemical plating process or an electroplating process.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0027] In the wafer-level packaging method provided by the technical solution of the present invention, the side wall of the initial seed layer is etched to form a seed layer, the side wall of the seed layer is recessed relative to the bottom of the side wall of the wire layer, and a protective layer is formed on the surface of the wire layer and the side wall of the seed layer. The protective layer and the seed layer fully wrap the wire layer on all sides, thereby avoiding the situation where the end of the protective layer is sandwiched between the passivation layer and the solder resist layer, reducing the situation of metal precipitation caused by the pulling and deformation of the protective layer, and thereby improving the reliability of device performance.

[0028] Furthermore, after forming the protective layer and before forming the solder resist layer, a groove is formed in the passivation layer exposed by the conductor layer; the solder resist layer is also located in the groove, so that the interface between the passivation layer and the solder resist layer is on a different interface from the end of the protective layer, thereby reducing the probability of metal precipitation at the end of the protective layer through the interface between the passivation layer and the solder resist layer, thereby improving the reliability of device performance.

[0029] In the wafer-level packaging structure provided by the technical solution of the present invention, the protective layer is located on the surface of the wire layer and the side wall of the seed layer, and the protective layer and the seed layer fully wrap the wire layer on all sides, thereby avoiding the end of the protective layer being sandwiched between the passivation layer and the solder resist layer, reducing the metal precipitation caused by the pulling and deformation of the protective layer, and thus improving the reliability of the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 3 It is a structural schematic diagram of each step of a wafer-level packaging method;

[0031] Figures 4 to 10 is a schematic structural diagram of each step of a wafer-level packaging method according to an embodiment of the present invention;

[0032] Figure 11 to Figure 12 It is a structural schematic diagram of each step of a wafer-level packaging method according to another embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the performance of the packaging structure formed by the existing wafer-level packaging method needs to be improved. Now, a wafer-level packaging method is described and analyzed.

[0034] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0035] Figures 1 to 3 The invention is a structural schematic diagram of each step of a wafer-level packaging method.

[0036] Please refer to Figure 1, providing a substrate 101; forming a passivation layer 102 on the substrate 101; forming a titanium seed material layer (not marked in the figure) on the passivation layer 102; forming a copper material layer (not marked in the figure) on the titanium seed material layer; forming a mask layer 103 on the copper material layer, wherein the mask layer 103 exposes a portion of the surface of the copper material layer; etching the copper material layer and the titanium seed material layer using the mask layer 103 as a mask until the surface of the passivation layer 102 is exposed, forming a metal layer 104 with the copper material layer, and forming a seed layer 105 with the titanium seed material layer.

[0037] Please refer to Figure 2 After forming the metal layer 104 and the seed layer 105 , the mask layer 103 is removed; after removing the mask layer 103 , the surface of the passivation layer 102 is cleaned.

[0038] Please refer to Figure 3 , a protective layer is formed on the surface of the metal layer 104, the protective layer comprising a nickel material layer 106 and a gold material layer 107 located on the nickel material layer 106; after the protective layer is formed, a solder resist layer 108 is formed on the surface of the passivation layer 102 and the surface of the protective layer.

[0039] The above method is used in wafer-level packaging. The material of the passivation layer 102 is polyimide (PI for short). The titanium seed material layer is usually formed by a physical vapor deposition process. During the process, titanium ions are easily attached to the surface of the passivation layer 102. The cleaning process is used to remove the titanium ions on the surface of the passivation layer 102. During the cleaning process, the surface of the passivation layer 102 is etched. Since the reaction of the etching liquid is isotropic, the passivation layer 102 under the seed layer 105 may even be etched laterally, forming a pit A (such as Figure 2 The protective layer is formed by chemical plating. Due to the presence of the pit A, the protective layer has a downwardly bent end B near the side wall of the pit A (as shown in FIG. Figure 3 shown).

[0040] The thermal expansion coefficient of the protective layer is much smaller than that of the passivation layer 102 and the solder resist layer 108. In the reliability test of the package structure, under high temperature, high humidity and bias conditions, there is a large thermal expansion mismatch between the protective layer and the passivation layer 102 and the solder resist layer 108, and the metal circuit is prone to pulling and deformation, especially the end B is sandwiched between the passivation layer 102 and the solder resist layer 108, which is more likely to be pulled and deformed. Due to the pulling and deformation of the metal circuit, the protective layer is prone to metal precipitation along the bottom of the opening A (i.e., the interface between the solder resist layer 108 and the passivation layer 102), resulting in problems such as abnormal electromigration between the metal circuits of the power pin and the ground terminal (Ground, GND) pin, and current overload burning of some circuits, which reduces the reliability of device performance.

[0041] In order to solve the above problems, in a wafer-level packaging method provided by the present invention, the side wall of the initial seed layer is etched to form a seed layer, and the side wall of the seed layer is recessed relative to the bottom of the side wall of the wire layer, and a protective layer is formed on the surface of the wire layer and the side wall of the seed layer. The protective layer and the seed layer fully wrap the wire layer on all sides, thereby avoiding the situation where the end of the protective layer is sandwiched between the passivation layer and the solder resist layer, reducing the situation where the protective layer is pulled and deformed to produce metal precipitation under reliability test conditions due to the bias between adjacent circuits and under temperature and humidity conditions, thereby improving the reliability of device performance.

[0042] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 4 to 10 It is a structural schematic diagram of each step of a wafer-level packaging method according to an embodiment of the present invention.

[0044] Please refer to Figure 4 , providing a substrate 200 ; and forming a passivation layer 201 on the substrate 200 .

[0045] The substrate 200 includes a functional device layer (not shown in the figure), a pad (not shown in the figure) electrically connected to the functional device layer is exposed on the surface of the substrate 200, and the passivation layer 201 exposes the pad. Subsequently, a wire layer is formed on the passivation layer as a rewiring layer for wafer-level packaging.

[0046] The material of the passivation layer 201 includes polyimide. In this embodiment, the material of the passivation layer 201 is polyimide. In other embodiments, the material of the passivation layer can be poly(p-phenylene benzobisoxazole) or photosensitive benzocyclobutene.

[0047] The thickness of the passivation layer 201 is in a range of 5 μm to 10 μm. The thickness refers to the dimension along the normal direction of the surface of the substrate 200 .

[0048] Subsequently, a seed layer and a wire layer located on the surface of the seed layer are formed on a portion of the surface of the passivation layer 201, and the sidewall of the seed layer is recessed relative to the bottom of the sidewall of the wire layer. For the method of forming the seed layer and the wire layer, please refer to Figures 5 to 7 .

[0049] Please refer to Figure 5 , forming a seed material layer 300 on the surface of the passivation layer 201 ; forming a wire material layer 301 on the surface of the seed material layer 300 ; forming a mask layer 204 on the surface of the wire material layer 301 , wherein the mask layer 204 exposes a portion of the surface of the wire material layer 301 .

[0050] The material of the seed material layer 300 includes titanium. In this embodiment, the material of the seed material layer 300 is titanium.

[0051] The formation process of the seed material layer 300 includes a physical vapor deposition process. In this embodiment, the formation process of the seed material layer 300 is a physical vapor deposition process.

[0052] The seed material layer 300 has a thickness ranging from 1000 Å to 4000 Å.

[0053] The material of the wire material layer 301 includes copper. In this embodiment, the material of the wire material layer 301 is copper.

[0054] The forming process of the conductor material layer 301 includes an electroplating process. In this embodiment, the forming process of the conductor material layer 301 is an electroplating process.

[0055] Subsequently, the mask layer 204 is used as a mask to etch the conductor material layer 301 and the seed material layer 300, so that the conductor material layer 301 forms the conductor layer, and the seed material layer 300 forms the seed layer. In this embodiment, the method for etching the conductor material layer 301 and the seed material layer 300 can be found in Figure 6 to Figure 7 .

[0056] Please refer to Figure 6 , using a first etching process to etch the wire material layer and the seed material layer until the surface of the passivation layer 201 is exposed, forming the wire layer 203 with the wire material layer, and forming the initial seed layer 202 with the seed material layer.

[0057] Specifically, the initial seed layer 202 is also located on the bonding pad, so that the wire layer 203 is electrically connected to the bonding pad.

[0058] The first etching process includes a dry etching process, which is conducive to forming a conductive line layer 203 with a better morphology.

[0059] The angle a between the extension direction of the side wall of the conductive line layer 203 and the normal direction of the surface of the substrate 200 is in the range of 25° to 75°.

[0060] The thickness of the wire layer 203 is in a range of 2 μm to 10 μm.

[0061] The material of the wire layer 203 includes copper.

[0062] Please refer to Figure 7 , a second etching process is used to etch the sidewall of the initial seed layer 202 to form a seed layer 205, and the sidewall of the seed layer 205 is recessed relative to the bottom of the sidewall of the wire layer 203; after the seed layer 205 is formed, the mask layer 204 is removed.

[0063] The seed layer 205 is made of titanium.

[0064] The second etching process includes a wet etching process.

[0065] The process parameters of the wet etching process include: the etching solution includes an acidic solution or an alkaline solution, the acidic solution includes hydrofluoric acid, and the alkaline solution includes a mixed solution of sodium hydroxide and hydrogen peroxide. In the wet etching process, a large etching selectivity ratio is provided for the initial seed layer 202 and the passivation layer 201, thereby reducing damage to the passivation layer 201 during the etching process; a large etching selectivity ratio is provided for the initial seed layer 202 and the wire layer 203, thereby reducing damage to the wire layer 203 during the etching process.

[0066] In this embodiment, hydrofluoric acid is used as an etching solution to etch the sidewalls of the initial seed layer 202 to form the seed layer 205 .

[0067] The depth of the side wall of the seed layer 205 recessed relative to the bottom of the side wall of the wire layer 203 ranges from 0.3 μm to 2 μm.

[0068] Please refer to Figure 8 After the seed layer 205 is formed, a protective layer is formed on the surface of the wire layer 203 and the side wall of the seed layer 205 .

[0069] Since the side wall of the seed layer 205 is recessed relative to the bottom of the side wall of the conductor layer 203, the protective layer will be formed on the side wall of the seed layer 205, so that the protective layer and the seed layer 205 completely wrap the conductor layer 203 on all sides, avoiding the end of the protective layer being sandwiched between the passivation layer 201 and the solder mask layer, reducing the metal precipitation caused by the pulling and deformation of the protective layer, and thereby improving the reliability of the device performance.

[0070] The material of the protection layer includes one or both of nickel and gold.

[0071] The thickness of the protective layer ranges from 2 μm to 4 μm.

[0072] Specifically, in this embodiment, the protective layer includes a first protective layer 206 and a second protective layer 207 located on the first protective layer 206. More specifically, the material of the first protective layer 206 is nickel, and the material of the second protective layer 207 is gold; the thickness of the first protective layer ranges from 2 μm to 3.5 μm, and the thickness of the second protective layer ranges from 0.05 μm to 0.15 μm.

[0073] In another embodiment, a third protective layer is provided between the first protective layer and the second protective layer; the material of the third protective layer includes palladium; and the thickness of the third protective layer ranges from 0.2 μm to 1 μm.

[0074] The protective layer is formed by a chemical plating process or an electroplating process. In this embodiment, the protective layer is formed by an electroplating process.

[0075] After the protective layer is formed, a solder resist layer is formed on the surface of the passivation layer 201 .

[0076] In this embodiment, after forming the protective layer and before forming the solder resist layer, a groove is formed in the passivation layer exposed by the protective layer. For details, please refer to Fig. 9 In other embodiments, the groove may not be formed.

[0077] Please refer to Fig. 9 After forming the protection layer and before forming the solder resist layer, a groove 208 is formed in the passivation layer 201 exposed by the protection layer.

[0078] Subsequently, the formed solder resist layer is also located in the groove 208. The groove 208 makes the interface between the passivation layer 201 and the solder resist layer and the end of the protective layer be at different interfaces, thereby reducing the probability of metal precipitation at the end of the protective layer through the interface between the passivation layer 201 and the solder resist layer, thereby improving the reliability of device performance.

[0079] The depth of the groove 208 is in the range of 2 μm to 4 μm. The depth range is selected because it can reduce the probability of metal precipitation without affecting the performance of the passivation layer 201 .

[0080] The formation process of the groove 208 includes a dry etching process, which is conducive to forming a groove with a better morphology and improving the stability of device performance.

[0081] The process parameters of the dry etching process include: the etching gas includes oxygen, the power range is 500W to 1000W, the gas flow range is 100sccm to 200sccm, the chamber pressure range is less than 1mTorr, and the chamber temperature range is 100°C to 300°C. In this embodiment, the chamber temperature range is 100°C to 200°C. The reason for selecting the chamber temperature range is that if the chamber temperature range is greater than 300°C, the passivation layer 201 will be significantly etched laterally to form a depression, thereby reducing device performance.

[0082] Please refer to Fig.10 After the protective layer is formed, a solder resist layer 209 is formed on the surface of the passivation layer 201, and the solder resist layer 209 is also located on the surface of the protective layer.

[0083] In this embodiment, the solder resist layer 209 is also located in the groove 208 .

[0084] The solder resist layer 209 is used to prevent solder overflow in the subsequent soldering process from causing circuit short circuits, and to prevent non-soldering points from being contaminated by solder, etc., and can effectively protect the circuit from moisture.

[0085] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.10 , including: a substrate 200; a passivation layer 201 located on the substrate 200; a seed layer 205 located on a portion of the passivation layer 201 and a wire layer 203 located on the seed layer 205, wherein the side wall of the seed layer 205 is recessed relative to the bottom of the side wall of the wire layer 203; a protective layer located on the surface of the wire layer 203 and the side wall of the seed layer 205; a solder resist layer 209 located on the surface of the passivation layer 201, and the solder resist layer 209 is also located on the surface of the protective layer.

[0086] The protective layer is located on the surface of the wire layer 203 and the side wall of the seed layer 205. The protective layer and the seed layer 205 completely wrap the wire layer 203, thereby avoiding the end of the protective layer from being sandwiched between the passivation layer 201 and the solder resist layer 209, reducing the metal precipitation caused by the pulling and deformation of the protective layer, and thus improving the reliability of device performance.

[0087] In this embodiment, a groove 208 is formed in the passivation layer 201 exposed by the protective layer; and the solder resist layer 209 is also located in the groove 208 .

[0088] The depth of the groove 208 is in a range of 2 μm to 4 μm.

[0089] The depth of the side wall of the seed layer 205 recessed relative to the bottom of the side wall of the wire layer 203 ranges from 0.3 μm to 2 μm.

[0090] The thickness of the passivation layer 201 ranges from 5 μm to 10 μm; the thickness of the seed layer 205 ranges from 1000 Å to 4000 Å; the thickness of the wire layer 203 ranges from 2 μm to 10 μm; and the thickness of the protection layer ranges from 2 μm to 4 μm.

[0091] The material of the passivation layer 201 includes polyimide; the material of the seed layer 205 includes titanium; and the material of the wire layer 203 includes copper.

[0092] The material of the protection layer includes one or both of nickel and gold.

[0093] In this embodiment, the protective layer includes a first protective layer 206 and a second protective layer 207 located on the first protective layer 206. Specifically, the material of the first protective layer 206 is nickel, and the material of the second protective layer 207 is gold.

[0094] The angle between the extension direction of the side wall of the conductive line layer 203 and the normal direction of the surface of the substrate 200 is in the range of 25° to 75°.

[0095] The substrate 200 includes a functional device layer (not shown in the figure), and a pad (not shown in the figure) electrically connected to the functional device layer is exposed on the surface of the substrate 200, and the passivation layer 201 exposes the pad; the seed layer 205 is also located on the pad.

[0096] Figure 11 to Figure 12 It is a structural schematic diagram of each step of a wafer-level packaging method according to another embodiment of the present invention.

[0097] This embodiment is different from the previous embodiment in the method of etching the wire material layer and the seed material layer.

[0098] Please Figure 5 Based on this, continue to refer to Fig.11 , the wire material layer 301 is etched by a first etching process until the surface of the seed material layer 300 is exposed, and the wire material layer 301 is used to form the wire layer 302 .

[0099] In this embodiment, the first etching process includes a dry etching process.

[0100] Please refer to Fig.12 , the seed material layer 300 exposed by the wire layer 302 is etched using a second etching process to form the seed layer 303 ; after the seed layer 303 is formed, the mask layer 204 is removed.

[0101] The process parameters of the wet etching process include: the etching solution includes an acidic solution or an alkaline solution, the acidic solution includes hydrofluoric acid, and the alkaline solution includes a mixed solution of sodium hydroxide and hydrogen peroxide.

[0102] Specifically, in this embodiment, a mixed solution of sodium hydroxide and hydrogen peroxide is used to etch the seed material layer 300 exposed by the wire layer 302 .

[0103] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A wafer-level packaging structure, characterized in that: include: substrate; a passivation layer on the substrate; A seed layer located on a portion of the passivation layer and a wire layer located on the seed layer, wherein a side wall of the seed layer is recessed relative to a bottom of a side wall of the wire layer; A protective layer located on the surface of the wire layer and the side wall of the seed layer; A solder resist layer is located on the surface of the passivation layer, and the solder resist layer is also located on the surface of the protective layer, and the thermal expansion coefficient of the protective layer is smaller than the thermal expansion coefficients of the passivation layer and the solder resist layer.

2. The wafer-level packaging structure according to claim 1, characterized in that: The passivation layer exposed by the protective layer has a groove therein; the solder resist layer is also located in the groove.

3. The wafer-level packaging structure according to claim 2, characterized in that: The depth of the grooves ranges from 2 µm to 4 µm.

4. The wafer-level packaging structure according to claim 1, wherein: The depth of the seed layer sidewall recessed relative to the bottom of the wire layer sidewall is in a range of 0.3 μm to 2 μm.

5. The wafer-level packaging structure according to claim 1, wherein: The thickness of the passivation layer ranges from 5 µm to 10 µm; the thickness of the seed layer ranges from 1000 A to 4000 A; the thickness of the wire layer ranges from 2 µm to 10 µm; and the thickness of the protective layer ranges from 2 µm to 4 µm.

6. The wafer-level packaging structure according to claim 1, wherein: The material of the passivation layer includes polyimide; the material of the seed layer includes titanium; the material of the wire layer includes copper; and the material of the protection layer includes one or both of nickel and gold.

7. The wafer-level packaging structure according to claim 1, wherein: The angle between the extension direction of the side wall of the conductor layer and the normal direction of the substrate surface ranges from 25° to 75°.

8. The wafer-level packaging structure according to claim 1, wherein: The substrate comprises a functional device layer, a pad electrically connected to the functional device layer is exposed on the surface of the substrate, and the passivation layer exposes the pad; the seed layer is also located on the pad.

9. A wafer-level packaging method, characterized in that: include: providing a substrate; forming a passivation layer on the substrate; Forming a seed layer and a wire layer located on the surface of the seed layer on a portion of the surface of the passivation layer, wherein a side wall of the seed layer is recessed relative to a bottom of a side wall of the wire layer; After forming the seed layer, forming a protective layer on the surface of the wire layer and the side wall of the seed layer; After the protective layer is formed, a solder resist layer is formed on the surface of the passivation layer. The solder resist layer is also located on the surface of the protective layer. The thermal expansion coefficient of the protective layer is smaller than the thermal expansion coefficients of the passivation layer and the solder resist layer.

10. The wafer level packaging method according to claim 9, wherein: Also includes: After forming the protection layer and before forming the solder resist layer, a groove is formed in the passivation layer exposed by the protection layer; the solder resist layer is also located in the groove.

11. The wafer level packaging method according to claim 10, wherein: The groove forming process includes a dry etching process; the process parameters of the dry etching process include: the etching gas includes oxygen, the power range is 500 W to 1000 W, the gas flow range is 100 sccm to 200 sccm, the chamber pressure range is less than 1 mTorr, and the chamber temperature range is 100°C to 300°C.

12. The wafer level packaging method according to claim 10, wherein: The depth of the grooves ranges from 2 µm to 4 µm.

13. The wafer level packaging method according to claim 9, wherein: The method for forming the seed layer and the wire layer includes: forming a seed material layer on the surface of the passivation layer; forming a wire material layer on the surface of the seed material layer; forming a mask layer on the surface of the wire material layer, wherein the mask layer exposes a portion of the surface of the wire material layer; etching the wire material layer and the seed material layer using the mask layer as a mask, forming the wire layer with the wire material layer, and forming the seed layer with the seed material layer; after forming the seed layer, removing the mask layer.

14. The wafer level packaging method according to claim 13, wherein: The method for etching the wire material layer and the seed material layer includes: using a first etching process to etch the wire material layer and the seed material layer until the surface of the passivation layer is exposed, forming the wire layer with the wire material layer, and forming an initial seed layer with the seed material layer; using a second etching process to etch the side wall of the initial seed layer to form the seed layer.

15. The wafer level packaging method according to claim 14, wherein: The first etching process includes a dry etching process; the second etching process includes a wet etching process; the process parameters of the wet etching process include: the etching solution includes an acidic solution or an alkaline solution, the acidic solution includes hydrofluoric acid, and the alkaline solution includes a mixed solution of sodium hydroxide and hydrogen peroxide.

16. The wafer level packaging method according to claim 13, wherein: The method for etching the wire material layer and the seed material layer includes: using a first etching process to etch the wire material layer until the surface of the seed material layer is exposed, thereby forming the wire layer with the wire material layer; and using a second etching process to etch the seed material layer exposed by the wire layer, thereby forming the seed layer.

17. The wafer level packaging method according to claim 16, wherein: The first etching process includes a dry etching process; the second etching process includes a wet etching process; the process parameters of the wet etching process include: the etching solution includes an acidic solution or an alkaline solution, the acidic solution includes hydrofluoric acid, and the alkaline solution includes a mixed solution of sodium hydroxide and hydrogen peroxide.

18. The wafer level packaging method according to claim 13, wherein: The forming process of the conductor material layer includes an electroplating process; the forming process of the seed material layer includes a physical vapor deposition process.

19. The wafer level packaging method according to claim 9, wherein: The material of the passivation layer includes polyimide; the material of the seed layer includes titanium; the material of the wire layer includes copper; and the material of the protection layer includes one or both of nickel and gold.

20. The wafer level packaging method according to claim 9, wherein: The protective layer is formed by a chemical plating process or an electroplating process.

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