Semiconductor device and method for forming the same

Abstract

The present disclosure provides a semiconductor device and a method for forming the same, and relates to the field of semiconductor technology. The semiconductor device includes a substrate, a gate structure, and a self-aligned contact structure, wherein: the substrate includes a source and a drain; the gate structure is formed on the substrate and is located between the source and the drain; the self-aligned contact structure is formed on the substrate and includes a first contact structure, a second contact structure, and a third contact structure connected in sequence in a direction perpendicular to the substrate, the first contact structure contacts the source or the drain, and the second contact structure has a cross-sectional area in a direction parallel to the substrate that is greater than the cross-sectional area of ​​the first contact structure and the third contact structure in a direction parallel to the substrate. The semiconductor device and the method for forming the same disclosed by the present disclosure can reduce contact resistance and process difficulty.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration and fast transmission speed. With the continuous development of mobile devices, people have put forward huge demands for small size and integration of memory.

[0003] However, as the size continues to shrink, the spacing between the gate and source / drain contacts in dynamic random access memory continues to decrease, and it becomes increasingly difficult to ensure sufficient separation between the gate and source / drain contacts to avoid short circuits between the gate and source / drain contacts.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to overcome the deficiencies in the above-mentioned prior art and to provide a semiconductor device and a method for forming the same, which can reduce contact resistance and lower process difficulty.

[0006] According to one aspect of the present disclosure, there is provided a semiconductor device, comprising:

[0007] a substrate, including a source and a drain;

[0008] A gate structure, formed on the substrate and located between the source and the drain;

[0009] A self-aligned contact structure is formed on the substrate and includes a first contact structure, a second contact structure and a third contact structure connected in sequence in a direction perpendicular to the substrate, the first contact structure is in contact with the source or the drain, and the second contact structure has a cross-sectional area in a direction parallel to the substrate that is greater than the cross-sectional areas of the first contact structure and the third contact structure in a direction parallel to the substrate.

[0010] In an exemplary embodiment of the present disclosure, the second contact structure of the self-aligned contact structure includes at least a first contact segment adjacent to the first contact structure and a second contact segment adjacent to the third contact structure, wherein, in a direction parallel to the substrate, a cross-sectional area of ​​the second contact segment is greater than a cross-sectional area of ​​the first contact segment.

[0011] In an exemplary embodiment of the present disclosure, at least a portion of a sidewall of the first contact segment abuts against an edge of the gate structure.

[0012] In an exemplary embodiment of the present disclosure, an interlayer insulating layer is further included, wherein the interlayer insulating layer is formed on the substrate and covers the gate structure, and the self-aligned contact structure is formed in the interlayer insulating layer.

[0013] In an exemplary embodiment of the present disclosure, the interlayer insulating layer includes a first interlayer insulating layer, a second interlayer insulating layer and a third interlayer insulating layer stacked in sequence, the first contact structure is located in the first interlayer insulating layer, the second contact structure is located in the second interlayer insulating layer, the third contact structure is located in the third interlayer insulating layer, and the material density of the second interlayer insulating layer is less than the material density of the first interlayer insulating layer and the third interlayer insulating layer.

[0014] In an exemplary embodiment of the present disclosure, the semiconductor device further includes:

[0015] The metal wiring layer is arranged on a side of the interlayer insulating layer away from the substrate and is electrically connected to the self-aligned contact structure.

[0016] According to one aspect of the present disclosure, there is provided a method for forming a semiconductor device, comprising:

[0017] Providing a substrate, the substrate comprising a source electrode and a drain electrode;

[0018] forming a gate structure on the substrate, wherein the gate structure is located between the source and the drain;

[0019] A self-aligned contact structure is formed on the substrate, and the self-aligned contact structure includes a first contact structure, a second contact structure, and a third contact structure connected in sequence in a direction perpendicular to the substrate, the first contact structure is in contact with the source or the drain, and the cross-sectional area of ​​the second contact structure in a direction parallel to the substrate is greater than the cross-sectional areas of the first contact structure and the third contact structure in a direction parallel to the substrate.

[0020] In an exemplary embodiment of the present disclosure, the second contact structure of the self-aligned contact structure includes at least a first contact segment adjacent to the first contact structure and a second contact segment adjacent to the third contact structure, wherein, in a direction parallel to the substrate, a cross-sectional area of ​​the second contact segment is greater than a cross-sectional area of ​​the first contact segment.

[0021] In an exemplary embodiment of the present disclosure, at least a portion of a sidewall of the first contact segment abuts against an edge of the gate structure.

[0022] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0023] An interlayer insulating layer is formed on the substrate, the interlayer insulating layer covers the gate structure, and the self-aligned contact structure is formed in the interlayer insulating layer.

[0024] In an exemplary embodiment of the present disclosure, the interlayer insulating layer includes a first interlayer insulating layer, a second interlayer insulating layer and a third interlayer insulating layer stacked in sequence, the first contact structure is located in the first interlayer insulating layer, the second contact structure is located in the second interlayer insulating layer, the third contact structure is located in the third interlayer insulating layer, and the material density of the second interlayer insulating layer is less than the material density of the first interlayer insulating layer and the third interlayer insulating layer.

[0025] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0026] A metal wiring layer is formed on a side of the interlayer insulating layer facing away from the substrate, and the metal wiring layer is electrically connected to the self-aligned contact structure.

[0027] In an exemplary embodiment of the present disclosure, a self-aligned contact structure is formed on the substrate, wherein the self-aligned contact structure includes a first contact structure, a second contact structure, and a third contact structure connected in sequence in a direction perpendicular to the substrate, wherein the third contact structure contacts the source or the drain, and wherein the cross-sectional area of ​​the second contact structure in a direction parallel to the substrate is greater than the cross-sectional areas of the first contact structure and the third contact structure in a direction parallel to the substrate, including:

[0028] Forming a first interlayer insulating layer, a second interlayer insulating layer and a third interlayer insulating layer in sequence on the surface of the substrate, wherein the first interlayer insulating layer is located in a region outside the gate structure, and the second interlayer insulating layer covers the gate structure;

[0029] The first interlayer insulating layer, the second interlayer insulating layer and the third interlayer insulating layer are respectively etched to form a contact hole; the contact hole comprises a first hole segment, a second hole segment and a third hole segment which are connected in sequence, and a cross-sectional area of ​​the second hole segment in a direction parallel to the substrate is larger than a cross-sectional area of ​​the first hole segment and the third hole segment in a direction parallel to the substrate;

[0030] Conductive material is deposited in the first hole segment, the second hole segment and the third hole segment to form a self-aligned contact structure.

[0031] The semiconductor device and the method for forming the same disclosed herein can, on the one hand, separate the gate structure from the source or drain through the self-aligned contact structure, thereby reducing the risk of short circuit between the gate structure and the source or drain. On the other hand, since the cross-sectional area of ​​the second contact structure in the direction parallel to the substrate is larger than the cross-sectional area of ​​the first contact structure and the third contact structure in the direction parallel to the substrate, the lateral width of the self-aligned contact structure can be increased, which helps to reduce the contact resistance of the self-aligned contact structure; at the same time, since the size of the self-aligned contact structure is increased, the process difficulty of its formation is reduced.

[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0034] Figure 1 It is a schematic diagram of the structure of a semiconductor device in the related art.

[0035] Figure 2 It is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure.

[0036] Figure 3 FIG. 4 is a top view of a semiconductor device according to an embodiment of the present disclosure.

[0037] Figure 4 A flow chart for forming a self-aligned contact structure in a real-time manner according to the present disclosure.

[0038] Figure 5 To correspond to Figure 4 Schematic diagram of the structure after completing step S110.

[0039] Figure 6 Schematic diagram of the first hole section in the real-time method of the present disclosure.

[0040] Figure 7 Schematic diagram of the second hole section in the real-time method of the present disclosure.

[0041] Figure 8 Schematic diagram of the third hole section in the real-time method of the present disclosure.

[0042] Fig. 9 To correspond to Figure 4 A schematic diagram of the structure after completing step S130.

[0043] Fig.10 The present invention is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention.

[0044] In the figure: 100, substrate; 101, source; 102, drain; 200, gate; 300, self-aligned contact structure; 400, metal wiring layer; 1, substrate; 11, source; 12, drain; 2, gate structure; 21, film layer stack structure; 22, first gate insulating dielectric layer; 23, second gate insulating dielectric layer; 3, self-aligned contact structure; 31, first hole segment; 32, second hole segment; 33, third hole segment; 4, interlayer insulating layer; 41, first interlayer insulating layer; 42, second interlayer insulating layer; 43, third interlayer insulating layer; 5, conductor; 6, metal silicide layer. DETAILED DESCRIPTION

[0045] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0046] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0047] The terms "a", "an", "the" and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first", "second" and "third" are used only as labels and are not intended to limit the quantity of their objects.

[0048] In related technologies, such as Figure 1As shown in FIG. 1 , the semiconductor device mainly includes a substrate 100, a gate 200, a self-aligned contact structure 300 and a metal wiring layer 400, wherein the substrate 100 includes a source 101 and a drain 102, the gate 200 is located above the channel region between the source 101 and the drain 102, and the self-aligned contact structure 300 is formed on the substrate 100, and one end is in contact with the source 101 or the drain 102, and the other end is in contact with the metal wiring layer 400. However, as the size of the semiconductor device decreases, the distance between the self-aligned contact structure 300 and the gate 200 becomes shorter, which is easy to Figure 1 At the same time, in order to meet the spacing requirements between word lines and bit lines and the spacing requirements of capacitor plugs, the self-aligned contact structure 300 is narrow and the contact resistance is large.

[0049] The present disclosure provides a semiconductor device, such as Figure 2 As shown, the semiconductor device may include a substrate 1, a gate structure 2 and a self-aligned contact structure 3, wherein:

[0050] The substrate 1 may include a source electrode 11 and a drain electrode 12;

[0051] The gate structure 2 may be formed on the substrate 1 and may be located between the source 11 and the drain 12;

[0052] The self-aligned contact structure 3 can be formed on the substrate 1 and can include a first contact structure, a second contact structure and a third contact structure connected in sequence in a direction perpendicular to the substrate 1. The first contact structure can contact the source 11 or the drain 12. The cross-sectional area of ​​the second contact structure in a direction parallel to the substrate 1 can be greater than the cross-sectional areas of the first contact structure and the third contact structure in a direction parallel to the substrate 1.

[0053] The semiconductor device disclosed in the present invention can, on the one hand, separate the gate structure 2 from the source 11 or the drain 12 through the self-aligned contact structure 3, thereby reducing the risk of short circuit between the gate structure 2 and the source 11 or the drain 12. On the other hand, since the cross-sectional area of ​​the second contact structure in the direction parallel to the substrate 1 is larger than the cross-sectional area of ​​the first contact structure and the third contact structure in the direction parallel to the substrate 1, the lateral width of the self-aligned contact structure 3 can be increased, which helps to reduce the contact resistance of the self-aligned contact structure 3; at the same time, since the size of the self-aligned contact structure 3 is increased, the process difficulty of its formation is reduced.

[0054] The specific details of the semiconductor device in the embodiment of the present disclosure are described in detail below:

[0055] The substrate 1 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be silicon or other semiconductor materials. The shape and material of the substrate 1 are not particularly limited herein.

[0056] The substrate 1 may be a P-type substrate 1 or an n-type substrate 1, which may include a source 11 and a drain 12 arranged at intervals. The source 11 and the drain 12 may be doped. For example, the substrate 1 may be a P-type substrate 1, and the source 11 and the drain 12 may be n-doped to form a pn junction. For example, an n-type doping material may be doped into the source 11 and the drain 12 so that the source 11 and the drain 12 form an n-type semiconductor. The n-type doping material may be an element in the IV main group of the periodic table, for example, it may be phosphorus, and of course, it may also be a material of other elements, which will not be listed here one by one.

[0057] In one embodiment, phosphorus ions may be implanted into the source 11 and the drain 12 by ion implantation. Of course, other processes may also be used to dope the source 11 and / or the drain 12, which is not particularly limited herein.

[0058] There may be a channel region between the source 11 and the drain 12, in which current can flow. The gate structure 2 may be formed on the substrate 1 and may be located between the source 11 and the drain 12, that is, the gate structure 2 may be located in the channel region between the source 11 and the drain 12, and the current in the channel region may be controlled by the potential of the gate structure 2 to achieve a gate control function.

[0059] A gate structure 2 can be formed in the channel region of the substrate 1 by processes such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, magnetron sputtering or vacuum evaporation. The gate structure 2 may include a film layer stack structure 21 and a gate insulating dielectric layer located on the sidewalls and top of the film layer stack structure 21. The film layer stack structure 21 can be isolated from the self-aligned contact structure 3 by a non-zero distance through the gate insulating dielectric layer to reduce the risk of short circuit.

[0060] In one embodiment, there may be a plurality of gate structures 2, and the plurality of gate structures 2 may be arranged side by side on the substrate 1. The film layer stack structure 21 of each gate structure 2 may include a gate dielectric layer and a gate layer, wherein the gate dielectric layer may be formed on the substrate 1, and the gate layer may be formed on a side of the gate dielectric layer away from the substrate 1. By providing the gate dielectric layer, the physical dimension between the gate layer and the drain 12 may be increased, and the electric field between the drain 12 and the gate layer may be reduced, thereby reducing the leakage current of the drain 12.

[0061] The gate dielectric layer may be formed directly above the channel region on the substrate 1 , and may be a thin film formed on the surface of the substrate 1 , or a coating formed on the surface of the substrate 1 , which is not particularly limited herein.

[0062] The gate layer is located on the side of the gate dielectric layer away from the substrate 1, and can be used to control the electric field strength on the surface of the source 11 or the drain 12, thereby controlling the current between the source 11 and the drain 12. The gate layer can be a thin film formed on the side of the gate dielectric layer away from the substrate 1, or a coating formed on the surface of the gate dielectric layer away from the substrate 1, which is not particularly limited here.

[0063] The gate insulating dielectric layer may cover the side walls and the top of the film layer stack structure 21. In some embodiments, the gate insulating dielectric layer may be a multi-layer structure, which may include at least a first gate insulating dielectric layer 22 and a second gate insulating dielectric layer 23, wherein the first gate insulating dielectric layer 22 may be conformally attached to the side walls and the top of the film layer stack structure 21, and the second gate insulating dielectric layer 23 may be conformally attached to the surface of the first gate insulating dielectric layer 22, and the first gate insulating dielectric layer 22 and the second gate insulating dielectric layer 23 may be composed of materials with a smaller dielectric constant, which is beneficial to reduce the depletion layer electric field strength, thereby reducing the GIDL effect.

[0064] The self-aligned contact structure 3 can be formed on the substrate 1, one end of which can be in contact with the source 11 or the drain 12, and can be arranged side by side with the gate structure 2. For example, the self-aligned contact structure 3 can be arranged on one side of the gate structure 2, and can be in contact with the gate insulating dielectric layer of the gate structure 2, which helps to reduce the size of the device. At the same time, the gate layer can be isolated from the self-aligned contact structure 3 by the gate insulating dielectric layer to reduce the risk of short circuit.

[0065] The self-aligned contact structure 3 may be columnar and may extend to a side away from the substrate 1. The self-aligned contact structure 3 includes a first contact structure, a second contact structure, and a third contact structure connected in sequence in a direction perpendicular to the substrate 1, wherein: the first contact structure may contact the source 11 or the drain 12, and the cross-sectional area of ​​the second contact structure in a direction parallel to the substrate 1 may be larger than the cross-sectional areas of the first contact structure and the third contact structure in a direction parallel to the substrate 1, thereby increasing the lateral width of the self-aligned contact structure 3, which helps to reduce the contact resistance of the self-aligned contact structure 3; at the same time, due to the increase in the size of the self-aligned contact structure 3, the process difficulty of its formation can be reduced. In addition, due to the small contact area between the third contact structure and the source 11 or the drain 12, the contact resistance can be further reduced.

[0066] The first contact structure, the second contact structure and the third contact structure may be a stacked film layer structure formed by different processes, or may be an integrated structure formed by a single deposition process, which is not particularly limited herein.

[0067] The self-aligned contact structure 3 can be made of a conductive material, for example, tungsten or copper, etc., of course, it can also be other conductive materials, which are not specifically limited here. The boundary of the self-aligned contact structure 3 can be the same as or different from its internal material, which is not specifically limited here.

[0068] In one embodiment, the second contact structure of the self-aligned contact structure 3 may include at least a first contact segment and a second contact segment that are in contact with each other, wherein the first contact segment may be adjacent to the first contact structure, and the second contact segment may be adjacent to the third contact structure. In order to improve the device integration, at least part of the sidewall of the first contact segment may abut against the edge of the gate structure 2, that is, it may abut against the surface of the second gate insulating dielectric layer 23 away from the first gate insulating dielectric layer 22, and in the direction parallel to the substrate 1, the cross-sectional area of ​​the second contact segment may be greater than the cross-sectional area of ​​the first contact segment, thereby increasing the lateral width of the quasi-contact structure and reducing the contact resistance.

[0069] When there are multiple gate structures 2 , there may also be multiple self-aligned contact structures 3 , and each of the self-aligned contact structures 3 may be arranged at intervals and may be alternately distributed with each of the gate structures 2 .

[0070] In one embodiment of the present disclosure, the semiconductor device of the present disclosure may further include an interlayer insulating layer 4, which may be formed on the substrate 1 and may cover the gate structure 2. The interlayer insulating layer 4 may be formed on the substrate 1 by atomic layer deposition, chemical vapor deposition, physical vapor deposition, magnetron sputtering or vacuum evaporation.

[0071] The interlayer insulating layer 4 may be made of insulating material, and each gate structure 2 may be separated by the interlayer insulating layer 4 to reduce leakage current. For example, the material may be silicon dioxide or silicon nitride, and of course, other insulating materials may also be used, which are not listed here one by one.

[0072] The self-aligned contact structure 3 may be formed in the interlayer insulating layer 4. In one embodiment, the interlayer insulating layer 4 may include a first interlayer insulating layer 41, a second interlayer insulating layer 42, and a third interlayer insulating layer 43 which are stacked in sequence. The first interlayer insulating layer 41, the second interlayer insulating layer 42, and the third interlayer insulating layer 43 may be sequentially formed on the substrate 1 by atomic layer deposition, chemical vapor deposition, physical vapor deposition, magnetron sputtering, or vacuum evaporation. The first contact structure may be located in the first interlayer insulating layer 41, the second contact structure may be located in the second interlayer insulating layer 42, and the third contact structure may be located in the third interlayer insulating layer 43.

[0073] The material density of the second interlayer insulating layer 42 can be lower than the material density of the first interlayer insulating layer 41 and the third interlayer insulating layer 43; during the etching process of 42, the etching rate can be controlled so that the etching rate of the second interlayer insulating layer 42 is higher than the etching rate of the first interlayer insulating layer 41 and the third interlayer insulating layer 43, thereby making the cross-sectional area of ​​the second contact structure finally formed in the direction parallel to the substrate 1 larger than the cross-sectional area of ​​the first contact structure and the third contact structure in the direction parallel to the substrate 1, which can increase the lateral width of the self-aligned contact structure 3 and help reduce the contact resistance of the self-aligned contact structure 3.

[0074] In one embodiment, if Figure 4 As shown, forming a self-aligned contact structure 3 on a substrate may include the following steps:.

[0075] Step S110, forming a first interlayer insulating layer, a second interlayer insulating layer and a third interlayer insulating layer in sequence on the surface of the substrate, wherein the first interlayer insulating layer is located in a region outside the gate structure, and the second interlayer insulating layer covers the gate structure.

[0076] like Figure 5 As shown, the first interlayer insulating layer 41 may be a thin film or coating formed on the surface of the substrate 1, which is not particularly limited herein. The first interlayer insulating layer 41 may be formed in the region of the substrate 1 outside the gate structure 2 by atomic layer deposition, chemical vapor deposition, physical vapor deposition, magnetron sputtering or vacuum evaporation, and the surface of the first interlayer insulating layer 41 facing away from the substrate 1 may be lower than the surface of the gate structure 2 facing away from the substrate 1.

[0077] A second interlayer insulating layer 42 may be formed on the surface of the first interlayer insulating layer 41 facing away from the substrate 1 by magnetron sputtering. The second interlayer insulating layer 42 may cover the gate structure 2 , and in order to facilitate subsequent etching, the material density of the second interlayer insulating layer 42 may be less than the material density of the first interlayer insulating layer 41 .

[0078] The third interlayer insulating layer 43 may be formed on the side of the second interlayer insulating layer 42 away from the first interlayer insulating layer 41 by vacuum evaporation. The material density of the third interlayer insulating layer 43 may be greater than the material density of the second interlayer insulating layer 42. In the embodiment of the present disclosure, the structure after completing step S110 is as follows: Figure 5 shown.

[0079] Step S120, etching the first interlayer insulating layer, the second interlayer insulating layer and the third interlayer insulating layer respectively to form a contact hole; and the contact hole includes a first hole segment, a second hole segment and a third hole segment connected in sequence, and the cross-sectional area of ​​the second hole segment in a direction parallel to the substrate is larger than the cross-sectional areas of the first hole segment and the third hole segment in a direction parallel to the substrate.

[0080] The third interlayer insulating layer 43 may be etched to form a first hole segment 31 for forming a third contact structure. Figure 6 Specifically, an anisotropic etching process may be used to etch the third interlayer insulating layer 43. The first hole section 31 may be a through hole, and the second interlayer insulating layer 42 may be exposed.

[0081] The etching rate can be controlled at the first hole segment 31, and the second interlayer insulating layer 42 can be etched using a selective etching process to form a second hole segment 32 for forming a second contact structure. Figure 7 The etching rate of the second interlayer insulating layer 42 may be greater than the etching rate of the first interlayer insulating layer 41, and the aperture of the second hole segment 32 formed by etching may be greater than the aperture of the first hole segment 31. The second hole segment 32 may be a through hole and may expose the first interlayer insulating layer 41.

[0082] The first interlayer insulating layer 41 may be anisotropically etched at the second hole section 32 to form a third hole section 33 for forming a first contact structure. Figure 8 As shown, the third hole section 33 may be a through hole, and a side thereof facing away from the second hole section 32 may be connected to the substrate 1 .

[0083] Step S130 , depositing a conductive material in the first hole segment, the second hole segment, and the third hole segment to form a self-aligned contact structure.

[0084] Conductive materials may be deposited in the first hole segment 31, the second hole segment 32 and the third hole segment 33 by atomic layer deposition to form a self-aligned contact structure 3. The surface of the self-aligned contact structure 3 facing away from the substrate 1 may be flush with the surface of the third interlayer insulating layer 43 facing away from the substrate 1. In the embodiment of the present disclosure, the structure after completing step S130 is as follows: Fig. 9 shown.

[0085] The semiconductor device of the embodiment of the present disclosure may further include a metal silicide layer 6, such as Figure 8 As shown, the metal silicide layer 6 can be formed in the substrate 1 and can be in contact with the first contact structure to prevent poor contact between the self-aligned contact structure 3 and the source 11 or the drain 12 after a subsequent annealing process, and can be used to improve the contact reliability between the self-aligned contact structure 3 and the source 11 or the drain 12.

[0086] For example, after forming the contact hole and before forming the self-aligned contact structure 3, a metal material may be implanted in the area where the substrate 1 contacts the contact hole by an ion implantation process to form a metal silicide layer. In one embodiment, the metal material may be cobalt, and the material of the metal silicide layer 6 may be cobalt silicide. Of course, other materials may also be used, which are not particularly limited here. After forming the metal silicide layer 6, a conductive material may be deposited in the contact hole to form the self-aligned contact structure 3, and the self-aligned contact structure 3 may be in contact with and connected to the metal silicide layer 6.

[0087] It should be noted that, in the embodiment of the present disclosure, the width of the first contact structure in a direction parallel to the substrate 1 may be equal to the width of the third contact structure in a direction parallel to the substrate 1, the width of the third contact structure in a direction parallel to the substrate 1 may be smaller than the width of the second contact structure in a direction parallel to the substrate 1, the width of the second contact structure in a direction parallel to the substrate 1 may be smaller than 1.5 times the width of the third contact structure in a direction parallel to the substrate 1, and the width of the metal silicide layer 6 may be set according to the actual needs of the device.

[0088] The semiconductor device of the embodiment of the present disclosure may further include a metal wiring layer, which may be disposed on the side of the interlayer insulating layer 4 away from the substrate 1 and may include a plurality of conductors 5 arranged side by side, and the conductors 5 may be in the form of strips, such as Figure 3 The conductor 5 may be made of a conductor or semiconductor material, for example, tungsten, copper or polysilicon, etc. Each conductor 5 may be distributed corresponding to each alignment contact structure 3 and may be electrically connected to each alignment contact structure 3, respectively.

[0089] For example, a metal wiring layer can be formed on the side of the interlayer insulating layer 4 facing away from the substrate 1 by vacuum evaporation, magnetron sputtering or chemical vapor deposition, and a plurality of conductors 5 distributed side by side can be formed in the metal wiring layer by etching. Of course, each conductor 5 can also be formed by other methods, which are not listed here one by one.

[0090] The semiconductor device disclosed in the present invention may be a memory chip, such as a DRAM (Dynamic Random Access Memory). Of course, it may also be other semiconductor devices, which are not listed here one by one.

[0091] The present disclosure also provides a method for forming a semiconductor device, such as Fig.10 As shown, the forming method may include:

[0092] Step S210, providing a substrate, wherein the substrate includes a source electrode and a drain electrode;

[0093] Step S220, forming a gate structure on the substrate, wherein the gate structure is located between the source and the drain;

[0094] Step S230, forming a self-aligned contact structure on the substrate, the self-aligned contact structure comprising a first contact structure, a second contact structure and a third contact structure connected in sequence in a direction perpendicular to the substrate, the first contact structure contacts the source or the drain, and the second contact structure has a cross-sectional area in a direction parallel to the substrate that is greater than the cross-sectional areas of the first contact structure and the third contact structure in a direction parallel to the substrate.

[0095] The method for forming a semiconductor device disclosed in the present invention can, on the one hand, separate the gate structure 2 from the source 11 or the drain 12 through the self-aligned contact structure 3, thereby reducing the risk of short circuit between the gate structure 2 and the source 11 or the drain 12. On the other hand, since the cross-sectional area of ​​the second contact structure in the direction parallel to the substrate 1 is larger than the cross-sectional area of ​​the first contact structure and the third contact structure in the direction parallel to the substrate 1, the lateral width of the self-aligned contact structure 3 can be increased, which helps to reduce the contact resistance of the self-aligned contact structure 3; at the same time, since the size of the self-aligned contact structure 3 is increased, the process difficulty of its formation is reduced.

[0096] The specific details and manufacturing process of each part in the above-mentioned method for forming the semiconductor device have been described in detail in the corresponding semiconductor device, so they will not be repeated here.

[0097] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: a substrate, including a source electrode and a drain electrode; A gate structure, formed on the substrate and located between the source and the drain; a self-aligned contact structure, formed on the substrate, and comprising a first contact structure, a second contact structure, and a third contact structure connected in sequence in a direction perpendicular to the substrate, wherein the first contact structure contacts the source or the drain, and the second contact structure has a cross-sectional area in a direction parallel to the substrate that is greater than the cross-sectional areas of the first contact structure and the third contact structure in a direction parallel to the substrate; An interlayer insulating layer, the interlayer insulating layer is formed on the substrate and covers the gate structure, the self-aligned contact structure is formed in the interlayer insulating layer, the interlayer insulating layer includes a first interlayer insulating layer, a second interlayer insulating layer and a third interlayer insulating layer stacked in sequence, the first contact structure is located in the first interlayer insulating layer, the second contact structure is located in the second interlayer insulating layer, and the third contact structure is located in the third interlayer insulating layer.

2. The semiconductor device according to claim 1, wherein: The second contact structure of the self-aligned contact structure includes at least a first contact segment adjacent to the first contact structure and a second contact segment adjacent to the third contact structure, wherein in a direction parallel to the substrate, a cross-sectional area of ​​the second contact segment is greater than a cross-sectional area of ​​the first contact segment.

3. The semiconductor device according to claim 2, characterized in that At least a portion of a sidewall of the first contact segment abuts against an edge of the gate structure.

4. The semiconductor device according to claim 1, wherein: A material density of the second interlayer insulating layer is lower than a material density of the first interlayer insulating layer and the third interlayer insulating layer.

5. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: The metal wiring layer is arranged on a side of the interlayer insulating layer away from the substrate and is electrically connected to the self-aligned contact structure.

6. The semiconductor device according to claim 1, wherein: The gate structure includes a film layer stack structure and a gate insulating dielectric layer located on the sidewall and top of the film layer stack structure, and the film layer stack structure is separated from the self-aligned contact structure by the gate insulating dielectric layer.

7. The semiconductor device according to claim 6, characterized in that The gate insulating dielectric layer includes a first gate insulating dielectric layer and a second gate insulating dielectric layer, the first gate insulating dielectric layer is conformally attached to the side wall and the top of the film layer stack structure, the second gate insulating dielectric layer is conformally attached to the surface of the first gate insulating dielectric layer, and the first gate insulating dielectric layer also extends to cover a portion of the surface of the source and a portion of the drain.

8. The semiconductor device according to claim 7, characterized in that The second gate insulating dielectric layer also extends to cover a portion of the surface of the source electrode and a portion of the surface of the drain electrode.

9. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a source electrode and a drain electrode; forming a gate structure on the substrate, wherein the gate structure is located between the source and the drain; forming an interlayer insulating layer on the substrate, the interlayer insulating layer covering the gate structure, the interlayer insulating layer comprising a first interlayer insulating layer, a second interlayer insulating layer and a third interlayer insulating layer stacked in sequence; A self-aligned contact structure is formed in the interlayer insulating layer on the substrate, and the self-aligned contact structure includes a first contact structure, a second contact structure and a third contact structure connected in sequence in a direction perpendicular to the substrate, the first contact structure is located in the first interlayer insulating layer, the second contact structure is located in the second interlayer insulating layer, and the third contact structure is located in the third interlayer insulating layer. The first contact structure is in contact with the source or the drain, and the cross-sectional area of ​​the second contact structure in a direction parallel to the substrate is greater than the cross-sectional areas of the first contact structure and the third contact structure in a direction parallel to the substrate.

10. The forming method according to claim 9, characterized in that: The second contact structure of the self-aligned contact structure includes at least a first contact segment adjacent to the first contact structure and a second contact segment adjacent to the third contact structure, wherein in a direction parallel to the substrate, a cross-sectional area of ​​the second contact segment is greater than a cross-sectional area of ​​the first contact segment.

11. The forming method according to claim 10, characterized in that: At least a portion of a sidewall of the first contact segment abuts against an edge of the gate structure.

12. The forming method according to claim 9, characterized in that: A material density of the second interlayer insulating layer is lower than a material density of the first interlayer insulating layer and the third interlayer insulating layer.

13. The forming method according to claim 9, characterized in that: The forming method further comprises: A metal wiring layer is formed on a side of the interlayer insulating layer facing away from the substrate, and the metal wiring layer is electrically connected to the self-aligned contact structure.

14. The forming method according to claim 9, characterized in that: The self-aligned contact structure is formed on the substrate, wherein the self-aligned contact structure includes a first contact structure, a second contact structure, and a third contact structure connected in sequence in a direction perpendicular to the substrate, the third contact structure is in contact with the source or the drain, and the cross-sectional area of ​​the second contact structure in a direction parallel to the substrate is greater than the cross-sectional areas of the first contact structure and the third contact structure in a direction parallel to the substrate, including: Forming the first interlayer insulating layer, the second interlayer insulating layer and the third interlayer insulating layer in sequence on the surface of the substrate, wherein the first interlayer insulating layer is located in a region outside the gate structure, and the second interlayer insulating layer covers the gate structure; The first interlayer insulating layer, the second interlayer insulating layer and the third interlayer insulating layer are respectively etched to form a contact hole; the contact hole comprises a first hole segment, a second hole segment and a third hole segment which are connected in sequence, and a cross-sectional area of ​​the second hole segment in a direction parallel to the substrate is larger than a cross-sectional area of ​​the first hole segment and the third hole segment in a direction parallel to the substrate; Conductive material is deposited in the first hole segment, the second hole segment and the third hole segment to form the self-aligned contact structure.

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