A multi-channel asynchronous signal single-channel data transmission circuit based on oversampling

Abstract

The present application relates to the field of microelectronic integrated circuit technology, and in particular to a multi-channel asynchronous signal single-channel data transmission circuit based on oversampling, comprising: a multi-channel asynchronous data source, used to output multi-channel asynchronous data; a parallel-serial conversion circuit, the input end of the parallel-serial conversion circuit is connected to the output end of the multi-channel asynchronous data source, the output end of the parallel-serial conversion circuit is connected to one end of the channel, used to receive multi-channel asynchronous data input by the multi-channel asynchronous data source, and convert the multi-channel asynchronous data into single-channel serial data based on a control signal; a serial-parallel conversion circuit, the input end of the serial-parallel conversion circuit is connected to the other end of the channel, the output end of the serial-parallel conversion circuit is connected to a multi-channel data receiving end, used to receive single-channel serial data input by the channel, and input the single-channel serial data to the multi-channel data receiving end based on a control signal. The present application using the above scheme can effectively reduce the number of channels without reducing the data transmission rate and throughput rate.

Description

Technical Field

[0001] The present application relates to the technical field of microelectronic integrated circuits, and in particular to a multi-channel asynchronous signal single-channel data transmission circuit based on oversampling. Background Art

[0002] With the development of information technology, the demand for data in human society has exploded. At the same time, the requirements for data transmission systems are also developing in the direction of high speed and high concurrency. Therefore, high-speed data transmission and interface circuits have become the focus of research in recent years. However, the data source and the number of data transmission channels in the existing data transmission circuits are in a one-to-one correspondence. The more data transmission channels there are, the greater the implementation cost. Summary of the invention

[0003] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0004] To this end, the first purpose of the present application is to propose a multi-channel asynchronous signal single-channel data transmission circuit based on oversampling to solve the technical problem of reducing the number of channels without reducing the data transmission rate and throughput rate.

[0005] To achieve the above-mentioned purpose, a multi-channel asynchronous signal single-channel data transmission circuit based on oversampling is proposed in a first aspect of the present application, comprising:

[0006] Multiple asynchronous data sources, used to output multiple asynchronous data;

[0007] A parallel-to-serial conversion circuit, wherein an input end of the parallel-to-serial conversion circuit is connected to an output end of the multi-channel asynchronous data source, and an output end of the parallel-to-serial conversion circuit is connected to one end of a channel, and is used for receiving multi-channel asynchronous data inputted by the multi-channel asynchronous data source, and converting the multi-channel asynchronous data into single-channel serial data based on a control signal;

[0008] A serial-to-parallel conversion circuit, wherein the input end of the serial-to-parallel conversion circuit is connected to the other end of the channel, and the output end of the serial-to-parallel conversion circuit is connected to a multi-channel data receiving end, for receiving single-channel serial data input by the channel, and inputting the single-channel serial data to the multi-channel data receiving end based on a control signal.

[0009] Optionally, in one embodiment of the present application, the multi-channel asynchronous data source includes at least two data sources for outputting single-channel serial data; the multi-channel data receiving end includes at least two receiving ends for receiving single-channel serial data output by the data source;

[0010] Each data source corresponds to a receiving end.

[0011] Optionally, in one embodiment of the present application, the parallel-to-serial conversion circuit includes:

[0012] A data selector, wherein the input end of the data selector is connected to the output end of the multiple asynchronous data sources, and is used to receive multiple asynchronous data input by the multiple asynchronous data sources, and select and output a single serial data corresponding to any data source based on a control signal;

[0013] A trigger, wherein the input end of the trigger is connected to the output end of the data selector, and the output end of the trigger is connected to one end of the channel, and is used to transfer the single-channel serial data input by the data selector to the channel based on a control signal.

[0014] Optionally, in one embodiment of the present application, the serial-to-parallel conversion circuit includes:

[0015] A plurality of triggers connected in parallel, wherein the input end of the trigger is connected to the other end of the channel, the output end of the trigger is connected to the multi-channel data receiving end, each trigger corresponds to a receiving end, and is used to receive a single-channel serial data input by the channel, and input the single-channel serial data into the receiving end corresponding to the data source based on a control signal.

[0016] Optionally, in one embodiment of the present application, the oversampling-based multi-channel asynchronous signal single-channel data transmission circuit further includes a control circuit;

[0017] The first output end of the control circuit is connected to the control end of the data selector and the control end of the serial-to-parallel conversion circuit, and is used to output a first control signal to control the output of the data selector and the serial-to-parallel conversion circuit;

[0018] The second output end of the control circuit is connected to the control end of the trigger and is used to output a second control signal to control the output of the trigger in the parallel-to-serial conversion circuit.

[0019] Optionally, in an embodiment of the present application, the first control signal is a multi-channel clock signal, and each clock signal in the multi-channel clock signal is sequentially changed to a high level.

[0020] Optionally, in an embodiment of the present application, the first control signal is a multi-channel clock signal, and each clock signal in the multi-channel clock signal is sequentially changed to a high level, including:

[0021] The number of the multiple clock signals is the same as the number of the multiple asynchronous data; each clock signal corresponds to a data source;

[0022] When any clock signal is at a high level, the data selector outputs single-channel serial data corresponding to the data source corresponding to the high-level clock signal, and at the same time, the serial-to-parallel conversion circuit inputs the single-channel serial data into the receiving end corresponding to the data source.

[0023] Optionally, in one embodiment of the present application, when any one of the clock signals is at a high level, the serial-to-parallel conversion circuit inputs the single-channel serial data into a receiving end corresponding to the data source, including:

[0024] When any one of the clock signals is at a high level, the serial-to-parallel conversion circuit inputs the single-channel serial data into a receiving end corresponding to the data source at the falling edge of the clock signal.

[0025] Optionally, in one embodiment of the present application, the method for outputting a second control signal to control the output of a trigger in the parallel-to-serial conversion circuit includes:

[0026] The frequency of the second control signal is determined according to the following formula:

[0027] Foversample ≥ fmax*N*2*α

[0028] Wherein, Foversample is the frequency of the second control signal, fmax is the maximum oscillation frequency, N is the number of channels of multi-channel asynchronous data, α is the oversampling rate, and α≥2.

[0029] Optionally, in one embodiment of the present application, the method for outputting a second control signal to control the output of a trigger in the parallel-to-serial conversion circuit includes:

[0030] The second control signal is a periodic clock signal, and the trigger transfers the single-channel serial data input by the data selector to the channel at the rising edge of the clock in the periodic clock signal.

[0031] In summary, the multi-channel asynchronous signal single-channel data transmission circuit based on oversampling provided by the embodiment of the present application includes: a multi-channel asynchronous data source, which is used to output multi-channel asynchronous data; a parallel-serial conversion circuit, the input end of the parallel-serial conversion circuit is connected to the output end of the multi-channel asynchronous data source, and the output end of the parallel-serial conversion circuit is connected to one end of the channel, which is used to receive the multi-channel asynchronous data input by the multi-channel asynchronous data source, and convert the multi-channel asynchronous data into a single-channel serial data based on a control signal; a serial-parallel conversion circuit, the input end of the serial-parallel conversion circuit is connected to the other end of the channel, and the output end of the serial-parallel conversion circuit is connected to the multi-channel data receiving end, which is used to receive the single-channel serial data input by the channel, and input the single-channel serial data to the multi-channel data receiving end based on the control signal. The present application transmits data by multiplexing or sharing a channel through multi-channel asynchronous data, which can effectively reduce the number of channels without reducing the data transmission rate and throughput rate, can break the limitation of the traditional single channel transmission of single data, and can save the cost of introducing multiple channels.

[0032] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0034] Figure 1 A schematic diagram of a conventional four-way asynchronous data transmission method provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of the structure of a conventional pixel-level imaging readout circuit provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of a multi-channel asynchronous signal single-channel data transmission circuit based on oversampling provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of the structure of a four-way asynchronous signal single-channel data transmission circuit provided in an embodiment of the present application;

[0038] Figure 5 A timing diagram for when only one data source is used for signal transmission provided in the embodiment of the present application

[0039] Figure 6 A timing diagram for when two data sources simultaneously transmit signals is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be construed as limiting the present application. On the contrary, the embodiments of the present application include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.

[0041] According to some embodiments, in the application scenario of the data transmission circuit, it is necessary to transmit signals from multiple data sources concurrently, wherein each signal source is often asynchronous and high-speed, wherein the asynchronous means that the frequencies of the data channels are different and the arrival times are also different.

[0042] In some embodiments, taking four data sources as an example, based on a certain working mechanism, the four data sources each generate asynchronous signals DATA1-DATA4 of different frequencies, and the four asynchronous signals are transmitted to the data receiving end respectively, and finally the receiving end performs data processing respectively. According to the traditional data transmission method, the four data need to pass through four different data transmission channels on the way to realize the data transmission from the data source to the receiving end, so the data source and the number of data transmission channels are in a one-to-one correspondence, such as Figure 1 As shown, S1-S4 are data sources, D1-D4 are receiving ends, and the dotted line is the data transmission channel.

[0043] In some embodiments, in the application scenario of a data transmission circuit in a multi-layer integrated circuit of a three-dimensional package, with the rapid development of three-dimensional packaging technology in recent years, more and more people are designing electronic systems in a system-in-a-package (SIP) manner. People are no longer limited to electronic design on a single chip, but can realize vertical interconnection of multi-layer chips through TSV through holes.

[0044] For example, in imaging display circuits, as the resolution continues to increase, we need to achieve more and more pixels within a certain area limit, that is, the number of pixels per unit area continues to increase. At this time, the advantages of imaging circuits based on three-dimensional packaging emerge, because we can use chip stacking in the vertical direction to achieve continuous increase in the horizontal area. Therefore, as the number of circuit layers increases, the effective area that can be used by a single pixel also continues to grow. Traditional pixel-level imaging readout circuits such as Figure 2 As shown, Figure 2(a) is a top view of a three-dimensional packaging structure in which four pixel units independently use their own TSV through holes, where the rectangular box represents a single upper pixel unit circuit, the triangle represents a single lower pixel unit circuit, and the circular box represents the TSV through hole for signal transmission between the upper and lower chips. Each pixel unit has a TSV through hole; Figure 2 (b) is a side view of a three-dimensional packaging structure in which four pixel units independently use their own TSV through holes, wherein the horizontal boxes represent the upper and lower chips respectively, and the vertical boxes represent the TSV through holes for interconnecting the upper and lower chips, wherein each pixel unit has a TSV through hole.

[0045] However, in the existing 3D integrated circuit packaging technology, it is difficult to achieve high-density TSV interconnection inside the chip, mainly due to the following three reasons:

[0046] The first reason is that high-density through silicon vias (TSV) mean that high-density drilling is required inside the chip, so the chip stress increases greatly, the chip becomes fragile and brittle, and the chip yield and reliability are also reduced.

[0047] The second reason is that high-density TSV through holes also require high production accuracy to achieve, which requires more advanced technology and higher costs.

[0048] The third reason is that the TSV via itself also needs to occupy the area of ​​the pixel circuit. Therefore, as the pixel size continues to shrink, the proportion of TSV vias occupying the pixel layout area becomes more obvious, seriously restricting the available layout area. Taking all the above factors into consideration, it is difficult to use an independent TSV via for data transmission in each pixel.

[0049] Therefore, from a higher level, data transmission circuits are difficult to implement in the context of multi-layer integrated circuits in three-dimensional packaging. Figure 1 The illustrated method uses a separate channel for each data source to transmit data.

[0050] Example 1

[0051] Figure 3 A schematic diagram of the structure of a multi-channel asynchronous signal single-channel data transmission circuit based on oversampling provided in an embodiment of the present application.

[0052] like Figure 3 As shown, an embodiment of the present application provides a multi-channel asynchronous signal single-channel data transmission circuit based on oversampling, comprising:

[0053] Multiple asynchronous data sources, used to output multiple asynchronous data;

[0054] A parallel-to-serial conversion circuit, wherein an input end of the parallel-to-serial conversion circuit is connected to an output end of a multi-channel asynchronous data source, and an output end of the parallel-to-serial conversion circuit is connected to one end of a channel, and is used for receiving multi-channel asynchronous data inputted from the multi-channel asynchronous data source, and converting the multi-channel asynchronous data into a single-channel serial data based on a control signal;

[0055] A serial-to-parallel conversion circuit, wherein the input end of the serial-to-parallel conversion circuit is connected to the other end of the channel, and the output end of the serial-to-parallel conversion circuit is connected to the multi-channel data receiving end, for receiving single-channel serial data input by the channel, and inputting the single-channel serial data to the multi-channel data receiving end based on a control signal.

[0056] Specifically, a channel refers to a path for transmitting data signals, and the channel does not specifically refer to a fixed channel. The channel includes but is not limited to TSV vias, optical fibers, coaxial cables, etc.

[0057] In the embodiment of the present application, the multi-channel asynchronous data source includes at least two data sources for outputting single-channel serial data; the multi-channel data receiving end includes at least two receiving ends for receiving single-channel serial data output by the data source;

[0058] Each data source corresponds to a receiving end.

[0059] In an embodiment of the present application, the parallel-to-serial conversion circuit includes:

[0060] A data selector, wherein the input end of the data selector is connected to the output end of the multiple asynchronous data sources, and is used to receive multiple asynchronous data inputted from the multiple asynchronous data sources, and select and output a single serial data corresponding to any data source based on a control signal;

[0061] A trigger, the input end of the trigger is connected to the output end of the data selector, and the output end of the trigger is connected to one end of the channel, and is used to pass the single-channel serial data input by the data selector to the channel based on the control signal. In an embodiment of the present application, the number of input ends and control ends of the data selector is the number of upper-level pixel unit circuits.

[0062] In an embodiment of the present application, the serial-to-parallel conversion circuit includes:

[0063] Multiple triggers are connected in parallel, the input end of the trigger is connected to the other end of the channel, the output end of the trigger is connected to the multi-channel data receiving end, each trigger corresponds to a receiving end, which is used to receive single-channel serial data input by the channel and input the single-channel serial data into the receiving end corresponding to the data source based on the control signal.

[0064] In the embodiment of the present application, the multi-channel asynchronous signal single-channel data transmission circuit based on oversampling further includes a control circuit;

[0065] The first output end of the control circuit is connected to the control end of the data selector and the control end of the serial-to-parallel conversion circuit, and is used to output a first control signal to control the output of the data selector and the serial-to-parallel conversion circuit;

[0066] The second output end of the control circuit is connected to the control end of the trigger and is used to output a second control signal to control the output of the trigger in the parallel-to-serial conversion circuit.

[0067] Specifically, the number of input terminals and control terminals of the data selector is the number of data sources.

[0068] In the embodiment of the present application, the first control signal is a multi-channel clock signal, and each of the multi-channel clock signals is sequentially changed to a high level.

[0069] In the embodiment of the present application, the first control signal is a multi-channel clock signal, and each of the multi-channel clock signals is sequentially increased to a high level, including:

[0070] The number of multiple clock signals is the number of multiple asynchronous data; each clock signal corresponds to a data source;

[0071] When any clock signal is at a high level, the data selector outputs single-channel serial data corresponding to the data source corresponding to the high-level clock signal, and at the same time, the serial-to-parallel conversion circuit inputs the single-channel serial data into the receiving end corresponding to the data source.

[0072] In the embodiment of the present application, when any clock signal is at a high level, the serial-to-parallel conversion circuit inputs a single-channel serial data into a receiving end corresponding to the data source, including:

[0073] When any one of the clock signals is at a high level, the serial-to-parallel conversion circuit inputs the single-channel serial data into the receiving end corresponding to the data source at the falling edge of the clock signal.

[0074] It should be noted that in order to ensure that the single-channel serial data output by each data source can be transmitted without error, the frequency of the second control signal needs to be controlled so that the trigger in the parallel-to-serial conversion circuit can capture every transition edge of the multiple asynchronous data.

[0075] In an embodiment of the present application, the method for outputting a second control signal to control the output of a trigger in a parallel-to-serial conversion circuit includes:

[0076] The frequency of the second control signal is determined according to the following formula:

[0077] Foversample ≥ fmax*N*2*α

[0078] Wherein, Foversample is the frequency of the second control signal, fmax is the maximum oscillation frequency, N is the number of channels of multi-channel asynchronous data, α is the oversampling rate, and α≥2.

[0079] Specifically, if only one single-channel serial data is performing asynchronous oscillation, the maximum oscillation frequency fmax of the single-channel serial data is a known quantity.

[0080] It should be noted that in order to avoid the overlap of the transition edge of the second control signal with the transition edge of the multi-channel asynchronous data, which may cause a certain transition edge to be ignored due to the problem of setup time, a certain oversampling rate is required. The multi-channel asynchronous data is converted into single-channel serial data by "oversampling", and the single-channel serial data can be transmitted through one channel.

[0081] In an embodiment of the present application, the method for outputting a second control signal to control the output of a trigger in a parallel-to-serial conversion circuit includes:

[0082] The second control signal is a periodic clock signal. The trigger transfers the single-channel serial data input by the data selector to the channel at the rising edge of the clock in the periodic clock signal.

[0083] Specifically, the types of triggers in the parallel-to-serial conversion circuit and the types of triggers in the serial-to-parallel conversion circuit include but are not limited to D triggers (data flip-flop, DFF), T triggers, RS triggers, and JK triggers.

[0084] Take a scenario as an example, a four-way asynchronous signal single-channel data transmission circuit such as Figure 4 As shown, the multi-channel asynchronous data source includes four data sources S1-S4, and the data sources S1-S4 respectively generate data DATA1-DATA4 asynchronously and concurrently. The four data DATA1-DATA4 are connected to the four-input data selector, and the SEL1-SEL4 signals are used to control the four-input data selector to output one of the four data DATA1-DATA4. The DFF passes the output MUX0 of the four-input data selector to the channel at the rising edge of the OVERSAMPLE_CLK clock, and the four triggers DFFN in the serial-to-parallel conversion circuit transmit the data on the channel to DIV_O1-DIV_O4 at the falling edge of the clock in the SEL1-SEL4 signals. The four data DIV_O1-DIV_O4 are finally transmitted to the four receiving ends PIXEL1DOWN-PIXEL4DOWN, respectively, thereby completing the data transmission without error.

[0085] Specifically, when the SEL1 signal is at a high level, the MUXO signal outputs the A-way input signal; when the SEL2 signal is at a high level, the MUXO signal outputs the B-way input signal; when the SEL3 signal is at a high level, the MUXO signal outputs the C-way input signal; when the SEL4 signal is at a high level, the MUXO signal outputs the D-way input signal.

[0086] Specifically, the number of transition edges of DATA1 is copied to DIV_O1, the number of transition edges of DATA2 is copied to DIV_O2, the number of transition edges of DATA3 is copied to DIV_O3, and the number of transition edges of DATA4 is copied to DIV_O4.

[0087] Specifically, the timing diagram when only one data source is transmitting signals is as follows: Figure 5 As shown, the number of transition edges of DATA1 is completely presented on DIV_O1, and the data in DATA1 is transmitted without error.

[0088] Specifically, the timing diagram when two data sources transmit signals simultaneously is as follows: Figure 6 As shown, the number of transition edges of DATA1 is completely presented on DIV_O1, and the number of transition edges of DATA2 is completely presented on DIV_O2, indicating that when two data sources are transmitting signals at the same time, the data can also be transmitted without error through the multi-channel asynchronous signal single-channel data transmission circuit based on oversampling proposed in the embodiment of the present application. Similarly, when at least three signals are transmitted at the same time, the multi-channel asynchronous signal single-channel data transmission circuit based on oversampling proposed in the embodiment of the present application is still effective.

[0089] In summary, the multi-channel asynchronous signal single-channel data transmission circuit based on oversampling provided by the embodiment of the present application includes: a multi-channel asynchronous data source, which is used to output multi-channel asynchronous data; a parallel-serial conversion circuit, the input end of the parallel-serial conversion circuit is connected to the output end of the multi-channel asynchronous data source, and the output end of the parallel-serial conversion circuit is connected to one end of the channel, which is used to receive the multi-channel asynchronous data input by the multi-channel asynchronous data source, and convert the multi-channel asynchronous data into a single-channel serial data based on a control signal; a serial-parallel conversion circuit, the input end of the serial-parallel conversion circuit is connected to the other end of the channel, and the output end of the serial-parallel conversion circuit is connected to the multi-channel data receiving end, which is used to receive the single-channel serial data input by the channel, and input the single-channel serial data to the multi-channel data receiving end based on the control signal. The present application transmits data by multiplexing or sharing a channel through multi-channel asynchronous data, which can effectively reduce the number of channels without reducing the data transmission rate and throughput rate, can break the limitation of the traditional single channel transmission of single data, and can save the cost of introducing multiple channels.

[0090] It should be noted that, in the description of this application, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0091] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0092] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0093] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0094] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0095] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0096] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0097] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A multi-channel asynchronous signal single-channel data transmission circuit based on oversampling, characterized in that: include: Multiple asynchronous data sources, used to output multiple asynchronous data; A parallel-to-serial conversion circuit, wherein an input end of the parallel-to-serial conversion circuit is connected to an output end of the multi-channel asynchronous data source, and an output end of the parallel-to-serial conversion circuit is connected to one end of a channel, and is used for receiving multi-channel asynchronous data inputted by the multi-channel asynchronous data source, and converting the multi-channel asynchronous data into single-channel serial data based on a control signal; The parallel-to-serial conversion circuit includes a data selector and a trigger; The input end of the data selector is connected to the output end of the multiple asynchronous data sources, and is used to receive multiple asynchronous data input by the multiple asynchronous data sources, and select and output a single serial data corresponding to any data source in the multiple asynchronous data sources based on the control signal; The input end of the trigger in the parallel-to-serial conversion circuit is connected to the output end of the data selector, and the output end of the trigger in the parallel-to-serial conversion circuit is connected to one end of the channel, for transmitting the single-channel serial data input by the data selector to the channel based on the control signal; A serial-to-parallel conversion circuit, wherein the input end of the serial-to-parallel conversion circuit is connected to the other end of the channel, and the output end of the serial-to-parallel conversion circuit is connected to a multi-channel data receiving end, for receiving single-channel serial data input by the channel, and inputting the single-channel serial data to the multi-channel data receiving end based on a control signal; The serial-to-parallel conversion circuit includes a plurality of triggers connected in parallel, the input end of the trigger in the serial-to-parallel conversion circuit is connected to the other end of the channel, the output end of the trigger in the serial-to-parallel conversion circuit is connected to the multiple data receiving end, each trigger in the serial-to-parallel conversion circuit corresponds to one receiving end of the multiple data receiving ends, and is used to receive single-channel serial data input by the channel, and input the single-channel serial data into the receiving end corresponding to the data source based on the control signal; A control circuit, wherein a first output end of the control circuit is connected to a control end of the data selector and a control end of the serial-to-parallel conversion circuit, and is used to output a first control signal to control the output of the data selector and the serial-to-parallel conversion circuit; The second output end of the control circuit is connected to the control end of the trigger, and is used to output a second control signal to control the output of the trigger in the parallel-to-serial conversion circuit, wherein the second control signal is a periodic clock signal, and the trigger transmits the single-channel serial data input by the data selector to the channel at the rising edge of the clock in the periodic clock signal, and the frequency of the second control signal is determined according to the following formula: Foversample ≥ fmax*N*2*α Wherein, Foversample is the frequency of the second control signal, fmax is the maximum oscillation frequency, N is the number of channels of multi-channel asynchronous data, α is the oversampling rate, and α≥2.

2. The circuit according to claim 1, characterized in that The multi-channel asynchronous data source includes at least two data sources for outputting single-channel serial data; the multi-channel data receiving end includes at least two receiving ends for receiving single-channel serial data output by the data source; Each data source corresponds to a receiving end.

3. The circuit according to claim 1, characterized in that The first control signal is a multi-channel clock signal, and each of the multi-channel clock signals is sequentially changed to a high level.

4. The circuit according to claim 1, characterized in that The first control signal is a multi-channel clock signal, and each of the multi-channel clock signals is sequentially increased to a high level, including: The number of the multiple clock signals is the same as the number of the multiple asynchronous data; each clock signal corresponds to a data source; When any clock signal is at a high level, the data selector outputs single-channel serial data corresponding to the data source corresponding to the high-level clock signal, and at the same time, the serial-to-parallel conversion circuit inputs the single-channel serial data into the receiving end corresponding to the data source.

5. The circuit according to claim 4, characterized in that When any one of the clock signals is at a high level, the serial-to-parallel conversion circuit inputs the single-channel serial data into a receiving end corresponding to the data source, including: When any one of the clock signals is at a high level, the serial-to-parallel conversion circuit inputs the single-channel serial data into a receiving end corresponding to the data source at the falling edge of the clock signal.

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